mirror of https://github.com/trudnai/Steve2.git
Page Table removed
This commit is contained in:
parent
650f169f3a
commit
e00583823d
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@ -657,8 +657,8 @@
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@ -881,22 +881,6 @@
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@ -1057,22 +1041,6 @@
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@ -1217,22 +1185,6 @@
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@ -1265,22 +1217,6 @@
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@ -1393,5 +1329,69 @@
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BreakpointExtensionID = "Xcode.Breakpoint.FileBreakpoint">
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<BreakpointContent
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uuid = "86A35A38-C08C-4F86-B3CF-45B86C2579DC"
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shouldBeEnabled = "No"
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continueAfterRunningActions = "No"
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filePath = "A2Mac/ViewController.swift"
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startingLineNumber = "477"
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landmarkName = "Update()"
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</BreakpointProxy>
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||||
</Breakpoints>
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||||
</Bucket>
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||||
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@ -888,8 +888,6 @@ void rom_loadFile( const char * bundlePath, const char * filename ) {
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else if ( flen == 16 * KB ) {
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read_rom( bundlePath, filename, Apple2_16K_ROM, 0);
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memcpy(Apple2_64K_MEM + 0xC000, Apple2_16K_ROM, 16 * KB);
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// SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_16K_ROM, 0x00);
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}
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else if ( flen == 12 * KB ) {
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@ -18,8 +18,6 @@ INLINE void PUSH( uint8_t src ) {
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}
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INLINE uint8_t POP() {
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// return RAM[ stack_base_addr | ++m6502.SP ];
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// return *( RAM_PG_RD_TBL[ stack_base_addr >> 8 ] + ++m6502.SP );
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return RDLOMEM[ stack_base_addr | ++m6502.SP ];
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}
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@ -188,72 +188,6 @@ uint8_t * const WRHIMEM = Apple2_Dummy_RAM; // Pointer to the Shadow Memory
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NULL, \
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NULL
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uint8_t * RAM_PG_RD_TBL[256] = {
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// 48K main memory
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x00),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x10),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x20),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x30),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x40),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x50),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x60),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x70),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x80),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x90),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xA0),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xB0),
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// I/O Addresses
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xC0),
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// Reading from the ROM
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DEF_RAM_PAGE16( Apple2_16K_ROM, 0x10), // D0
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DEF_RAM_PAGE16( Apple2_16K_ROM, 0x20), // E0
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DEF_RAM_PAGE16( Apple2_16K_ROM, 0x30) // F0
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};
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uint8_t * RAM_PG_WR_TBL[256] = {
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// 48K main memory
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x00),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x10),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x20),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x30),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x40),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x50),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x60),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x70),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x80),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0x90),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xA0),
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xB0),
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// I/O Addresses
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// DEF_RAM_DUMMY16,
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DEF_RAM_PAGE16( Apple2_64K_MEM, 0xC0),
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// DEF_RAM_PAGE(Apple2_64K_RAM, 0xC0),
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// // SLOT ROM is non-writeable
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 01
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 02
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 03
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 04
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 05
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 06
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 07
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 08
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 09
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0A
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0B
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0C
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0D
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0E
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// DEF_RAM_PAGE(Apple2_Dummy_Page, 0), // 0F
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// NO Writing to the ROM
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DEF_RAM_DUMMY16,
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DEF_RAM_DUMMY16,
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DEF_RAM_DUMMY16,
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};
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enum slot {
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SLOT0 = 0x00,
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@ -362,46 +296,8 @@ enum mmio {
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void resetMemory() {
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// 48K main memory
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x00, Apple2_64K_MEM, 0x00)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x10, Apple2_64K_MEM, 0x10)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x20, Apple2_64K_MEM, 0x20)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x30, Apple2_64K_MEM, 0x30)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x40, Apple2_64K_MEM, 0x40)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x50, Apple2_64K_MEM, 0x50)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x60, Apple2_64K_MEM, 0x60)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x70, Apple2_64K_MEM, 0x70)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x80, Apple2_64K_MEM, 0x80)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0x90, Apple2_64K_MEM, 0x90)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xA0, Apple2_64K_MEM, 0xA0)
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xB0, Apple2_64K_MEM, 0xB0)
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// I/O Addresses
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xC0, Apple2_64K_MEM, 0xC0)
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// Reading from the ROM
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, Apple2_16K_ROM, 0x10) // D0
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_16K_ROM, 0x20) // E0
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SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_16K_ROM, 0x30) // F0
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// 48K main memory
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x00, Apple2_64K_MEM, 0x00)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x10, Apple2_64K_MEM, 0x10)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x20, Apple2_64K_MEM, 0x20)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x30, Apple2_64K_MEM, 0x30)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x40, Apple2_64K_MEM, 0x40)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x50, Apple2_64K_MEM, 0x50)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x60, Apple2_64K_MEM, 0x60)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x70, Apple2_64K_MEM, 0x70)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x80, Apple2_64K_MEM, 0x80)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0x90, Apple2_64K_MEM, 0x90)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xA0, Apple2_64K_MEM, 0xA0)
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xB0, Apple2_64K_MEM, 0xB0)
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// I/O Addresses
|
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xC0, Apple2_64K_MEM, 0xC0)
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// NO Writing to the ROM
|
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, Apple2_Dummy_RAM, 0 );
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_Dummy_RAM, 0 );
|
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SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_Dummy_RAM, 0 );
|
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|
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|
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// Reset memory configuration
|
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MEMcfg.RAM_16K = 0;
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MEMcfg.RAM_128K = 1;
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MEMcfg.RD_RAM = 0;
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@ -442,8 +338,6 @@ void textPageSelect() {
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// load the content of Video Page 2
|
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memcpy(shadow, Apple2_64K_AUX, 0x400);
|
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|
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SWITCH_VIDEO_RAM( RAM_PG_RD_TBL, 0x04, Apple2_64K_MEM, 0x04)
|
||||
SWITCH_VIDEO_RAM( RAM_PG_WR_TBL, 0x04, Apple2_64K_MEM, 0x04)
|
||||
}
|
||||
else {
|
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// save the content of Shadow Memory
|
||||
|
@ -452,8 +346,6 @@ void textPageSelect() {
|
|||
// load the content of Video Page 2
|
||||
memcpy(shadow, Apple2_64K_RAM, 0x400);
|
||||
|
||||
SWITCH_VIDEO_RAM( RAM_PG_RD_TBL, 0x04, Apple2_64K_MEM, 0x04)
|
||||
SWITCH_VIDEO_RAM( RAM_PG_WR_TBL, 0x04, Apple2_64K_MEM, 0x04)
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -473,8 +365,6 @@ void auxMemorySelect() {
|
|||
|
||||
// load the content of Aux Memory
|
||||
memcpy(Apple2_64K_MEM + 0x200, Apple2_64K_AUX, 0xA00);
|
||||
|
||||
SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_MEM );
|
||||
}
|
||||
else {
|
||||
memory = Apple2_64K_RAM + 0x200;
|
||||
|
@ -484,20 +374,17 @@ void auxMemorySelect() {
|
|||
|
||||
// load the content of Int Memory
|
||||
memcpy(Apple2_64K_MEM + 0x200, Apple2_64K_RAM, 0xA00);
|
||||
|
||||
SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_MEM );
|
||||
}
|
||||
|
||||
if ( MEMcfg.WR_AUX_MEM ) {
|
||||
SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_MEM );
|
||||
// TODO: set write table for AUX
|
||||
}
|
||||
else {
|
||||
SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_MEM );
|
||||
// TODO: set write table for RAM
|
||||
}
|
||||
}
|
||||
else {
|
||||
SWITCH_AUX_MEM( RAM_PG_RD_TBL, Apple2_64K_MEM );
|
||||
SWITCH_AUX_MEM( RAM_PG_WR_TBL, Apple2_64K_MEM );
|
||||
// TODO: set read table for RAM
|
||||
}
|
||||
|
||||
// load new content to shadow memory
|
||||
|
@ -649,9 +536,6 @@ INLINE uint8_t ioRead( uint16_t addr ) {
|
|||
memcpy(Apple2_64K_MEM + 0xD000, Apple2_64K_AUX, 0x3000);
|
||||
|
||||
// set the RAM extension to read on the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, RAM_BANK, 0x00 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_64K_AUX, 0xE0 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_64K_AUX, 0xF0 );
|
||||
break;
|
||||
|
||||
default:
|
||||
|
@ -664,9 +548,6 @@ INLINE uint8_t ioRead( uint16_t addr ) {
|
|||
memcpy(Apple2_64K_MEM + 0xD000, Apple2_16K_ROM + 0x1000, 0x3000);
|
||||
|
||||
// set the ROM to read on the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xD0, Apple2_16K_ROM, 0x10 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xE0, Apple2_16K_ROM, 0x20 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_RD_TBL, 0xF0, Apple2_16K_ROM, 0x30 );
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -678,17 +559,11 @@ INLINE uint8_t ioRead( uint16_t addr ) {
|
|||
case io_MEM_RDRAM_WRAM_1:
|
||||
MEMcfg.WR_RAM = 1;
|
||||
// set the RAM extension to read from the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, RAM_BANK, 0x00 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_64K_AUX, 0xE0 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_64K_AUX, 0xF0 );
|
||||
break;
|
||||
|
||||
default:
|
||||
MEMcfg.WR_RAM = 0;
|
||||
// set the ROM to read on the upper memory area
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xD0, Apple2_Dummy_RAM, 0 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xE0, Apple2_Dummy_RAM, 0 );
|
||||
SWITCH_RAM_PAGE16( RAM_PG_WR_TBL, 0xF0, Apple2_Dummy_RAM, 0 );
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -826,38 +701,36 @@ INLINE void ioWrite( uint16_t addr, uint8_t val ) {
|
|||
|
||||
case io_SETSTDZP:
|
||||
MEMcfg.ALT_ZP = 0;
|
||||
SWITCH_STACK_ZP(RAM_PG_RD_TBL, Apple2_64K_RAM);
|
||||
SWITCH_STACK_ZP(RAM_PG_WR_TBL, Apple2_64K_RAM);
|
||||
// TODO: set zero page table to RAM
|
||||
break;
|
||||
|
||||
case io_SETALTZP:
|
||||
MEMcfg.ALT_ZP = 1;
|
||||
SWITCH_STACK_ZP(RAM_PG_RD_TBL, Apple2_64K_AUX);
|
||||
SWITCH_STACK_ZP(RAM_PG_WR_TBL, Apple2_64K_AUX);
|
||||
// TODO: set zero page table to AUX
|
||||
break;
|
||||
|
||||
case io_SETSLOTCXROM:
|
||||
// printf("io_SETSLOTCXROM\n");
|
||||
MEMcfg.int_Cx_ROM = 0;
|
||||
SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_64K_RAM, 0xC0);
|
||||
// TODO: set Cx00 ROM area table to SLOT
|
||||
break;
|
||||
|
||||
case io_SETINTCXROM:
|
||||
// printf("io_SETINTCXROM\n");
|
||||
MEMcfg.int_Cx_ROM = 1;
|
||||
SWITCH_CX_ROM( RAM_PG_RD_TBL, 0xC0, Apple2_16K_ROM, 0x00);
|
||||
// TODO: set Cx00 ROM area table to INT
|
||||
break;
|
||||
|
||||
case io_SETSLOTC3ROM:
|
||||
// printf("io_SETSLOTC3ROM\n");
|
||||
MEMcfg.slot_C3_ROM = 1;
|
||||
SWITCH_ROM_PAGE( RAM_PG_RD_TBL, 0xC3, Apple2_64K_RAM, 0xC3);
|
||||
// TODO: set C300 ROM area table to SLOT
|
||||
break;
|
||||
|
||||
case io_SETINTC3ROM:
|
||||
// printf("io_SETINTC3ROM\n");
|
||||
MEMcfg.slot_C3_ROM = 0;
|
||||
SWITCH_ROM_PAGE( RAM_PG_RD_TBL, 0xC3, Apple2_16K_ROM, 0x03);
|
||||
// TODO: set C300 ROM area table to INT
|
||||
break;
|
||||
|
||||
case io_VID_CLR80VID:
|
||||
|
@ -914,10 +787,6 @@ INLINE void ioWrite( uint16_t addr, uint8_t val ) {
|
|||
/**
|
||||
Naive implementation of RAM read from address
|
||||
**/
|
||||
INLINE uint8_t memread8_paged( uint16_t addr ) {
|
||||
return * ( RAM_PG_RD_TBL[addr >> 8] + (addr & 0xFF) );
|
||||
// return RAM[addr];
|
||||
}
|
||||
INLINE uint8_t memread8_low( uint16_t addr ) {
|
||||
return RDLOMEM[addr];
|
||||
}
|
||||
|
@ -997,7 +866,6 @@ INLINE void memwrite( uint16_t addr, uint8_t data ) {
|
|||
ioWrite(addr, data);
|
||||
}
|
||||
else {
|
||||
// *(RAM_PG_WR_TBL[ addr >> 8 ] + (addr & 0xFF)) = data;
|
||||
memwrite8_high(addr, data);
|
||||
}
|
||||
}
|
||||
|
@ -1005,15 +873,6 @@ INLINE void memwrite( uint16_t addr, uint8_t data ) {
|
|||
memwrite8_low(addr, data);
|
||||
}
|
||||
|
||||
// // I/O or ROM or RAM EXP
|
||||
// if ( ( addr >= 0xC000 ) && ( addr < 0xC100 ) ) {
|
||||
// return ioWrite( addr, src );
|
||||
// }
|
||||
//
|
||||
// // DO NOT MAKE IT NICER! faster this way!
|
||||
// *(RAM_PG_WR_TBL[ addr >> 8 ] + (addr & 0xFF)) = src;
|
||||
//// RAM[addr] = src;
|
||||
//
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
Loading…
Reference in New Issue