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Author SHA1 Message Date
James Tauber
82de64b000 treat README as Markdown 2012-07-23 04:14:42 -04:00
James Tauber
2492947e1d made applepy.py executable 2012-04-18 07:36:57 -04:00
James Tauber
bdbc60e6e5 Merge pull request #16 from ghewgill/startpc 
Startup option to support running binary images
 2012-04-18 03:21:09 -07:00
Greg Hewgill
9ff2dbb70e add --pc switch for starting run at specific program counter 2012-04-18 07:43:19 +12:00
Greg Hewgill
4ee9b846f9 initialise display state variables in constructor 2011-10-01 08:17:38 +13:00
James Tauber
c9ecb5f31e Merge pull request #15 from ghewgill/control 
Control channel as HTTP/REST/JSON server
 2011-08-22 10:51:03 -07:00
Greg Hewgill
60acf37150 add console control utility 2011-08-21 18:30:49 +12:00
Greg Hewgill
6782a1d268 implement post to /memory in control requests 2011-08-21 18:29:42 +12:00
Greg Hewgill
80e95d114b control channel is now HTTP/REST/JSON 2011-08-20 21:46:14 +12:00
James Tauber
fad0de8cc9 Merge pull request #13 from ghewgill/socket 
Change comms to use sockets instead of stdio
 2011-08-20 01:50:43 -07:00
James Tauber
aac75ef1cb Merge pull request #14 from ghewgill/windows 
open memory files in binary mode
 2011-08-20 01:49:38 -07:00
Greg Hewgill
0604bd1515 add fileno() method to ControlHandler for better compatiblity with select() 2011-08-20 18:22:33 +12:00
Greg Hewgill
0b86a8693f disassemble show instruction bytes 2011-08-20 15:37:55 +12:00
Greg Hewgill
29b1342a47 reincarnate disassembler on control channel 2011-08-20 14:23:51 +12:00
Greg Hewgill
aee0bba7aa add dump memory command 2011-08-20 13:59:36 +12:00
Greg Hewgill
8b62860152 refactor control command processing 2011-08-20 13:59:22 +12:00
Greg Hewgill
19693bc905 start of cpu core control channel 
Currently this listens on TCP port 6502 on localhost. The protocol
is a simple text protocol, type "help" for a list of commands.
 2011-08-19 21:48:46 +12:00
Greg Hewgill
a673f8a4d4 graceful shutdown if cpu core exits 2011-08-19 21:43:12 +12:00
Greg Hewgill
9f09818aa0 abandon startup if cpu module does not start 2011-08-19 21:07:19 +12:00
Greg Hewgill
15e174c02a rename --ui switch to --bus 2011-08-19 20:30:55 +12:00
Greg Hewgill
9ffbf63716 open memory files in binary mode 2011-08-18 21:21:42 +12:00
Greg Hewgill
dcc8e9d8ce update curses UI for socket comms 2011-08-18 21:14:49 +12:00
Greg Hewgill
cd692af6f3 use sockets for comms instead of stdio 2011-08-18 21:04:11 +12:00
James Tauber
c36ad8b662 Merge pull request #12 from ghewgill/patch-1 
Mention the minimal applepy_curses.py in README
 2011-08-17 21:12:17 -07:00
Greg Hewgill
a73ab29be2 Edited README via GitHub 2011-08-19 11:40:19 +12:00
Greg Hewgill
338f8962fd Mention the minimal applepy_curses.py in README 2011-08-19 11:37:00 +12:00
James Tauber
6f1005693c Merge pull request #11 from ghewgill/cassette 
Cassette
 2011-08-16 03:59:27 -07:00
Greg Hewgill
b8c7949d8e attempt to skip to data part of tape 2011-08-16 18:22:41 +12:00
Greg Hewgill
6951db69ad finish cassette support 2011-08-16 16:41:15 +12:00
Greg Hewgill
4963eeca9d initial cassette input 2011-08-16 15:49:48 +12:00
James Tauber
360f415fc9 Merge pull request #10 from ghewgill/splitcore 
Separate CPU core and UI processes
 2011-08-15 20:10:14 -07:00
Greg Hewgill
c9c609be1d Separate CPU core and UI processes 
This is a first step toward separating the CPU core and UI.  The UI program
starts the CPU core as a subprocess and communicates through its standard input
and output. The protocol is deliberately simple at this point. Each bus request
from the core is exactly eight bytes:

    +-------------------------+
    | cpu cycle counter high  |
    +-------------------------+
    | cpu cycle counter       |
    +-------------------------+
    | cpu cycle counter       |
    +-------------------------+
    | cpu cycle counter low   |
    +-------------------------+
    | 0x00=read / 0x01=write  |
    +-------------------------+
    | address high            |
    +-------------------------+
    | address low             |
    +-------------------------+
    | value (unused for read) |
    +-------------------------+

A single-byte response from the UI is required for a read request, and a
response must not be sent for a write request.

The above protocol is expected to change. For example:

    - the UI should tell the CPU core which address ranges are of interest
    - needs ability to send memory images to the core (both ROM and RAM)

The stream communications is currently buggy because it expects that all eight
bytes will be read when requested (that is, partial reads are not handled). In
practice, this seems to work okay for the moment.

To improve portability, it may be better to communicate over TCP sockets
instead of stdin/stdout.
 2011-08-16 12:54:23 +12:00
James Tauber
7c657a8dd8 removed unused import 2011-08-15 09:41:58 -04:00
James Tauber
a2fcbd5238 adjusted speaker sample length to allow for leading edge 2011-08-15 09:37:32 -04:00
James Tauber
fbd213e240 made options...um...optional param to Memory so tests pass 2011-08-15 09:34:49 -04:00
James Tauber
cba0ce064c Merge branch 'options' 2011-08-15 09:28:19 -04:00
James Tauber
51acc8e156 Merge branch 'master' into options 
Conflicts:
	applepy.py
 2011-08-15 09:27:53 -04:00
James Tauber
882e8478f8 Merge pull request #8 from ghewgill/arrowkeys 
map left/right arrow keys to ^H/^U
 2011-08-15 06:18:52 -07:00
James Tauber
2b1680a6a7 Merge pull request #7 from ghewgill/flash 
add flash attribute to text mode
 2011-08-15 06:17:44 -07:00
Greg Hewgill
8827db4f6a command line options: --rom, --ram, --quiet 2011-08-15 22:47:16 +12:00
Greg Hewgill
a543112ee9 map left/right arrow keys to ^H/^U 2011-08-15 22:19:03 +12:00
Greg Hewgill
27d7a717dc add flash attribute to text mode 2011-08-15 21:58:10 +12:00
James Tauber
b9033a459a moved speaker buffer playing into the Speaker class 2011-08-15 02:30:28 -04:00
James Tauber
96787a2667 Merge branch 'cycles' 2011-08-15 02:23:25 -04:00
James Tauber
4dd414dea8 implemented speaker; not a bad hack :-) 2011-08-15 02:22:58 -04:00
James Tauber
35c0e69991 pass in None for cycles so tests run 2011-08-15 00:26:52 -04:00
James Tauber
be91422317 refactored memory access so cycle can be passed in 2011-08-15 00:21:20 -04:00
James Tauber
a92dcfecd3 implemented cycle calculation (except for page boundary crossing) 2011-08-14 23:50:34 -04:00
James Tauber
1159cef81c added notes on implementation that seems to give the right result 2011-08-14 23:45:10 -04:00
James Tauber
e2211e4189 more groking of why memory-based ASL, DEC, INC, LSR, ROL and ROR take what they take 2011-08-14 21:50:55 -04:00