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Fix BRA imm instruction, add 0xD2 - CMP (zpg)

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I thought 0x80 was a weird NOP imm, but it's BRA.

Implement 0xD2 - CMP (zpg)

Move all 65C02 instruction implementations together

Update disassembler for 0xD2 - CMP (zpg)
This commit is contained in:
Brad Grantham 2018-08-10 23:25:20 -07:00
parent a2b96de667
commit 8e47791e12
2 changed files with 51 additions and 37 deletions
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86
apple2e.cpp
View File

@ -1526,11 +1526,6 @@ struct CPU6502
break;
}
case 0x80: { // NOP imm (Choplifter?)
read_pc_inc(bus);
break;
}
case 0x8A: { // TXA
set_flags(N | Z, a = x);
break;
@ -2155,11 +2150,6 @@ struct CPU6502
break;
}
case 0xDA: { // PHX
stack_push(bus, x);
break;
}
case 0x01: { // ORA (ind, X)
unsigned char zpg = (read_pc_inc(bus) + x) & 0xFF;
int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
@ -2210,14 +2200,6 @@ struct CPU6502
break;
}
case 0x12: { // ORA (ind), 65C02 instruction
unsigned char zpg = read_pc_inc(bus);
int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
m = bus.read(addr);
set_flags(N | Z, a = a | m);
break;
}
case 0x05: { // ORA zpg
unsigned char zpg = read_pc_inc(bus);
m = bus.read(zpg);
@ -2701,18 +2683,6 @@ struct CPU6502
break;
}
case 0x9C: { // STZ abs
int addr = read_pc_inc(bus) + read_pc_inc(bus) * 256;
bus.write(addr, 0x0);
break;
}
case 0x64: { // STZ zpg
unsigned char zpg = read_pc_inc(bus);
bus.write(zpg, 0);
break;
}
case 0x8E: { // STX abs
int addr = read_pc_inc(bus) + read_pc_inc(bus) * 256;
bus.write(addr, x);
@ -2745,21 +2715,48 @@ struct CPU6502
break;
}
case 0xB2: { // LDA (zpg), 65C02 instruction
// 65C02 instructions
case 0x80: { // BRA imm, 65C02
int rel = (read_pc_inc(bus) + 128) % 256 - 128;
if((pc + rel) / 256 != pc / 256)
clk.add_cpu_cycles(1);
pc += rel;
break;
}
case 0x64: { // STZ zpg, 65C02
unsigned char zpg = read_pc_inc(bus);
bus.write(zpg, 0);
break;
}
case 0x9C: { // STZ abs, 65C02
int addr = read_pc_inc(bus) + read_pc_inc(bus) * 256;
bus.write(addr, 0x0);
break;
}
case 0xDA: { // PHX, 65C02
stack_push(bus, x);
break;
}
case 0xB2: { // LDA (zpg), 65C02
unsigned char zpg = read_pc_inc(bus);
int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
set_flags(N | Z, a = bus.read(addr));
break;
}
case 0x92: { // STA (zpg), 65C02 instruction
case 0x92: { // STA (zpg), 65C02
unsigned char zpg = read_pc_inc(bus);
int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
bus.write(addr, a);
break;
}
case 0x72: { // ADC (zpg), 65C02 instruction
case 0x72: { // ADC (zpg), 65C02
unsigned char zpg = read_pc_inc(bus);
int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
@ -2779,16 +2776,33 @@ struct CPU6502
break;
}
case 0x3A: { // DEC, 65C02 instruction
case 0x3A: { // DEC, 65C02
set_flags(N | Z, a = a - 1);
break;
}
case 0x1A: { // INC, 65C02 instruction
case 0x1A: { // INC, 65C02
set_flags(N | Z, a = a + 1);
break;
}
case 0x12: { // ORA (ind), 65C02
unsigned char zpg = read_pc_inc(bus);
int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
m = bus.read(addr);
set_flags(N | Z, a = a | m);
break;
}
case 0xD2: { // CMP (zpg), 65C02 instruction
unsigned char zpg = read_pc_inc(bus);
int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
m = bus.read(addr);
flag_change(C, m <= a);
set_flags(N | Z, m = a - m);
break;
}
default:
printf("unhandled instruction %02X at %04X\n", inst, pc - 1);
fflush(stdout); exit(1);
@ -2831,7 +2845,7 @@ int CPU6502::cycles[256] =
/* 0xA- */ 2, 6, 2, -1, 3, 3, 3, -1, 2, 2, 2, -1, 4, 4, 4, -1,
/* 0xB- */ 2, 5, 5, -1, 4, 4, 4, -1, 2, 4, 2, -1, 4, 4, 4, -1,
/* 0xC- */ 2, 6, -1, -1, 3, 3, 5, -1, 2, 2, 2, -1, 4, 4, 3, -1,
/* 0xD- */ 2, 5, -1, -1, -1, 4, 6, -1, 2, 4, 3, -1, -1, 4, 7, -1,
/* 0xD- */ 2, 5, 5, -1, -1, 4, 6, -1, 2, 4, 3, -1, -1, 4, 7, -1,
/* 0xE- */ 2, 6, -1, -1, 3, 3, 5, -1, 2, 2, 2, -1, 4, 4, 6, -1,
/* 0xF- */ 2, 5, -1, -1, -1, 4, 6, -1, 2, 4, -1, -1, -1, 4, 7, -1,
};

2
dis6502.cpp
View File

@ -55,7 +55,7 @@ tuple<int, string> disassemble_6502(int address, const unsigned char* buffer)
{2,31,1},{2,29,4},{2,30,1},{1,69,0},{2,31,0},{2,29,0},{2,30,0},{1,69,0},{1,52,0},{2,29,1},{1,51,0},{1,69,0},{3,31,0},{3,29,0},{3,30,0},{1,69,0}, // A
{2,4,8}, {2,29,5},{2,29,0},{1,69,0},{2,31,2},{2,29,2},{2,30,3},{1,69,0},{1,16,0},{3,29,3},{1,53,0},{1,69,0},{3,31,2},{3,29,2},{3,30,3},{1,69,0}, // B
{2,19,1},{2,17,4},{1,69,0},{1,69,0},{2,19,0},{2,17,0},{2,20,0},{1,69,0},{1,26,0},{2,17,1},{1,21,0},{1,69,0},{3,19,0},{3,17,0},{3,20,0},{1,69,0}, // C
{2,8,8}, {2,17,5},{1,69,0},{1,69,0},{1,69,0},{2,17,2},{2,20,2},{1,69,0},{1,14,0},{3,17,3},{1,58,0},{1,69,0},{1,69,0},{3,17,2},{3,20,2},{1,69,0}, // D
{2,8,8}, {2,17,5},{2,17,0},{1,69,0},{1,69,0},{2,17,2},{2,20,2},{1,69,0},{1,14,0},{3,17,3},{1,58,0},{1,69,0},{1,69,0},{3,17,2},{3,20,2},{1,69,0}, // D
{2,18,1},{2,44,4},{1,69,0},{1,69,0},{2,18,0},{2,44,0},{2,24,0},{1,69,0},{1,25,0},{2,44,1},{1,33,0},{1,69,0},{3,18,0},{3,44,0},{3,24,0},{1,69,0}, // E
{2,5,8}, {2,44,5},{1,69,0},{1,69,0},{1,69,0},{2,44,2},{2,24,2},{1,69,0},{1,46,0},{3,44,3},{1,69,0},{1,69,0},{1,69,0},{3,44,2},{3,24,2},{1,69,0} // F
};