Fix BRA imm instruction, add 0xD2 - CMP (zpg)
I thought 0x80 was a weird NOP imm, but it's BRA. Implement 0xD2 - CMP (zpg) Move all 65C02 instruction implementations together Update disassembler for 0xD2 - CMP (zpg)
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a2b96de667
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8e47791e12
86
apple2e.cpp
86
apple2e.cpp
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@ -1526,11 +1526,6 @@ struct CPU6502
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break;
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break;
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}
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}
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case 0x80: { // NOP imm (Choplifter?)
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read_pc_inc(bus);
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break;
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}
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case 0x8A: { // TXA
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case 0x8A: { // TXA
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set_flags(N | Z, a = x);
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set_flags(N | Z, a = x);
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break;
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break;
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@ -2155,11 +2150,6 @@ struct CPU6502
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break;
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break;
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}
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}
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case 0xDA: { // PHX
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stack_push(bus, x);
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break;
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}
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case 0x01: { // ORA (ind, X)
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case 0x01: { // ORA (ind, X)
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unsigned char zpg = (read_pc_inc(bus) + x) & 0xFF;
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unsigned char zpg = (read_pc_inc(bus) + x) & 0xFF;
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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@ -2210,14 +2200,6 @@ struct CPU6502
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break;
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break;
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}
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}
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case 0x12: { // ORA (ind), 65C02 instruction
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unsigned char zpg = read_pc_inc(bus);
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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m = bus.read(addr);
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set_flags(N | Z, a = a | m);
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break;
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}
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case 0x05: { // ORA zpg
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case 0x05: { // ORA zpg
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unsigned char zpg = read_pc_inc(bus);
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unsigned char zpg = read_pc_inc(bus);
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m = bus.read(zpg);
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m = bus.read(zpg);
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@ -2701,18 +2683,6 @@ struct CPU6502
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break;
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break;
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}
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}
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case 0x9C: { // STZ abs
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int addr = read_pc_inc(bus) + read_pc_inc(bus) * 256;
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bus.write(addr, 0x0);
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break;
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}
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case 0x64: { // STZ zpg
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unsigned char zpg = read_pc_inc(bus);
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bus.write(zpg, 0);
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break;
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}
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case 0x8E: { // STX abs
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case 0x8E: { // STX abs
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int addr = read_pc_inc(bus) + read_pc_inc(bus) * 256;
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int addr = read_pc_inc(bus) + read_pc_inc(bus) * 256;
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bus.write(addr, x);
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bus.write(addr, x);
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@ -2745,21 +2715,48 @@ struct CPU6502
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break;
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break;
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}
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}
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case 0xB2: { // LDA (zpg), 65C02 instruction
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// 65C02 instructions
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case 0x80: { // BRA imm, 65C02
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int rel = (read_pc_inc(bus) + 128) % 256 - 128;
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if((pc + rel) / 256 != pc / 256)
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clk.add_cpu_cycles(1);
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pc += rel;
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break;
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}
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case 0x64: { // STZ zpg, 65C02
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unsigned char zpg = read_pc_inc(bus);
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bus.write(zpg, 0);
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break;
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}
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case 0x9C: { // STZ abs, 65C02
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int addr = read_pc_inc(bus) + read_pc_inc(bus) * 256;
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bus.write(addr, 0x0);
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break;
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}
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case 0xDA: { // PHX, 65C02
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stack_push(bus, x);
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break;
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}
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case 0xB2: { // LDA (zpg), 65C02
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unsigned char zpg = read_pc_inc(bus);
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unsigned char zpg = read_pc_inc(bus);
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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set_flags(N | Z, a = bus.read(addr));
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set_flags(N | Z, a = bus.read(addr));
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break;
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break;
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}
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}
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case 0x92: { // STA (zpg), 65C02 instruction
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case 0x92: { // STA (zpg), 65C02
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unsigned char zpg = read_pc_inc(bus);
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unsigned char zpg = read_pc_inc(bus);
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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bus.write(addr, a);
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bus.write(addr, a);
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break;
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break;
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}
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}
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case 0x72: { // ADC (zpg), 65C02 instruction
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case 0x72: { // ADC (zpg), 65C02
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unsigned char zpg = read_pc_inc(bus);
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unsigned char zpg = read_pc_inc(bus);
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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@ -2779,16 +2776,33 @@ struct CPU6502
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break;
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break;
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}
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}
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case 0x3A: { // DEC, 65C02 instruction
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case 0x3A: { // DEC, 65C02
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set_flags(N | Z, a = a - 1);
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set_flags(N | Z, a = a - 1);
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break;
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break;
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}
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}
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case 0x1A: { // INC, 65C02 instruction
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case 0x1A: { // INC, 65C02
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set_flags(N | Z, a = a + 1);
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set_flags(N | Z, a = a + 1);
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break;
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break;
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}
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}
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case 0x12: { // ORA (ind), 65C02
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unsigned char zpg = read_pc_inc(bus);
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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m = bus.read(addr);
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set_flags(N | Z, a = a | m);
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break;
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}
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case 0xD2: { // CMP (zpg), 65C02 instruction
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unsigned char zpg = read_pc_inc(bus);
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int addr = bus.read(zpg) + bus.read((zpg + 1) & 0xFF) * 256;
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m = bus.read(addr);
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flag_change(C, m <= a);
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set_flags(N | Z, m = a - m);
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break;
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}
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default:
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default:
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printf("unhandled instruction %02X at %04X\n", inst, pc - 1);
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printf("unhandled instruction %02X at %04X\n", inst, pc - 1);
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fflush(stdout); exit(1);
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fflush(stdout); exit(1);
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@ -2831,7 +2845,7 @@ int CPU6502::cycles[256] =
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/* 0xA- */ 2, 6, 2, -1, 3, 3, 3, -1, 2, 2, 2, -1, 4, 4, 4, -1,
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/* 0xA- */ 2, 6, 2, -1, 3, 3, 3, -1, 2, 2, 2, -1, 4, 4, 4, -1,
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/* 0xB- */ 2, 5, 5, -1, 4, 4, 4, -1, 2, 4, 2, -1, 4, 4, 4, -1,
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/* 0xB- */ 2, 5, 5, -1, 4, 4, 4, -1, 2, 4, 2, -1, 4, 4, 4, -1,
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/* 0xC- */ 2, 6, -1, -1, 3, 3, 5, -1, 2, 2, 2, -1, 4, 4, 3, -1,
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/* 0xC- */ 2, 6, -1, -1, 3, 3, 5, -1, 2, 2, 2, -1, 4, 4, 3, -1,
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/* 0xD- */ 2, 5, -1, -1, -1, 4, 6, -1, 2, 4, 3, -1, -1, 4, 7, -1,
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/* 0xD- */ 2, 5, 5, -1, -1, 4, 6, -1, 2, 4, 3, -1, -1, 4, 7, -1,
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/* 0xE- */ 2, 6, -1, -1, 3, 3, 5, -1, 2, 2, 2, -1, 4, 4, 6, -1,
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/* 0xE- */ 2, 6, -1, -1, 3, 3, 5, -1, 2, 2, 2, -1, 4, 4, 6, -1,
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/* 0xF- */ 2, 5, -1, -1, -1, 4, 6, -1, 2, 4, -1, -1, -1, 4, 7, -1,
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/* 0xF- */ 2, 5, -1, -1, -1, 4, 6, -1, 2, 4, -1, -1, -1, 4, 7, -1,
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};
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};
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@ -55,7 +55,7 @@ tuple<int, string> disassemble_6502(int address, const unsigned char* buffer)
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{2,31,1},{2,29,4},{2,30,1},{1,69,0},{2,31,0},{2,29,0},{2,30,0},{1,69,0},{1,52,0},{2,29,1},{1,51,0},{1,69,0},{3,31,0},{3,29,0},{3,30,0},{1,69,0}, // A
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{2,31,1},{2,29,4},{2,30,1},{1,69,0},{2,31,0},{2,29,0},{2,30,0},{1,69,0},{1,52,0},{2,29,1},{1,51,0},{1,69,0},{3,31,0},{3,29,0},{3,30,0},{1,69,0}, // A
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{2,4,8}, {2,29,5},{2,29,0},{1,69,0},{2,31,2},{2,29,2},{2,30,3},{1,69,0},{1,16,0},{3,29,3},{1,53,0},{1,69,0},{3,31,2},{3,29,2},{3,30,3},{1,69,0}, // B
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{2,4,8}, {2,29,5},{2,29,0},{1,69,0},{2,31,2},{2,29,2},{2,30,3},{1,69,0},{1,16,0},{3,29,3},{1,53,0},{1,69,0},{3,31,2},{3,29,2},{3,30,3},{1,69,0}, // B
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{2,19,1},{2,17,4},{1,69,0},{1,69,0},{2,19,0},{2,17,0},{2,20,0},{1,69,0},{1,26,0},{2,17,1},{1,21,0},{1,69,0},{3,19,0},{3,17,0},{3,20,0},{1,69,0}, // C
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{2,19,1},{2,17,4},{1,69,0},{1,69,0},{2,19,0},{2,17,0},{2,20,0},{1,69,0},{1,26,0},{2,17,1},{1,21,0},{1,69,0},{3,19,0},{3,17,0},{3,20,0},{1,69,0}, // C
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{2,8,8}, {2,17,5},{1,69,0},{1,69,0},{1,69,0},{2,17,2},{2,20,2},{1,69,0},{1,14,0},{3,17,3},{1,58,0},{1,69,0},{1,69,0},{3,17,2},{3,20,2},{1,69,0}, // D
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{2,8,8}, {2,17,5},{2,17,0},{1,69,0},{1,69,0},{2,17,2},{2,20,2},{1,69,0},{1,14,0},{3,17,3},{1,58,0},{1,69,0},{1,69,0},{3,17,2},{3,20,2},{1,69,0}, // D
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{2,18,1},{2,44,4},{1,69,0},{1,69,0},{2,18,0},{2,44,0},{2,24,0},{1,69,0},{1,25,0},{2,44,1},{1,33,0},{1,69,0},{3,18,0},{3,44,0},{3,24,0},{1,69,0}, // E
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{2,18,1},{2,44,4},{1,69,0},{1,69,0},{2,18,0},{2,44,0},{2,24,0},{1,69,0},{1,25,0},{2,44,1},{1,33,0},{1,69,0},{3,18,0},{3,44,0},{3,24,0},{1,69,0}, // E
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{2,5,8}, {2,44,5},{1,69,0},{1,69,0},{1,69,0},{2,44,2},{2,24,2},{1,69,0},{1,46,0},{3,44,3},{1,69,0},{1,69,0},{1,69,0},{3,44,2},{3,24,2},{1,69,0} // F
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{2,5,8}, {2,44,5},{1,69,0},{1,69,0},{1,69,0},{2,44,2},{2,24,2},{1,69,0},{1,46,0},{3,44,3},{1,69,0},{1,69,0},{1,69,0},{3,44,2},{3,24,2},{1,69,0} // F
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};
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};
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