6e2e54e2be
Add more 65C02 instructions, fix BRK on 65C02
2020-12-31 10:58:52 -08:00
afb222f18f
initialize CPU correctly, never set bit 4 or 5 of P
2020-12-27 20:50:32 -08:00
734900c314
add BBR, BBS, PLY, PHY, and PLX 65C02 instructions
2020-12-26 11:48:52 -08:00
1d8f0e0564
Fix some instructions, add missing ones
...
Get cpu6502 to pass functional tests from https://github.com/Klaus2m5/6502_65C02_functional_tests
Set bit 5 on status register pushed during IRQ, NMI, BRK.
Fix return address pushed for BRK
Fix flag setting for ROR
Fix flags pushed with PHP
Fix return address for RTI
Add 0xD5 - DEC zpg, X
Add 0xE1 - SBC (ind, X)
Add 0x61 - ADC (ind, X)
Add 0x1E - ASL abs, x
Add 0x21 - AND (ind, X)
Add 0x96 - STX zpg, Y
add 0x75 - ADC zpg, X
2020-12-21 14:59:37 -08:00
fb7d31d814
make ordering explicit of some 16-bit addressing
2020-12-16 22:55:29 -08:00
c2eb84b38c
use more well-defined int types
2020-12-16 22:55:29 -08:00
fe8e4a5058
update formatting from Jim's aed512 version of cpu6502
2019-02-16 08:49:10 -08:00
0bb0b6ffd4
add B6 and C1 instructions
2019-02-16 08:44:49 -08:00
1591046c74
Add way to disable 65C02 instructions.
2019-02-06 23:23:33 -08:00
85f7d8d7dd
update cpu6502 with Jim's improvements
2018-09-10 12:29:16 -07:00
5e8adf5de1
remove dead code and comments lacking confidence
2018-09-08 18:42:39 -07:00
17806a16b7
fix wording of template parameter docs
2018-09-08 18:37:41 -07:00
af715292b2
make class the first thing you see
2018-09-08 18:19:53 -07:00
40035852cd
add a little documentation
2018-09-08 17:45:57 -07:00
1dc3fe3df8
extract CPU6502 into single header implementation
2018-09-08 17:36:16 -07:00
Brad Grantham
Lawrence Kesteloot