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https://github.com/ivanizag/izapple2.git
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Trace slot memory access
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13c6a59ee5
commit
83f72fe8cb
4 files changed
+68
-28
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+18
-17
@@ -6,24 +6,24 @@ import (
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// Card represents an Apple II card to be inserted in a slot
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type Card interface {
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configure(name string, trace bool, traceMemory bool)
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loadRom(data []uint8, layout cardRomLayout) error
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assign(a *Apple2, slot int)
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reset()
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runDMACycle()
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setName(name string)
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setDebug(debug bool)
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GetName() string
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GetInfo() map[string]string
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}
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type cardBase struct {
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a *Apple2
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name string
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trace bool
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romCsxx *memoryRangeROM
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romC8xx memoryHandler
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romCxxx memoryHandler
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a *Apple2
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name string
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trace bool
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traceMemory bool
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romCsxx *memoryRangeROM
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romC8xx memoryHandler
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romCxxx memoryHandler
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slot int
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_ssr [16]softSwitchR
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@@ -32,10 +32,6 @@ type cardBase struct {
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_sswName [16]string
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}
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func (c *cardBase) setName(name string) {
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c.name = name
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}
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func (c *cardBase) GetName() string {
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return c.name
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}
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@@ -44,8 +40,10 @@ func (c *cardBase) GetInfo() map[string]string {
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return nil
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}
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func (c *cardBase) setDebug(debug bool) {
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c.trace = debug
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func (c *cardBase) configure(name string, trace bool, traceMemory bool) {
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c.name = name
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c.trace = trace
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c.traceMemory = traceMemory
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}
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func (c *cardBase) reset() {
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@@ -134,14 +132,17 @@ func (c *cardBase) assign(a *Apple2, slot int) {
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if c.romCsxx != nil {
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// Relocate to the assigned slot
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c.romCsxx.setBase(uint16(0xc000 + slot*0x100))
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a.mmu.setCardROM(slot, c.romCsxx)
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rom := traceMemory(c.romCsxx, c.name, c.traceMemory)
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a.mmu.setCardROM(slot, rom)
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}
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if c.romC8xx != nil {
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a.mmu.setCardROMExtra(slot, c.romC8xx)
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rom := traceMemory(c.romC8xx, c.name, c.traceMemory)
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a.mmu.setCardROMExtra(slot, rom)
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}
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if c.romCxxx != nil {
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rom := traceMemory(c.romCxxx, c.name, c.traceMemory)
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a.mmu.setCardROM(slot, c.romCxxx)
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a.mmu.setCardROMExtra(slot, c.romCxxx)
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a.mmu.setCardROMExtra(slot, rom)
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}
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}
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+6
-3
@@ -29,6 +29,7 @@ var commonParams = []paramSpec{
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{"trace", "Enable debug messages", "false"},
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{"tracess", "Trace softswitches", "false"},
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{"panicss", "Panic on unimplemented softswitches", "false"},
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{"tracemem", "Trace slot addressing accesses", "false"},
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}
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var cardFactory map[string]*cardBuilder
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@@ -134,10 +135,12 @@ func setupCard(a *Apple2, slot int, paramString string) (Card, error) {
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a.io.panicNotImplementedSlot(slot)
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}
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debug := paramsGetBool(finalParams, "trace")
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card.configure(
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builder.name,
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paramsGetBool(finalParams, "trace"),
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paramsGetBool(finalParams, "tracemem"),
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)
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card.setName(builder.name)
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card.setDebug(debug)
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card.assign(a, slot)
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a.cards[slot] = card
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return card, err
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+8
-8
@@ -19,12 +19,12 @@ type memoryManager struct {
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physicalROM memoryHandler // 0xc000 (or 0xd000) to 0xffff, 16 (or 12) Kb. Up to four banks
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// Language card upper area RAM: 0xd000 to 0xffff. One bank for regular LC cards, up to 8 with Saturn
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physicalLangRAM []*memoryRange // 0xd000 to 0xffff, 12KB. Up to 8 banks.
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physicalLangAltRAM []*memoryRange // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
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physicalLangRAM []memoryHandler // 0xd000 to 0xffff, 12KB. Up to 8 banks.
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physicalLangAltRAM []memoryHandler // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
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// Extended RAM: 0x0000 to 0xffff (with 4Kb moved from 0xc000 to 0xd000 alt). One bank for extended Apple 2e card, up to 256 with RamWorks
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physicalExtRAM []*memoryRange // 0x0000 to 0xffff. 60Kb, 0xc000 to 0xcfff not used. Up to 256 banks
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physicalExtAltRAM []*memoryRange // 0xd000 to 0xdfff, 4Kb. Up to 256 banks.
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physicalExtRAM []memoryRangeHandler // 0x0000 to 0xffff. 60Kb, 0xc000 to 0xcfff not used. Up to 256 banks
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physicalExtAltRAM []memoryHandler // 0xd000 to 0xdfff, 4Kb. Up to 256 banks.
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// Configuration switches, Language cards
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lcSelectedBlock uint8 // Language card block selected. Usually, always 0. But Saturn has 8
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@@ -304,8 +304,8 @@ func (mmu *memoryManager) setCardROMExtra(slot int, mh memoryHandler) {
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func (mmu *memoryManager) initLanguageRAM(groups uint8) {
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// Apple II+ language card or Saturn (up to 8 groups)
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mmu.physicalLangRAM = make([]*memoryRange, groups)
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mmu.physicalLangAltRAM = make([]*memoryRange, groups)
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mmu.physicalLangRAM = make([]memoryHandler, groups)
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mmu.physicalLangAltRAM = make([]memoryHandler, groups)
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for i := uint8(0); i < groups; i++ {
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mmu.physicalLangRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x3000), fmt.Sprintf("LC RAM block %v", i))
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mmu.physicalLangAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("LC RAM Alt block %v", i))
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@@ -323,8 +323,8 @@ func (mmu *memoryManager) initCustomRAM(customRam memoryRangeHandler) {
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func (mmu *memoryManager) initExtendedRAM(groups int) {
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// Apple IIe 80 col card with 64Kb style RAM or RAMWorks (up to 256 banks)
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mmu.physicalExtRAM = make([]*memoryRange, groups)
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mmu.physicalExtAltRAM = make([]*memoryRange, groups)
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mmu.physicalExtRAM = make([]memoryRangeHandler, groups)
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mmu.physicalExtAltRAM = make([]memoryHandler, groups)
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for i := 0; i < groups; i++ {
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mmu.physicalExtRAM[i] = newMemoryRange(0, make([]uint8, 0x10000), fmt.Sprintf("Extra RAM block %v", i))
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mmu.physicalExtAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("Extra RAM Alt block %v", i))
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@@ -0,0 +1,36 @@
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package izapple2
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import (
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"fmt"
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)
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type memoryTracer struct {
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memory memoryHandler
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name string
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}
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func traceMemory(memory memoryHandler, name string, trace bool) memoryHandler {
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if !trace {
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return memory
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}
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if memory == nil {
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return nil
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}
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return &memoryTracer{
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memory: memory,
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name: name,
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}
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}
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func (m *memoryTracer) peek(address uint16) uint8 {
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value := m.memory.peek(address)
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fmt.Printf("Memory %s: peek($%04X) = $%02X\n", m.name, address, value)
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return value
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}
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func (m *memoryTracer) poke(address uint16, value uint8) {
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fmt.Printf("Memory %s: poke($%04X, $%02X)\n", m.name, address, value)
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m.memory.poke(address, value)
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}
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