Trace slot memory access

This commit is contained in:
Ivan Izaguirre committed 2024-10-18 23:56:46 +02:00
1 parent 13c6a59ee5
commit 83f72fe8cb
4 files changed
+68 -28

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+18 -17
View File
@@ -6,24 +6,24 @@ import (
// Card represents an Apple II card to be inserted in a slot
type Card interface {
configure(name string, trace bool, traceMemory bool)
loadRom(data []uint8, layout cardRomLayout) error
assign(a *Apple2, slot int)
reset()
runDMACycle()
setName(name string)
setDebug(debug bool)
GetName() string
GetInfo() map[string]string
}
type cardBase struct {
a *Apple2
name string
trace bool
romCsxx *memoryRangeROM
romC8xx memoryHandler
romCxxx memoryHandler
a *Apple2
name string
trace bool
traceMemory bool
romCsxx *memoryRangeROM
romC8xx memoryHandler
romCxxx memoryHandler
slot int
_ssr [16]softSwitchR
@@ -32,10 +32,6 @@ type cardBase struct {
_sswName [16]string
}
func (c *cardBase) setName(name string) {
c.name = name
}
func (c *cardBase) GetName() string {
return c.name
}
@@ -44,8 +40,10 @@ func (c *cardBase) GetInfo() map[string]string {
return nil
}
func (c *cardBase) setDebug(debug bool) {
c.trace = debug
func (c *cardBase) configure(name string, trace bool, traceMemory bool) {
c.name = name
c.trace = trace
c.traceMemory = traceMemory
}
func (c *cardBase) reset() {
@@ -134,14 +132,17 @@ func (c *cardBase) assign(a *Apple2, slot int) {
if c.romCsxx != nil {
// Relocate to the assigned slot
c.romCsxx.setBase(uint16(0xc000 + slot*0x100))
a.mmu.setCardROM(slot, c.romCsxx)
rom := traceMemory(c.romCsxx, c.name, c.traceMemory)
a.mmu.setCardROM(slot, rom)
}
if c.romC8xx != nil {
a.mmu.setCardROMExtra(slot, c.romC8xx)
rom := traceMemory(c.romC8xx, c.name, c.traceMemory)
a.mmu.setCardROMExtra(slot, rom)
}
if c.romCxxx != nil {
rom := traceMemory(c.romCxxx, c.name, c.traceMemory)
a.mmu.setCardROM(slot, c.romCxxx)
a.mmu.setCardROMExtra(slot, c.romCxxx)
a.mmu.setCardROMExtra(slot, rom)
}
}
+6 -3
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@@ -29,6 +29,7 @@ var commonParams = []paramSpec{
{"trace", "Enable debug messages", "false"},
{"tracess", "Trace softswitches", "false"},
{"panicss", "Panic on unimplemented softswitches", "false"},
{"tracemem", "Trace slot addressing accesses", "false"},
}
var cardFactory map[string]*cardBuilder
@@ -134,10 +135,12 @@ func setupCard(a *Apple2, slot int, paramString string) (Card, error) {
a.io.panicNotImplementedSlot(slot)
}
debug := paramsGetBool(finalParams, "trace")
card.configure(
builder.name,
paramsGetBool(finalParams, "trace"),
paramsGetBool(finalParams, "tracemem"),
)
card.setName(builder.name)
card.setDebug(debug)
card.assign(a, slot)
a.cards[slot] = card
return card, err
+8 -8
View File
@@ -19,12 +19,12 @@ type memoryManager struct {
physicalROM memoryHandler // 0xc000 (or 0xd000) to 0xffff, 16 (or 12) Kb. Up to four banks
// Language card upper area RAM: 0xd000 to 0xffff. One bank for regular LC cards, up to 8 with Saturn
physicalLangRAM []*memoryRange // 0xd000 to 0xffff, 12KB. Up to 8 banks.
physicalLangAltRAM []*memoryRange // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
physicalLangRAM []memoryHandler // 0xd000 to 0xffff, 12KB. Up to 8 banks.
physicalLangAltRAM []memoryHandler // 0xd000 to 0xdfff, 4KB. Up to 8 banks.
// Extended RAM: 0x0000 to 0xffff (with 4Kb moved from 0xc000 to 0xd000 alt). One bank for extended Apple 2e card, up to 256 with RamWorks
physicalExtRAM []*memoryRange // 0x0000 to 0xffff. 60Kb, 0xc000 to 0xcfff not used. Up to 256 banks
physicalExtAltRAM []*memoryRange // 0xd000 to 0xdfff, 4Kb. Up to 256 banks.
physicalExtRAM []memoryRangeHandler // 0x0000 to 0xffff. 60Kb, 0xc000 to 0xcfff not used. Up to 256 banks
physicalExtAltRAM []memoryHandler // 0xd000 to 0xdfff, 4Kb. Up to 256 banks.
// Configuration switches, Language cards
lcSelectedBlock uint8 // Language card block selected. Usually, always 0. But Saturn has 8
@@ -304,8 +304,8 @@ func (mmu *memoryManager) setCardROMExtra(slot int, mh memoryHandler) {
func (mmu *memoryManager) initLanguageRAM(groups uint8) {
// Apple II+ language card or Saturn (up to 8 groups)
mmu.physicalLangRAM = make([]*memoryRange, groups)
mmu.physicalLangAltRAM = make([]*memoryRange, groups)
mmu.physicalLangRAM = make([]memoryHandler, groups)
mmu.physicalLangAltRAM = make([]memoryHandler, groups)
for i := uint8(0); i < groups; i++ {
mmu.physicalLangRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x3000), fmt.Sprintf("LC RAM block %v", i))
mmu.physicalLangAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("LC RAM Alt block %v", i))
@@ -323,8 +323,8 @@ func (mmu *memoryManager) initCustomRAM(customRam memoryRangeHandler) {
func (mmu *memoryManager) initExtendedRAM(groups int) {
// Apple IIe 80 col card with 64Kb style RAM or RAMWorks (up to 256 banks)
mmu.physicalExtRAM = make([]*memoryRange, groups)
mmu.physicalExtAltRAM = make([]*memoryRange, groups)
mmu.physicalExtRAM = make([]memoryRangeHandler, groups)
mmu.physicalExtAltRAM = make([]memoryHandler, groups)
for i := 0; i < groups; i++ {
mmu.physicalExtRAM[i] = newMemoryRange(0, make([]uint8, 0x10000), fmt.Sprintf("Extra RAM block %v", i))
mmu.physicalExtAltRAM[i] = newMemoryRange(0xd000, make([]uint8, 0x1000), fmt.Sprintf("Extra RAM Alt block %v", i))
+36
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@@ -0,0 +1,36 @@
package izapple2
import (
"fmt"
)
type memoryTracer struct {
memory memoryHandler
name string
}
func traceMemory(memory memoryHandler, name string, trace bool) memoryHandler {
if !trace {
return memory
}
if memory == nil {
return nil
}
return &memoryTracer{
memory: memory,
name: name,
}
}
func (m *memoryTracer) peek(address uint16) uint8 {
value := m.memory.peek(address)
fmt.Printf("Memory %s: peek($%04X) = $%02X\n", m.name, address, value)
return value
}
func (m *memoryTracer) poke(address uint16, value uint8) {
fmt.Printf("Memory %s: poke($%04X, $%02X)\n", m.name, address, value)
m.memory.poke(address, value)
}