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Fix a2audit regression on aux mem

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This commit is contained in:
Ivan Izaguirre 2020-09-23 18:21:45 +02:00
parent 8ebd745a63
commit 9ce9d1f96d
1 changed files with 1 additions and 0 deletions
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memoryManager.go
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@ -188,6 +188,7 @@ func (mmu *memoryManager) accessWrite(address uint16) memoryHandler {
return mmu.getPhysicalMainRAM(mmu.altMainRAMActiveWrite)
}
if address <= addressLimitIO {
mmu.lastAddressPage = invalidAddressPage
return mmu.apple2.io
}
if address <= addressLimitSlotsExtra {