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Playing with the Apple II Profile Interface Card
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commit
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11 files changed
+111
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@@ -255,7 +255,6 @@ The available cards are:
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diskiiseq: Disk II interface card emulating the Woz state machine
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fastchip: Accelerator card for Apple IIe (limited support)
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fujinet: SmartPort interface card hosting the Fujinet
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inout: Card to test I/O
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language: Language card with 16 extra KB for the Apple ][ and ][+
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memexp: Memory expansion card
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mouse: Mouse card implementation, does not emulate a real card, only the firmware behaviour
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+13
-3
@@ -54,8 +54,9 @@ type cardRomLayout int
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const (
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cardRomSimple cardRomLayout = iota // The ROM is on the slot area, there can be more than one page
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cardRomUpper // The ROM is on the full C800 area. The slot area copies C8xx
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cardRomUpperStart // The ROM is on the full C800 area. The slot area copies C8xx
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cardRomUpperHalfEnd // The ROM is on half of the C800 areas. The slot area copies CBxx
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cardRomUpperEnd // The ROM is on the full C800 area. The slot area copies CFxx
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cardRomFull // The ROM is on the full Cxxx area, with pages for each slot position
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)
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@@ -88,14 +89,14 @@ func (c *cardBase) loadRom(data []uint8, layout cardRomLayout) error {
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} else {
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return fmt.Errorf("invalid ROM size for simple layout")
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}
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case cardRomUpper:
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case cardRomUpperStart:
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if len(data) == 0x800 {
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// The file has C800 to CFFF
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// The 256 bytes in Cx00 are copied from the first page in C800
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c.romCsxx = newMemoryRangeROM(0, data, "Slot ROM")
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c.romC8xx = newMemoryRangeROM(0xc800, data, "Slot C8 ROM")
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} else {
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return fmt.Errorf("invalid ROM size for upper layout")
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return fmt.Errorf("invalid ROM size for upper start layout")
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}
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case cardRomUpperHalfEnd:
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if len(data) == 0x400 {
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@@ -107,6 +108,15 @@ func (c *cardBase) loadRom(data []uint8, layout cardRomLayout) error {
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} else {
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return fmt.Errorf("invalid ROM size for upper half end layout")
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}
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case cardRomUpperEnd:
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if len(data) == 0x800 {
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// The file has C800 to CFFF for ROM
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// The 256 bytes in Cx00 are copied from the last page in C800-CFFF
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c.romCsxx = newMemoryRangeROM(0, data[0x700:], "Slot ROM")
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c.romC8xx = newMemoryRangeROM(0xc800, data, "Slot C8 ROM")
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} else {
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return fmt.Errorf("invalid ROM size for upper end layout")
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}
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case cardRomFull:
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if len(data) == 0x1000 {
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// The file covers the full Cxxx range. Only showing the page
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@@ -20,6 +20,7 @@ type cardBuilder struct {
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description string
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defaultParams *[]paramSpec
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requiresIIe bool
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hide bool
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buildFunc func(params map[string]string) (Card, error)
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}
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@@ -57,6 +58,7 @@ func getCardFactory() map[string]*cardBuilder {
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cardFactory["prodosromdrive"] = newCardProDOSRomDriveBuilder()
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cardFactory["prodosromcard3"] = newCardProDOSRomCard3Builder()
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// cardFactory["prodosnvramdrive"] = newCardProDOSNVRAMDriveBuilder()
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cardFactory["profile"] = newCardProfileBuilder()
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cardFactory["saturn"] = newCardSaturnBuilder()
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cardFactory["smartport"] = newCardSmartPortStorageBuilder()
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cardFactory["swyftcard"] = newCardSwyftBuilder()
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@@ -28,6 +28,7 @@ func newCardInOutBuilder() *cardBuilder {
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return &cardBuilder{
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name: "InOut test card",
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description: "Card to test I/O",
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hide: true,
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buildFunc: func(params map[string]string) (Card, error) {
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return &CardInOut{}, nil
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},
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@@ -0,0 +1,87 @@
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package izapple2
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import (
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"fmt"
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)
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/*
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Profile card for Apple II Interface.
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The firmware source code for 5MB is available at: https://bitsavers.org/pdf/apple/disk/profile/appleII_interface/AII_Profile_Boot_Prom_198402.pdf
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See also:
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https://bitsavers.org/pdf/apple/disk/profile/072-0116_Profile_Level_II_Service_Manual_Oct84.pdf
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https://bitsavers.org/pdf/apple/disk/profile/Profile_Communication_Protocol.pdf
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https://mirrors.apple2.org.za/Apple%20II%20Documentation%20Project/Interface%20Cards/Hard%20Disk%20Drive%20Controllers/Apple%20II%20ProFile%20Interface%20Card/
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Softswitches:
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W0: WR_PORT, write to Z8 RAM (byte at a time)
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R1: RD_PORT, read from Z8 RAM (byte at a time)
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R2: BUSY, Z8 not ready
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bit 0 off is drive present and connected to card
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bit 6 is parity error
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bit 7 on is ready and online
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W2: RSTAT?
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W3: CLR PARITY, clear any previous parity error
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*/
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// CardProfile represents the Apple II Profile interface card
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type CardProfile struct {
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cardBase
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}
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func newCardProfileBuilder() *cardBuilder {
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return &cardBuilder{
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name: "Apple II Profile interface card",
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description: "Profile interface card - not implemented",
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hide: true,
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defaultParams: &[]paramSpec{
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{"rom", "ROM file to load", "<internal>/Apple II Interface 341-0271-A ROM 2716 for 5MB Profile.bin"},
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//{"rom", "ROM file to load", "<internal>/Apple II Interface 341-0299-B ROM 2716 for 10MB Profile.bin"},
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},
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buildFunc: func(params map[string]string) (Card, error) {
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var c CardProfile
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romFile := paramsGetPath(params, "rom")
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err := c.loadRomFromResource(romFile, cardRomUpperEnd)
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if err != nil {
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return nil, err
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}
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return &c, nil
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},
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}
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}
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func (c *CardProfile) assign(a *Apple2, slot int) {
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// WR_PORT, write to Z8 RAM (byte at a time)
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c.addCardSoftSwitchW(0, func(value uint8) {
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fmt.Printf("[cardProfile] WR_PORT: Write to Z8 RAM, value 0x%02x\n", value)
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}, "PROFILE_WR_PORT")
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// RD_PORT, read from Z8 RAM (byte at a time)
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c.addCardSoftSwitchR(1, func() uint8 {
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fmt.Printf("[cardProfile] RD_PORT: Read from Z8 RAM\n")
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return 0x00 // Return dummy data for now
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}, "PROFILE_RD_PORT")
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// BUSY, Z8 not ready
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c.addCardSoftSwitchR(2, func() uint8 {
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fmt.Printf("[cardProfile] BUSY: Z8 status check\n")
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// Return 0x80 (bit 7 on) to indicate ready and online
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// bit 0 off indicates drive present
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return 0x80
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}, "PROFILE_BUSY")
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// RSTAT?
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c.addCardSoftSwitchW(2, func(value uint8) {
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fmt.Printf("[cardProfile] RSTAT: Write status, value 0x%02x\n", value)
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}, "PROFILE_RSTAT")
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// CLR PARITY, clear any previous parity error
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c.addCardSoftSwitchW(3, func(value uint8) {
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fmt.Printf("[cardProfile] CLR_PARITY: Clear parity error, value 0x%02x\n", value)
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}, "PROFILE_CLR_PARITY")
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// Call base assignment to setup ROM and other card functionality
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c.cardBase.assign(a, slot)
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}
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@@ -33,7 +33,7 @@ func newCardThunderClockPlusBuilder() *cardBuilder {
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description: "Clock card",
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buildFunc: func(params map[string]string) (Card, error) {
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var c CardThunderClockPlus
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err := c.loadRomFromResource("<internal>/ThunderclockPlusROM.bin", cardRomUpper)
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err := c.loadRomFromResource("<internal>/ThunderclockPlusROM.bin", cardRomUpperStart)
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if err != nil {
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return nil, err
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}
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+3
-1
@@ -271,7 +271,9 @@ func setupFlags(models *configurationModels, configuration *configuration) error
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fmt.Fprintf(out, "\nThe available cards are:\n")
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for _, card := range availableCards() {
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builder := getCardFactory()[card]
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fmt.Fprintf(out, " %s: %s\n", card, builder.description)
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if !builder.hide {
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fmt.Fprintf(out, " %s: %s\n", card, builder.description)
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}
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}
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fmt.Fprintf(out, "\nThe available tracers are:\n")
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@@ -72,7 +72,6 @@ The available cards are:
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diskiiseq: Disk II interface card emulating the Woz state machine
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fastchip: Accelerator card for Apple IIe (limited support)
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fujinet: SmartPort interface card hosting the Fujinet
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inout: Card to test I/O
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language: Language card with 16 extra KB for the Apple ][ and ][+
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memexp: Memory expansion card
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mouse: Mouse card implementation, does not emulate a real card, only the firmware behaviour
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Binary file not shown.
Binary file not shown.
@@ -240,9 +240,10 @@ func loadMultiPageRom(a *Apple2, filenames []string) error {
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}
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var diskAliases = map[string]string{
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"dos33": "<internal>/dos33.dsk",
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"prodos": "<internal>/ProDOS_2_4_3.po",
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"cpm": "<internal>/cpm_2.20B_56K.po",
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"dos33": "<internal>/dos33.dsk",
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"prodos": "<internal>/ProDOS_2_4_3.po",
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"cpm": "<internal>/cpm_2.20B_56K.po",
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"cardcat": "<internal>/Card Cat 1.7.dsk",
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}
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func applyDiskAliases(filename string) string {
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