Remove dead code from codebase
This commit is contained in:
Lucas Scharenbroich
parent
02bc6fe493
commit
dc5742dd11
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@ -46,7 +46,7 @@
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; Additional code
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ASM FastCopies.s
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KND #$1001 ; Type and Attributes ($11=Static+Bank Relative,$01=Data)
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ALI BANK
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SNA FASTCPY
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; ASM FastCopies.s
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; KND #$1001 ; Type and Attributes ($11=Static+Bank Relative,$01=Data)
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; ALI BANK
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; SNA FASTCPY
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@ -965,7 +965,6 @@ _TSCompileSpriteStamp
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put Sprite2.s
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put SpriteRender.s
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put Render.s
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; put blitter/Scanline.s
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put render/Render.s
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put render/Fast.s
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put render/Slow.s
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@ -1,256 +0,0 @@
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; This support an alternate engine mode. When in scanline mode the renderer does not use the
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; global StartX and StartY parameters to set up the code field. Instead, an array of scanline
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; parameters must be provided to the blitter.
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;
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; This is a low-level mode and it is assumed that the arrays will contain valid values. This
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; process is quite a bit slower that the normal setup because it must calculate code field
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; entry points for each line, instead of once for the entire frame.
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_ScanlineBG0XPos
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:stk_save equ tmp0
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:virt_line_x2 equ tmp1
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:last_line_x2 equ tmp2
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:src_bank equ tmp3
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:exit_offset equ tmp4
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:entry_offset equ tmp5
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:exit_bra equ tmp6
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:exit_address equ tmp7
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:base_address equ tmp8
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:opcode equ tmp9
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:odd_entry_offset equ tmp10
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lda StartYMod208 ; This is the base line of the virtual screen
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asl
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sta :virt_line_x2 ; Keep track of it
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lda ScreenHeight
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asl
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clc
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adc :virt_line_x2
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sta :last_line_x2
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phb
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phb
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pla
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and #$FF00
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sta :src_bank
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:loop
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ldx :virt_line_x2
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lda StartXMod164Arr,x ; Get the offset for this line
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dec ; The exit point is one byte sooner
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bpl *+5
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lda #163
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bit #$0001 ; if odd, then original number was even
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beq :odd_exit ; if even, the original number was odd
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; This is the even code path
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and #$FFFE
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tay
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lda CodeFieldEvenBRA,y
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sta :exit_bra
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lda Col2CodeOffset,y
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sta :exit_offset
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sta LastPatchOffsetArr,x ; Cache afor later
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bra :do_entry
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; This is the odd code path
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:odd_exit tay
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lda CodeFieldOddBRA,y
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sta :exit_bra
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lda Col2CodeOffset,y
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sta :exit_offset
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sta LastPatchOffsetArr,x
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; Handle the entry point calculations
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:do_entry
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lda StartXMod164Arr,x
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clc
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adc ScreenWidth ; move to the right edge and back up a byte
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dec ; to get the index of the first on-screen byte
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cmp #164 ; Keep the value in range
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bcc *+5
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sbc #164
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; Same logic as before
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bit #$0001
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beq :odd_entry
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and #$FFFE
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tay
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lda Col2CodeOffset,y
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sta :entry_offset
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lda #$004C ; set the entry_jmp opcode to JMP
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sta :opcode
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stz :odd_entry_offset ; mark as an even case
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bra :prep_complete
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:odd_entry
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tay
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lda Col2CodeOffset,y
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sta :entry_offset ; Will be used to load the data
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lda Col2CodeOffset-2,y
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sta :odd_entry_offset ; will the the actual location to jump to
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lda #$00AF ; set the entry_jmp opcode to LDAL
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sta :opcode
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:prep_complete
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; Now patch in the code field line
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ldy BTableLow,x ; Get the address of the first code field line
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clc
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adc :exit_offset ; Add some offsets to get the base address in the code field line
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sta :exit_address
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sty :base_address
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lda BTableHigh,x
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ora :src_bank
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pha
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plb
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; First step is to set the BRA instruction to exit the code field at the proper location. There
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; are two sub-steps to do here; we need to save the 16-bit value that exists at the location and
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; then overwrite it with the branch instruction.
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; SaveOpcode
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; y is already set to :base_address
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ldx :exit_address ; Save from this location
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lda: $0000,x
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sta: OPCODE_SAVE+$0000,y
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;SetConst
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; txy ; ldy :exit_address -- starting at this address
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lda :exit_bra ; Copy this value into all of the lines
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sta: $0000,x
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; Next, patch in the CODE_ENTRY value, which is the low byte of a JMP instruction. This is an
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; 8-bit operation and, since the PEA code is bank aligned, we use the entry_offset value directly
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sep #$20
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; SetCodeEntry
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lda :entry_offset
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; ldy :base_address
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sta: CODE_ENTRY+$0000,y
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; SetCodeEntryOpcode
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lda :opcode
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sta: CODE_ENTRY_OPCODE+$0000,y
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; If this is an odd entry, also set the odd_entry low byte and save the operand high byte
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lda :odd_entry_offset
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beq :not_odd
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; SetOddCodeEntry
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sta: ODD_ENTRY+$0000,y
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; SaveHighOperand
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; ldx :exit_address
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lda: $0002,x
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sta: OPCODE_HIGH_SAVE+$0000,y
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:not_odd
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rep #$20 ; clear the carry
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; Do the end of the loop -- update the virtual line counter and reduce the number
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; of lines left to render
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plb ; restore the bank
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lda :virt_line_x2
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inc
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inc
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sta :virt_line_x2
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cmp :last_line_x2
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jne :loop
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rts
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_RestoreScanlineBG0Opcodes
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:virt_line_x2 equ tmp1
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:lines_left_x2 equ tmp2
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:src_bank equ tmp6
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asl
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sta :virt_line_x2 ; Keep track of it
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phb
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phb
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pla
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and #$FF00
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sta :src_bank
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txa
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asl
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sta :lines_left_x2
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:loop
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ldx :virt_line_x2
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lda BTableHigh,x
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ora :src_bank
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pha
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lda BTableLow,x ; Get the address of the first code field line
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clc
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adc LastPatchOffsetArr,x
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tax
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plb
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lda: OPCODE_SAVE+$0000,y
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sta: $0000,x
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; Do the end of the loop -- update the virtual line counter and reduce the number
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; of lines left to render
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plb ; restore the bank
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lda :virt_line_x2
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inc
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inc
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sta :virt_line_x2
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cmp :last_line_x2
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jne :loop
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stz LastPatchOffset ; Clear the value once completed
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rts
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; Unrolled copy routine to move BankTable entries into BNK_ADDR position. This is a bit different than the
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; other routines, because we don't need to put values into the code fields, but just copy one-byte values
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; into an internal array in bank 00 space. The reason for this is because the code sequence
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;
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; lda #ADDR
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; tcs
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; plb
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;
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; Take only 9 cycles, but the alternative is slower
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;
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; pea #$BBBB
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; plb
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; plb = 13 cycles
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;
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; If for some reason it becomes important to preserve the accumulator, or save the 208 bytes of
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; bank 00 memory, then we can change it. The advantage right now is that updating the array can
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; be done 16-bits at a time and without having to chunk up the writes across multiple banks. This
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; is quite a bit faster than the other routines.
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CopyTableToBankBytes
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tsx ; save the stack
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sei
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jmp $0000
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lda: 2,y
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pha
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lda: 0,y
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pha
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bottom
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txs ; restore the stack
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cli ; turn interrupts back on
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rts
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@ -1,580 +0,0 @@
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; Collection of functions that deal with tiles. Primarily rendering tile data into
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; the code fields.
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;
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; Tile data can be done faily often, so these routines are performance-sensitive.
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;
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; CopyTileConst -- the first 16 tile numbers are reserved and can be used
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; to draw a solid tile block
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; CopyTileLinear -- copies the tile data from the tile bank in linear order, e.g.
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; 32 consecutive bytes are copied
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; _RenderTile
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;
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; A high-level function that takes a 16-bit tile descriptor and dispatched to the
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; appropriate tile copy routine based on the descriptor flags
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;
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; Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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; |xx|xx|FF|MM|DD|VV|HH| | | | | | | | | |
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; +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
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; \____/ | | | | | \________________________/
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; | | | | | | Tile ID (0 to 511)
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; | | | | | |
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; | | | | | +-- H : Flip tile horizontally
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; | | | | +----- V : Flip tile vertically
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; | | | +-------- D : Render as a Dynamic Tile (Tile ID < 32, V and H have no effect)
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; | | +----------- M : Apply tile mask
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; | +-------------- F : Overlay a fringe tile
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; +------------------- Reserved (must be zero)
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;
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; Each logical tile (corresponding to each Tile ID) actually takes up 128 bytes of memory in the
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; tile bank
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;
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; +0 : 32 bytes of tile data
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; +32 : 32 bytes of tile mask
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; +64 : 32 bytes of horizontally flipped tile data
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; +96 : 32 bytes of horizontally flipped tile mask
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;
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; It is simply too slow to try to horizontally reverse the pixel data on the fly. This still allows
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; for up to 512 tiles to be stored in a single bank, which should be sufficient.
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;
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; Given an address to a Tile Store record, dispatch to the appropriate tile renderer. The Tile
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; Store record contains all of the low-level information that's needed to call the renderer.
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;
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; There are two execution paths that are handled here. First, if there is no sprite, then
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; the tile data is read directly and written into the code field in a single pass. If there
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; are sprites that overlap the tile, then the sprite data is combined with the tile data
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; and written to a temporary direct page buffer. If
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;
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; This routine sets the direct page register to the second page since we use that space to
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; build and cache tile and sprite data, when necessary
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_RenderTile2
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lda TileStore+TS_SPRITE_FLAG,x ; This is a bitfield of all the sprites that intersect this tile, only care if non-zero or not
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bne do_dirty_sprite
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; Handle the non-sprite tile blit
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CopyNoSprites
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sep #$20
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lda TileStore+TS_CODE_ADDR_HIGH,x ; load the bank of the target code field line
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pha ; and put on the stack for later
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; lda TileStore+TS_BASE_ADDR+1,x ; load the base address of the code field ($0000 or $8000)
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; sta _BASE_ADDR+1 ; so we can get by just copying the high byte
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rep #$20
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lda TileStore+TS_BASE_TILE_DISP,x ; Get the address of the renderer for this tile
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stal :tiledisp+1
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lda TileStore+TS_TILE_ID,x
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sta _TILE_ID ; Some tile blitters need to get the tile descriptor
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ldy TileStore+TS_CODE_ADDR_LOW,x ; load the address of the code field
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lda TileStore+TS_TILE_ADDR,x ; load the address of this tile's data (pre-calculated)
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pha
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lda TileStore+TS_WORD_OFFSET,x
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plx
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plb ; set the bank to the code field that will be updated
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; B is set to the correct code field bank
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; A is set to the tile word offset (0 through 80 in steps of 4)
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; Y is set to the top-left address of the tile in the code field
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; X is set to the address of the tile data
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:tiledisp jmp $0000 ; render the tile
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; The sprite code is just responsible for quickly copying all of the sprite data
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; into the direct page temp area.
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do_dirty_sprite
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pei TileStoreBankAndTileDataBank ; Special value that has the TileStore bank in LSB and TileData bank in MSB
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plb
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; Cache a couple of values into the direct page that are used across all copy routines
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lda TileStore+TS_TILE_ADDR,y ; load the address of this tile's data (pre-calculated)
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sta tileAddr
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ldx TileStore+TS_VBUFF_ADDR_COUNT,y
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jmp (dirty_sprite_dispatch,x)
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dirty_sprite_dispatch
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da CopyNoSprites
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da CopyOneSprite
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da CopyTwoSprites
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da CopyThreeSprites
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da CopyFourSprites ; MAX, don't bother with more than 4 sprites per tile
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; We can optimize later, for now just copy the sprite data and mask into its own
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; direct page buffer and combine with the tile data later
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;
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; We set up direct page pointers to the mask bank and use the bank register for the
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; data.
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CopyFourSprites
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lda TileStore+TS_VBUFF_ADDR_0,y
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sta spriteIdx
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lda TileStore+TS_VBUFF_ADDR_1,y
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sta spriteIdx+4
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lda TileStore+TS_VBUFF_ADDR_2,y
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sta spriteIdx+8
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lda TileStore+TS_VBUFF_ADDR_3,y
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sta spriteIdx+12
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; Copy three sprites into a temporary direct page buffer
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LDA_IL equ $A7 ; lda [dp]
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LDA_ILY equ $B7 ; lda [dp],y
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AND_IL equ $27 ; and [dp]
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AND_ILY equ $37 ; and [dp],y
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CopyThreeSprites
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lda TileStore+TS_VBUFF_ADDR_0,y
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sta spriteIdx
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lda TileStore+TS_VBUFF_ADDR_1,y
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sta spriteIdx+4
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lda TileStore+TS_VBUFF_ADDR_2,y
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sta spriteIdx+8
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]line equ 0
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lup 8
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ldy #]line*SPRITE_PLANE_SPAN
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lda (spriteIdx+8),y
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db AND_ILY,spriteIdx+4 ; Can't use long indirect inside LUP because of ']'
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ora (spriteIdx+4),y
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db AND_ILY,spriteIdx+0
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ora (spriteIdx+0),y
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sta tmp_sprite_data+{]line*4}
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db LDA_ILY,spriteIdx+8
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db AND_ILY,spriteIdx+4
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db AND_ILY,spriteIdx+0
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sta tmp_sprite_mask+{]line*4}
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ldy #]line*SPRITE_PLANE_SPAN+2
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lda (spriteIdx+8),y
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db AND_ILY,spriteIdx+4
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ora (spriteIdx+4),y
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db AND_ILY,spriteIdx+0
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ora (spriteIdx+0),y
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sta tmp_sprite_data+{]line*4}+2
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db LDA_ILY,spriteIdx+8
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db AND_ILY,spriteIdx+4
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db AND_ILY,spriteIdx+0
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sta tmp_sprite_mask+{]line*4}+2
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]line equ ]line+1
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--^
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; jmp FinishTile
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; Copy two sprites into a temporary direct page buffer
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CopyTwoSprites
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lda TileStore+TS_VBUFF_ADDR_0,y
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sta spriteIdx
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lda TileStore+TS_VBUFF_ADDR_1,y
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sta spriteIdx+4
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]line equ 0
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lup 8
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ldy #]line*SPRITE_PLANE_SPAN
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lda (spriteIdx+4),y
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db AND_ILY,spriteIdx+0
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ora (spriteIdx+0),y
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sta tmp_sprite_data+{]line*4}
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db LDA_ILY,spriteIdx+4
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db AND_ILY,spriteIdx+0
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sta tmp_sprite_mask+{]line*4}
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ldy #]line*SPRITE_PLANE_SPAN+2
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lda (spriteIdx+4),y
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db AND_ILY,spriteIdx+0
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ora (spriteIdx+0),y
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sta tmp_sprite_data+{]line*4}+2
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db LDA_ILY,spriteIdx+4
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db AND_ILY,spriteIdx+0
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sta tmp_sprite_mask+{]line*4}+2
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]line equ ]line+1
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--^
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; jmp FinishTile
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CopyOneSprite
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clc
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lda TileStore+TS_VBUFF_ADDR_0,y
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sta spriteIdx
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adc #2
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sta spriteIdx+4
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]line equ 0
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lup 8
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; ldal tiledata,x
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; and [spriteIdx]
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; ora (spriteIdx)
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; sta tmp_sprite_data+{]line*4}
|
||||
|
||||
ldal spritedata+{]line*SPRITE_PLANE_SPAN},x
|
||||
sta tmp_sprite_data+{]line*4}
|
||||
ldal spritedata+{]line*SPRITE_PLANE_SPAN}+2,x
|
||||
sta tmp_sprite_data+{]line*4}+2
|
||||
|
||||
ldal spritemask+{]line*SPRITE_PLANE_SPAN},x
|
||||
sta tmp_sprite_mask+{]line*4}
|
||||
ldal spritemask+{]line*SPRITE_PLANE_SPAN}+2,x
|
||||
sta tmp_sprite_mask+{]line*4}+2
|
||||
]line equ ]line+1
|
||||
--^
|
||||
|
||||
; jmp FinishTile
|
||||
|
||||
; Reference all of the tile rendering subroutines defined in the TileXXXXX files. Each file defines
|
||||
; 8 entry points:
|
||||
;
|
||||
; One set for normal, horizontally flipped, vertically flipped and hors & vert flipped.
|
||||
; A second set that are optimized for when EngineMode has BG1 disabled.
|
||||
TileProcs dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 00000 : normal tiles
|
||||
dw _TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00 ; 00001 : dynamic tiles
|
||||
dw _TBMaskedTile_00,_TBMaskedTile_0H,_TBMaskedTile_V0,_TBMaskedTile_VH ; 00010 : masked normal tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00 ; 00011 : masked dynamic tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00
|
||||
|
||||
; Fringe tiles not supported yet, so just repeat the block from above
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 00100 : fringed normal tiles
|
||||
dw _TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00 ; 00101 : fringed dynamic tiles
|
||||
dw _TBMaskedTile_00,_TBMaskedTile_0H,_TBMaskedTile_V0,_TBMaskedTile_VH ; 00110 : fringed masked normal tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00 ; 00111 : fringed masked dynamic tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00
|
||||
|
||||
; High-priority tiles without a sprite in front of them are just normal tiles. Repeat the top half
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 01000 : high-priority normal tiles
|
||||
dw _TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00 ; 01001 : high-priority dynamic tiles
|
||||
dw _TBMaskedTile_00,_TBMaskedTile_0H,_TBMaskedTile_V0,_TBMaskedTile_VH ; 01010 : high-priority masked normal tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00 ; 01011 : high-priority masked dynamic tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00
|
||||
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 01100 : high-priority fringed normal tiles
|
||||
dw _TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00,_TBDynamicTile_00 ; 01101 : high-priority fringed dynamic tiles
|
||||
dw _TBMaskedTile_00,_TBMaskedTile_0H,_TBMaskedTile_V0,_TBMaskedTile_VH ; 01110 : high-priority fringed masked normal tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00 ; 01111 : high-priority fringed masked dynamic tiles
|
||||
dw _TBDynamicMaskTile_00,_TBDynamicMaskTile_00
|
||||
|
||||
; Here are all the sprite variants of the tiles
|
||||
dw _TBSolidSpriteTile_00,_TBSolidSpriteTile_0H
|
||||
dw _TBSolidSpriteTile_V0,_TBSolidSpriteTile_VH ; 10000 : normal tiles w/sprite
|
||||
dw _TBDynamicSpriteTile_00,_TBDynamicSpriteTile_00
|
||||
dw _TBDynamicSpriteTile_00,_TBDynamicSpriteTile_00 ; 10001 : dynamic tiles w/sprite
|
||||
dw _TBMaskedSpriteTile_00,_TBMaskedSpriteTile_0H
|
||||
dw _TBMaskedSpriteTile_V0,_TBMaskedSpriteTile_VH ; 10010 : masked normal tiles w/sprite
|
||||
dw _TBDynamicMaskedSpriteTile_00,_TBDynamicMaskedSpriteTile_00
|
||||
dw _TBDynamicMaskedSpriteTile_00,_TBDynamicMaskedSpriteTile_00 ; 10011 : masked dynamic tiles w/sprite
|
||||
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 10100 : fringed normal tiles w/sprite
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 10101 : fringed dynamic tiles w/sprite
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 10110 : fringed masked normal tiles w/sprite
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 10111 : fringed masked dynamic tiles w/sprite
|
||||
|
||||
dw _TBSolidPrioritySpriteTile_00,_TBSolidPrioritySpriteTile_0H,
|
||||
dw _TBSolidPrioritySpriteTile_V0,_TBSolidPrioritySpriteTile_VH ; 11000 : high-priority normal tiles w/sprite
|
||||
dw _TBDynamicPrioritySpriteTile_00,_TBDynamicPrioritySpriteTile_00
|
||||
dw _TBDynamicPrioritySpriteTile_00,_TBDynamicPrioritySpriteTile_00 ; 11001 : high-priority dynamic tiles w/sprite
|
||||
dw _TBMaskedPrioritySpriteTile_00,_TBMaskedPrioritySpriteTile_0H
|
||||
dw _TBMaskedPrioritySpriteTile_V0,_TBMaskedPrioritySpriteTile_VH ; 11010 : high-priority masked normal tiles w/sprite
|
||||
dw _TBDynamicMaskedPrioritySpriteTile_00,_TBDynamicMaskedPrioritySpriteTile_00
|
||||
dw _TBDynamicMaskedPrioritySpriteTile_00,_TBDynamicMaskedPrioritySpriteTile_00 ; 11011 : high-priority masked dynamic tiles w/sprite
|
||||
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 11100 : high-priority fringed normal tiles w/sprite
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 11101 : high-priority fringed dynamic tiles w/sprite
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 11110 : high-priority fringed masked normal tiles w/sprite
|
||||
dw _TBSolidTile_00,_TBSolidTile_0H,_TBSolidTile_V0,_TBSolidTile_VH ; 11111 : high-priority fringed masked dynamic tiles w/sprite
|
||||
|
||||
; _TBConstTile
|
||||
;
|
||||
; A specialized routine that fills in a tile with a single constant value. It's intended to be used to
|
||||
; fill in solid colors, so there are no specialized horizontal or verical flipped variants
|
||||
_TBConstTile
|
||||
sta: $0001,y
|
||||
sta: $0004,y
|
||||
sta $1001,y
|
||||
sta $1004,y
|
||||
sta $2001,y
|
||||
sta $2004,y
|
||||
sta $3001,y
|
||||
sta $3004,y
|
||||
sta $4001,y
|
||||
sta $4004,y
|
||||
sta $5001,y
|
||||
sta $5004,y
|
||||
sta $6001,y
|
||||
sta $6004,y
|
||||
sta $7001,y
|
||||
sta $7004,y
|
||||
jmp _TBFillPEAOpcode
|
||||
|
||||
ClearTile
|
||||
and #$00FF
|
||||
ora #$4800
|
||||
sta: $0004,y
|
||||
sta $1004,y
|
||||
sta $2004,y
|
||||
sta $3004,y
|
||||
sta $4004,y
|
||||
sta $5004,y
|
||||
sta $6004,y
|
||||
sta $7004,y
|
||||
inc
|
||||
inc
|
||||
sta: $0001,y
|
||||
sta $1001,y
|
||||
sta $2001,y
|
||||
sta $3001,y
|
||||
sta $4001,y
|
||||
sta $5001,y
|
||||
sta $6001,y
|
||||
sta $7001,y
|
||||
|
||||
sep #$20
|
||||
lda #$B1 ; This is a special case where we can set all the words to LDA (DP),y
|
||||
sta: $0000,y
|
||||
sta: $0003,y
|
||||
sta $1000,y
|
||||
sta $1003,y
|
||||
sta $2000,y
|
||||
sta $2003,y
|
||||
sta $3000,y
|
||||
sta $3003,y
|
||||
sta $4000,y
|
||||
sta $4003,y
|
||||
sta $5000,y
|
||||
sta $5003,y
|
||||
sta $6000,y
|
||||
sta $6003,y
|
||||
sta $7000,y
|
||||
sta $7003,y
|
||||
rep #$20
|
||||
rts
|
||||
|
||||
; CopyBG0Tile
|
||||
;
|
||||
; A low-level function that copies 8x8 tiles directly into the code field space.
|
||||
;
|
||||
; A = Tile ID (0 - 511)
|
||||
; X = Tile column (0 - 40)
|
||||
; Y = Tile row (0 - 25)
|
||||
_CopyBG0Tile
|
||||
phb ; save the current bank
|
||||
phx ; save the original x-value
|
||||
pha ; save the tile ID
|
||||
|
||||
tya ; lookup the address of the virtual line (y * 8)
|
||||
asl
|
||||
asl
|
||||
asl
|
||||
asl ; x2 because the table contains words, not
|
||||
tay
|
||||
|
||||
sep #$20 ; set the bank register
|
||||
lda BTableHigh,y
|
||||
pha ; save for a few instruction
|
||||
rep #$20
|
||||
|
||||
txa
|
||||
asl ; there are two columns per tile, so multiple by 4
|
||||
asl ; asl will clear the carry bit
|
||||
tax
|
||||
|
||||
lda BTableLow,y
|
||||
sta _BASE_ADDR ; Used in masked tile renderer
|
||||
clc
|
||||
adc Col2CodeOffset+2,x ; Get the right edge (which is the lower physical address)
|
||||
tay
|
||||
|
||||
plb ; set the bank
|
||||
pla ; pop the tile ID
|
||||
; jsr _RenderTile
|
||||
|
||||
:exit
|
||||
plx ; pop the x-register
|
||||
plb ; restore the data bank and return
|
||||
rts
|
||||
|
||||
|
||||
; CopyBG1Tile
|
||||
;
|
||||
; A low-level function that copies 8x8 tiles directly into the BG1 data buffer.
|
||||
;
|
||||
; A = Tile ID (0 - 511)
|
||||
; X = Tile column (0 - 40)
|
||||
; Y = Tile row (0 - 25)
|
||||
_CopyBG1Tile
|
||||
phb ; save the current bank
|
||||
phx ; save the original x-value
|
||||
pha ; save the tile ID
|
||||
|
||||
tya ; lookup the address of the virtual line (y * 8)
|
||||
asl
|
||||
asl
|
||||
asl
|
||||
asl
|
||||
tay
|
||||
|
||||
txa
|
||||
asl
|
||||
asl ; 4 bytes per tile column
|
||||
clc
|
||||
adc BG1YTable,y
|
||||
tay
|
||||
|
||||
sep #$20
|
||||
lda BG1DataBank
|
||||
pha
|
||||
plb ; set the bank
|
||||
rep #$20
|
||||
|
||||
pla ; pop the tile ID
|
||||
jsr _RenderTileBG1
|
||||
|
||||
plx ; pop the x-register
|
||||
plb ; restore the data bank and return
|
||||
rts
|
||||
|
||||
; Tile Store that holds tile records which contain all the essential information for rendering
|
||||
; a tile.
|
||||
;
|
||||
; TileStore+TS_TILE_ID : Tile descriptor
|
||||
; TileStore+TS_DIRTY : $0000 is clean, any other value indicated a dirty tile
|
||||
; TileStore+TS_TILE_ADDR : Address of the tile in the tile data buffer
|
||||
; TileStore+TS_CODE_ADDR_LOW : Low word of the address in the code field that receives the tile
|
||||
; TileStore+TS_CODE_ADDR_HIGH : High word of the address in the code field that receives the tile
|
||||
; TileStore+TS_WORD_OFFSET : Logical number of word for this location
|
||||
; TileStore+TS_BASE_ADDR : Copy of BTableAddrLow
|
||||
; TileStore+TS_SCREEN_ADDR : Address on the physical screen corresponding to this tile (for direct rendering)
|
||||
; TileStore+TS_SPRITE_FLAG : A bit field of all sprites that intersect this tile
|
||||
; TileStore+TS_SPRITE_ADDR_1 ; Address of the sprite data that aligns with this tile. These
|
||||
; TileStore+TS_SPRITE_ADDR_2 ; values are 1:1 with the TS_SPRITE_FLAG bits and are not contiguous.
|
||||
; TileStore+TS_SPRITE_ADDR_3 ; If the bit position in TS_SPRITE_FLAG is not set, then the value in
|
||||
; TileStore+TS_SPRITE_ADDR_4 ; the TS_SPRITE_ADDR_* field is undefined.
|
||||
; TileStore+TS_SPRITE_ADDR_5
|
||||
; TileStore+TS_SPRITE_ADDR_6
|
||||
; TileStore+TS_SPRITE_ADDR_7
|
||||
; TileStore+TS_SPRITE_ADDR_8
|
||||
; TileStore+TS_SPRITE_ADDR_9
|
||||
; TileStore+TS_SPRITE_ADDR_10
|
||||
; TileStore+TS_SPRITE_ADDR_11
|
||||
; TileStore+TS_SPRITE_ADDR_12
|
||||
; TileStore+TS_SPRITE_ADDR_13
|
||||
; TileStore+TS_SPRITE_ADDR_14
|
||||
; TileStore+TS_SPRITE_ADDR_15
|
||||
; TileStore+TS_SPRITE_ADDR_16
|
||||
|
||||
; To make processing the tile faster, we do them in chunks of eight. This allows the loop to be
|
||||
; unrolled, which means we don't have to keep track of the register value and makes it faster to
|
||||
; clear the dirty tile flag after being processed.
|
||||
; _ApplyTilesUnrolled
|
||||
tdc ; Move to the dedicated direct page for tile rendering
|
||||
clc
|
||||
adc #$100
|
||||
tcd
|
||||
|
||||
phb ; Save the current bank
|
||||
tsc
|
||||
sta tmp0 ; Save it on the direct page
|
||||
bra at_loop
|
||||
|
||||
; The DirtyTiles array and the TileStore information is in the Tile Store bank. Because we
|
||||
; process up to 8 tiles as a time and the tile code sets the bank register to the target
|
||||
; code field bank, we need to restore the bank register each time. So, we pre-push
|
||||
; 8 copies of the TileStore bank onto the stack.
|
||||
|
||||
|
||||
at_exit
|
||||
tdc ; Move back to the original direct page
|
||||
sec
|
||||
sbc #$100
|
||||
tcd
|
||||
|
||||
plb ; Restore the original data bank and return
|
||||
rts
|
||||
dt_base equ $FE ; top of second direct page space
|
||||
|
||||
at_loop
|
||||
lda tmp0
|
||||
tcs
|
||||
|
||||
lda DirtyTileCount ; This is pre-multiplied by 2
|
||||
beq at_exit ; If there are no items, exit
|
||||
|
||||
ldx TileStoreBankDoubled
|
||||
phx
|
||||
phx
|
||||
phx
|
||||
|
||||
cmp #16 ; If there are >= 8 elements, then
|
||||
bcs at_chunk ; do a full chunk
|
||||
|
||||
stz DirtyTileCount ; Otherwise, this pass will handle them all
|
||||
tax
|
||||
jmp (at_table,x)
|
||||
at_table da at_exit,at_one,at_two,at_three
|
||||
da at_four,at_five,at_six,at_seven
|
||||
|
||||
at_chunk sec
|
||||
sbc #16
|
||||
sta DirtyTileCount ; Fall through
|
||||
|
||||
; Because all of the registers get used in the _RenderTile2 subroutine, we
|
||||
; push the values from the DirtyTiles array onto the stack and then pop off
|
||||
; the values as we go
|
||||
|
||||
ldy dt_base ; Reload the base index
|
||||
ldx DirtyTiles+14,y ; Load the TileStore offset
|
||||
stz TileStore+TS_DIRTY,x ; Clear this tile's dirty flag
|
||||
jsr _RenderTile2 ; Draw the tile
|
||||
plb ; Reset the data bank to the TileStore bank
|
||||
|
||||
at_seven
|
||||
ldy dt_base
|
||||
ldx DirtyTiles+12,y
|
||||
stz TileStore+TS_DIRTY,x
|
||||
jsr _RenderTile2
|
||||
plb
|
||||
|
||||
at_six
|
||||
ldy dt_base
|
||||
ldx DirtyTiles+10,y
|
||||
stz TileStore+TS_DIRTY,x
|
||||
jsr _RenderTile2
|
||||
plb
|
||||
|
||||
at_five
|
||||
ldy dt_base
|
||||
ldx DirtyTiles+8,y
|
||||
stz TileStore+TS_DIRTY,x
|
||||
jsr _RenderTile2
|
||||
plb
|
||||
|
||||
at_four
|
||||
ldy dt_base
|
||||
ldx DirtyTiles+6,y
|
||||
stz TileStore+TS_DIRTY,x
|
||||
jsr _RenderTile2
|
||||
plb
|
||||
|
||||
at_three
|
||||
ldy dt_base
|
||||
ldx DirtyTiles+4,y
|
||||
jsr _RenderTile2
|
||||
plb
|
||||
|
||||
at_two
|
||||
ldy dt_base
|
||||
ldx DirtyTiles+2,y
|
||||
stz TileStore+TS_DIRTY,x
|
||||
jsr _RenderTile2
|
||||
plb
|
||||
|
||||
at_one
|
||||
ldy dt_base
|
||||
ldx DirtyTiles+0,y
|
||||
stz TileStore+TS_DIRTY,x
|
||||
jsr _RenderTile2
|
||||
plb
|
||||
|
||||
jmp at_loop
|
||||
|
|
@ -1,92 +0,0 @@
|
|||
; Functions to handle rendering sprites into 8x8 tile buffers for dirty tile rendering. Because we
|
||||
; are rendering directly to the graphics screen instead of the code field, we can map the direct
|
||||
; page into Bank 01 and use that to avoid writing the merge sprite and tile data to an intermediate
|
||||
; buffer.
|
||||
|
||||
;DirtyTileSpriteProcs dw _TBDirtySpriteTile_00,_TBDirtySpriteTile_0H,_TBDirtySpriteTile_V0,_TBDirtySpriteTile_VH
|
||||
|
||||
; Optimization Note: The single-sprite blitter seems like it could be made faster by taking advantage of
|
||||
; the fact that only a single set of sprite data needs to be read, but the extra overhead
|
||||
; of using the direct page and setting up and restoring registers wipes out the 2 cycle
|
||||
; per word advantage.
|
||||
;
|
||||
; A = screen address
|
||||
; X = address of sprite data
|
||||
; Y = address of tile data
|
||||
; B = tile data bank
|
||||
|
||||
_OneDirtySprite_00
|
||||
_OneDirtySprite_0H
|
||||
|
||||
phd
|
||||
sei
|
||||
clc
|
||||
tcd
|
||||
_R0W1
|
||||
|
||||
_ODS_Line 0,0,$0
|
||||
_ODS_Line 1,1,$A0
|
||||
tdc
|
||||
adc #320
|
||||
tcd
|
||||
_ODS_Line 2,2,$0
|
||||
_ODS_Line 3,3,$A0
|
||||
tdc
|
||||
adc #320
|
||||
tcd
|
||||
_ODS_Line 4,4,$0
|
||||
_ODS_Line 5,5,$A0
|
||||
tdc
|
||||
adc #320
|
||||
tcd
|
||||
_ODS_Line 6,6,$0
|
||||
_ODS_Line 7,7,$A0
|
||||
|
||||
_R0W0
|
||||
cli
|
||||
pld
|
||||
rts
|
||||
|
||||
|
||||
_OneDirtySprite_V0
|
||||
_OneDirtySprite_VH
|
||||
phd
|
||||
sei
|
||||
clc
|
||||
tcd
|
||||
_R0W1
|
||||
|
||||
_ODS_Line 0,7,$0
|
||||
_ODS_Line 1,6,$A0
|
||||
tdc
|
||||
adc #320
|
||||
tcd
|
||||
_ODS_Line 2,5,$0
|
||||
_ODS_Line 3,4,$A0
|
||||
tdc
|
||||
adc #320
|
||||
tcd
|
||||
_ODS_Line 4,3,$0
|
||||
_ODS_Line 5,2,$A0
|
||||
tdc
|
||||
adc #320
|
||||
tcd
|
||||
_ODS_Line 6,1,$0
|
||||
_ODS_Line 7,0,$A0
|
||||
|
||||
_R0W0
|
||||
cli
|
||||
pld
|
||||
rts
|
||||
|
||||
|
||||
; Build up from here
|
||||
_FourDirtySprites
|
||||
lda TileStore+TS_VBUFF_ADDR_0,y
|
||||
sta spriteIdx
|
||||
lda TileStore+TS_VBUFF_ADDR_1,y
|
||||
sta spriteIdx+4
|
||||
lda TileStore+TS_VBUFF_ADDR_2,y
|
||||
sta spriteIdx+8
|
||||
lda TileStore+TS_VBUFF_ADDR_3,y
|
||||
sta spriteIdx+12
|
||||
|
|
@ -1,150 +0,0 @@
|
|||
; Functions to handle rendering sprite information into buffers for updates to the
|
||||
; code field. Due to lack of parallel structure, the sprites are combined with the
|
||||
; tile data and then written to a single direct page buffer. The data is read from
|
||||
; this buffer and then applied to the code field
|
||||
|
||||
; Merge a single block of sprite data with a tile
|
||||
_OneSprite_00
|
||||
_OneSprite_H0
|
||||
ldx TileStore+TS_VBUFF_ADDR_0,y
|
||||
lda TileStore+TS_TILE_ADDR,y
|
||||
tay
|
||||
|
||||
]line equ 0
|
||||
lup 8
|
||||
lda tiledata+{]line*TILE_DATA_SPAN},y
|
||||
andl spritemask+{]line*SPRITE_PLANE_SPAN},x
|
||||
oral spritedata+{]line*SPRITE_PLANE_SPAN},x
|
||||
sta tmp_sprite_data+{]line*4}
|
||||
|
||||
lda tiledata+{]line*TILE_DATA_SPAN}+2,y
|
||||
andl spritemask+{]line*SPRITE_PLANE_SPAN}+2,x
|
||||
oral spritedata+{]line*SPRITE_PLANE_SPAN}+2,x
|
||||
sta tmp_sprite_data+{]line*4}+2
|
||||
]line equ ]line+1
|
||||
--^
|
||||
|
||||
_OneSprite_V0
|
||||
_OneSprite_VH
|
||||
ldx TileStore+TS_VBUFF_ADDR_0,y
|
||||
lda TileStore+TS_TILE_ADDR,y
|
||||
tay
|
||||
|
||||
]line equ 7
|
||||
]dest equ 0
|
||||
lup 8
|
||||
lda tiledata+{]line*TILE_DATA_SPAN},y
|
||||
andl spritemask+{]dest*SPRITE_PLANE_SPAN},x
|
||||
oral spritedata+{]dest*SPRITE_PLANE_SPAN},x
|
||||
sta tmp_sprite_data+{]dest*4}
|
||||
|
||||
lda tiledata+{]line*TILE_DATA_SPAN}+2,y
|
||||
andl spritemask+{]dest*SPRITE_PLANE_SPAN}+2,x
|
||||
oral spritedata+{]dest*SPRITE_PLANE_SPAN}+2,x
|
||||
sta tmp_sprite_data+{]dest*4}+2
|
||||
]line equ ]line-1
|
||||
]dest equ ]dest+1
|
||||
--^
|
||||
rts
|
||||
|
||||
|
||||
; Merge two blocks of sprite data. This is more involved because we need to use the
|
||||
; direct page pointers to stack the sprite information
|
||||
_TwoSprite_00
|
||||
_TwoSprite_H0
|
||||
lda TileStore+TS_VBUFF_ADDR_0,y
|
||||
sta sprite_0
|
||||
lda TileStore+TS_VBUFF_ADDR_1,y
|
||||
sta sprite_1
|
||||
ldx TileStore+TS_TILE_ADDR,y
|
||||
|
||||
; line 0
|
||||
lda tiledata+{0*TILE_DATA_SPAN},x
|
||||
and [sprite_1]
|
||||
ora (sprite_1)
|
||||
and [sprite_0]
|
||||
ora (sprite_0)
|
||||
sta tmp_sprite_data+{0*4}
|
||||
|
||||
ldy #{0*SPRITE_PLANE_SPAN}+2
|
||||
lda tiledata+{0*TILE_DATA_SPAN}+2,x
|
||||
and [sprite_1],y
|
||||
ora (sprite_1),y
|
||||
and [sprite_0],y
|
||||
ora (sprite_0),y
|
||||
sta tmp_sprite_data+{0*4}+2
|
||||
|
||||
; line 1
|
||||
ldy #{1*SPRITE_PLANE_SPAN}
|
||||
lda tiledata+{1*TILE_DATA_SPAN},x
|
||||
and [sprite_1],y
|
||||
ora (sprite_1),y
|
||||
and [sprite_0],y
|
||||
ora (sprite_0),y
|
||||
sta tmp_sprite_data+{1*4}
|
||||
|
||||
ldy #{1*SPRITE_PLANE_SPAN}+2
|
||||
lda tiledata+{1*TILE_DATA_SPAN}+2,x
|
||||
and [sprite_1],y
|
||||
ora (sprite_1),y
|
||||
and [sprite_0],y
|
||||
ora (sprite_0),y
|
||||
sta tmp_sprite_data+{1*4}+2
|
||||
|
||||
rts
|
||||
|
||||
|
||||
; Merge three blocks of sprite data. This is more involved because we need to use the
|
||||
; direct page pointers to stack the sprite information
|
||||
_ThreeSprite_00
|
||||
_ThreeSprite_H0
|
||||
lda TileStore+TS_VBUFF_ADDR_0,y
|
||||
sta sprite_0
|
||||
lda TileStore+TS_VBUFF_ADDR_1,y
|
||||
sta sprite_1
|
||||
lda TileStore+TS_VBUFF_ADDR_2,y
|
||||
sta sprite_2
|
||||
ldx TileStore+TS_TILE_ADDR,y
|
||||
|
||||
; line 0
|
||||
lda tiledata+{0*TILE_DATA_SPAN},x
|
||||
and [sprite_2]
|
||||
ora (sprite_2)
|
||||
and [sprite_1]
|
||||
ora (sprite_1)
|
||||
and [sprite_0]
|
||||
ora (sprite_0)
|
||||
sta tmp_sprite_data+{0*4}
|
||||
|
||||
ldy #{0*SPRITE_PLANE_SPAN}+2
|
||||
lda tiledata+{0*TILE_DATA_SPAN}+2,x
|
||||
and [sprite_2],y
|
||||
ora (sprite_2),y
|
||||
and [sprite_1],y
|
||||
ora (sprite_1),y
|
||||
and [sprite_0],y
|
||||
ora (sprite_0),y
|
||||
sta tmp_sprite_data+{0*4}+2
|
||||
|
||||
; line 1
|
||||
ldy #{1*SPRITE_PLANE_SPAN}
|
||||
lda tiledata+{1*TILE_DATA_SPAN},x
|
||||
and [sprite_2],y
|
||||
ora (sprite_2),y
|
||||
and [sprite_1],y
|
||||
ora (sprite_1),y
|
||||
and [sprite_0],y
|
||||
ora (sprite_0),y
|
||||
sta tmp_sprite_data+{1*4}
|
||||
|
||||
ldy #{1*SPRITE_PLANE_SPAN}+2
|
||||
lda tiledata+{1*TILE_DATA_SPAN}+2,x
|
||||
and [sprite_2],y
|
||||
ora (sprite_2),y
|
||||
and [sprite_1],y
|
||||
ora (sprite_1),y
|
||||
and [sprite_0],y
|
||||
ora (sprite_0),y
|
||||
sta tmp_sprite_data+{1*4}+2
|
||||
|
||||
rts
|
||||
|
|
@ -1,43 +0,0 @@
|
|||
; A collection of tile blitters used in the dirty renderer. These renderers copy data directly
|
||||
; to the graphics screen. Also, because the dirty render assumes that the screen is not moving,
|
||||
; there is no support for two layer tiles.
|
||||
|
||||
; Address table of the rendering functions
|
||||
DirtyTileProcs dw _TBDirtyTile_00,_TBDirtyTile_0H,_TBDirtyTile_V0,_TBDirtyTile_VH
|
||||
|
||||
; Normal and horizontally flipped tiles. The horizontal variant is selected by choosing
|
||||
; and appropriate value for the X register, so these can share the same code.
|
||||
;
|
||||
; B = Bank 01
|
||||
; X = address of tile data
|
||||
; Y = screen address
|
||||
_TBDirtyTile_00
|
||||
_TBDirtyTile_0H
|
||||
]line equ 0
|
||||
lup 8
|
||||
ldal tiledata+{]line*4},x
|
||||
sta: $0000+{]line*160},y
|
||||
ldal tiledata+{]line*4}+2,x
|
||||
sta: $0002+{]line*160},y
|
||||
]line equ ]line+1
|
||||
--^
|
||||
rts
|
||||
|
||||
; Vertically flipped tile renderers
|
||||
;
|
||||
; B = Bank 01
|
||||
; X = address of tile data
|
||||
; Y = screen address
|
||||
_TBDirtyTile_V0
|
||||
_TBDirtyTile_VH
|
||||
]line equ 7
|
||||
]dest equ 0
|
||||
lup 8
|
||||
ldal tiledata+{]line*4},x
|
||||
sta: $0000+{]dest*160},y
|
||||
ldal tiledata+{]line*4}+2,x
|
||||
sta: $0002+{]dest*160},y
|
||||
]line equ ]line-1
|
||||
]dest equ ]dest+1
|
||||
--^
|
||||
rts
|
||||
Loading…
Reference in New Issue