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b2ead87d25
| Author | SHA1 | Date |
|---|---|---|
Lucas Scharenbroich
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b2ead87d25 | |
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Lucas Scharenbroich
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ab202470a9 |
175
demos/smb/Main.s
175
demos/smb/Main.s
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@ -87,6 +87,7 @@ FTblTmp equ 228
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; Initialize the sound hardware for APU emulation
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lda #2 ; 0 = 240Hz, 1 = 120Hz, 2 = 60Hz (external)
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jsr APUStartUp
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; Start up GTE to drive the graphics
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@ -119,6 +120,12 @@ FTblTmp equ 228
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pea #NESTileBlitter
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_GTESetAddress
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; Install a custom tile callback to draw tiles directly on the screen w/proper palettes
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; pea userTileDirectCallback
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; pea #^NESDirectTileBlitter
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; pea #NESDirectTileBlitter
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; _GTESetAddress
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; Get the address of a low-level routine that can be used to draw a tile directly to the graphics screen
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; pea rawDrawTile
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; _GTEGetAddress
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@ -132,8 +139,12 @@ FTblTmp equ 228
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; Initialize the graphics screen playfield (256x160). The NES is 240 lines high, so 160
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; is a reasonable compromise.
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; pea #128
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; pea #184
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pea #128
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pea #200
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; pea #80
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; pea #144
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_GTESetScreenMode
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@ -183,6 +194,9 @@ FTblTmp equ 228
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pla
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sta OldOneSec
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; Show the configuration screen
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; jsr ShowConfig
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; Set an internal flag to tell the VBL interrupt handler that it is
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; ok to start invoking the game logic. The ROM code has to be run
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; at 60 Hz because it controls the audio. Bad audio is way worse
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@ -368,8 +382,15 @@ EvtLoop
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ldy #33
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jsr CopyNametable
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brl EvtLoop
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:not_v
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cmp #'t' ; show VBL interrupt time
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bne :not_t
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lda show_vbl_cpu
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eor #1
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sta show_vbl_cpu
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brl EvtLoop
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:not_t
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cmp #'q'
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beq Exit
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brl EvtLoop
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@ -393,7 +414,9 @@ singleStepMode dw 0
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nmiCount dw 0
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DPSave dw 0
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LastAreaType dw 0
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frameCount dw 0
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frameCount dw 0
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show_vbl_cpu dw 0
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; Toggle an APU control bit
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ToggleAPUChannel
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pha
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@ -472,6 +495,17 @@ RenderFrame
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sta OldROMScrollEdge ; Stash a copy for the next round through
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lsr
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pha
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; Get the player's Y coordinate and determine of we need to adjust the camera based on the physical play field size
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; sep #$20
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; ldal ROMBase+$b5 ; Player_Y_HighPos
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; xba
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; ldal ROMBase+$ce ; Player_Y_Position
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; rep #$20
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;
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; sec
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; sbc TopClip ; If we're hiding the
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pea $0000
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_GTESetBG0Origin
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@ -535,6 +569,122 @@ AreaPalettes dw WaterPalette,Area1Palette,Area2Palette,Area3Palette,Area4Pale
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SwizzleTables adrl AT0_T0,AT1_T0,AT2_T0,AT3_T0,AT2_T0
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SwizzlePtr adrl AT1_T0
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; Draw PPU tiles to the screen for a UI
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;
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; 0 - 9 starts at tile 256
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; A - Z starts at tile 266
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; mushroom is $1CE = 462
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TILE_ZERO equ 256
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TILE_A equ 266
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TILE_SHROOM equ 462
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ShowConfig
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lda #0
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jsr SetAreaType
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lda #$0000
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stal $E19E00
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ldx #TILE_SHROOM+TILE_USER_BIT
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:loop
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phx
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phx
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pea $2000
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pea $0000 ; Bits 1-2, 5 and 7 are valid
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_GTEDrawTileToScreen
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ldx #msg1
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ldy #$2000+{8*160}
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lda #$0000
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jsr ConfigDrawString
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ldx #msg1
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ldy #$2000+{16*160}
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lda #$0001
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jsr ConfigDrawString
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ldx #msg1
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ldy #$2000+{24*160}
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lda #$0002
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jsr ConfigDrawString
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ldx #msg1
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ldy #$2000+{32*160}
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lda #$0003
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jsr ConfigDrawString
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:waitloop
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pha
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_GTEReadControl
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pla
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bit #PAD_KEY_DOWN
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beq :waitloop
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plx
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and #$007F
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cmp #LEFT_ARROW
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beq :decrement
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cmp #RIGHT_ARROW
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beq :increment
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rts
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:increment
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inx
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inx
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:decrement dex
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bra :loop
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; X = string pointer
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; Y = address
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ConfigDrawString
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stx Tmp0
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sty Tmp1
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sta Tmp2
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lda (Tmp0)
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and #$00FF
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tax
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ldy #1
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:loop
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phx
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phy
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lda (Tmp0),y
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and #$007F
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cmp #'A'
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bcc :not_letter
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sbc #'A'
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clc
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adc #TILE_A
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bra :draw
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:not_letter
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cmp #'0'
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bcc :skip
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sbc #'0'
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clc
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adc #TILE_ZERO
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:draw
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ora #TILE_USER_BIT
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pha
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pei Tmp1
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pei Tmp2 ; palette select
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_GTEDrawTileToScreen
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:skip
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lda Tmp1
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clc
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adc #4
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sta Tmp1
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ply
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plx
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iny
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dex
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bne :loop
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rts
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msg1 str 'HELLO 123'
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; Take a PPU address and convert it to a tile store coordinate
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;
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; Inputs
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@ -1021,7 +1171,7 @@ CopyNametable
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ldx Tmp2 ; Nametable address
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lda PPU_MEM+$2000,x
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and #$00FF
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ora #$0100+TILE_USER_BIT ; USe top 256 tiles and set as a user-defined tile
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ora #$0100+TILE_USER_BIT ; Use top 256 tiles and set as a user-defined tile
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pha
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jsr GetPaletteSelect
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ora 1,s ; Merge bits 9 and 10 into the Tile ID that's on the stack
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@ -1072,6 +1222,10 @@ CopyNametable
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; Trigger an NMI in the ROM
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triggerNMI
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sep #$30
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jsl quarter_speed_driver
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rep #$30
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ldal ppuctrl ; If the ROM has not enabled VBL NMI, also skip
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bit #$80
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beq :skip
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@ -1617,20 +1771,25 @@ nmiTask
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ldal singleStepMode
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bne :no_nmi
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; lda #1
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; jsr setborder
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ldal show_vbl_cpu
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beq :no_show_1
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jsr incborder
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:no_show_1
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jsr triggerNMI
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; lda #0
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; jsr setborder
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:no_nmi
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ldal show_vbl_cpu
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beq :no_nmi
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jsr decborder
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:no_nmi
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pld
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plb
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plp
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:skip
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rtl
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mx %00
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readInput
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110
demos/smb/apu.s
110
demos/smb/apu.s
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@ -31,6 +31,7 @@ access_doc_ram_no_inc = *
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mx %00
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APUStartUp
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stal apu_mode
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sei
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phd
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pea $c000
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@ -51,11 +52,16 @@ APUShutDown = *
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jsr stop_playing
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ldal apu_mode
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cmp #2
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beq :no_doc_interrupts
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lda backup_interrupt_ptr ; restore old interrupt ptr
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stal sound_interrupt_ptr
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lda backup_interrupt_ptr+2
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stal sound_interrupt_ptr+2
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:no_doc_interrupts
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cli
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pld
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clc
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@ -109,7 +115,7 @@ copy_instruments_to_doc
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lda #$0600
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jsr copy_noise
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lda #$8000
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; lda #$8000
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; jsr gen_noise
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rts
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@ -313,6 +319,10 @@ copy_register_config
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;--------------------------
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setup_interrupt = *
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ldal apu_mode
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cmp #2 ; mode 2 = external driver at 60Hz
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beq :no_doc_interrupts
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ldal sound_interrupt_ptr
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sta backup_interrupt_ptr
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ldal sound_interrupt_ptr+2
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@ -330,6 +340,19 @@ setup_interrupt = *
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sep #$20
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mx %10
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ldal apu_mode
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beq :do_240hz
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lda #598
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ldy #598/256
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bra :set_timer_freq
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:do_240hz lda #1195
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ldy #1195/256
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:set_timer_freq
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stal timer_sound_settings+1 ; low byte of timer frequency
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tya
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stal timer_sound_settings+3 ; high byte of timer frequency
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jsr access_doc_registers
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ldy #0
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@ -344,7 +367,7 @@ setup_interrupt = *
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rep #$20
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mx %00
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:no_doc_interrupts
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rts
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interrupt_oscillator = 31
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@ -398,6 +421,7 @@ noise_sound_settings = *
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dfb $a0+noise_oscillator,0 ; mode register, set to free run
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backup_interrupt_ptr ds 4
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apu_mode ds 2
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;-----------------------------------------------------------------------------------------
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; APU internals
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@ -557,6 +581,45 @@ PULSE_CONST_VOL_FLAG equ $10
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NOISE_CONST_VOL_FLAG equ $10
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TRIANGLE_HALT_FLAG equ $80
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mx %11
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quarter_speed_driver = *
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phb
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phd
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phk
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plb
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pea $c000
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pld
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ldx apu_frame_counter
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inx
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inx
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cpx #2*apu_frame_steps ; TODO: This is set by MSB in $4017 (4 or 5). 4 = PAL, 5 = NTSC.
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bcc *+4
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ldx #0
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stx apu_frame_counter
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jmp (:frame_counter_proc,x)
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:frame_counter_proc da :quarter_frame,:half_frame,:quarter_frame,:no_frame_60,:half_frame
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; Quarter-speed interrupts (60Hz) -- clock four times in each handler
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:half_frame
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:quarter_frame
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jsr half_frame_clock
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jsr quarter_frame_clock
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jsr quarter_frame_clock
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jsr half_frame_clock
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jsr quarter_frame_clock
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jsr quarter_frame_clock
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brl update_doc_registers
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:no_frame_60
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pld
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plb
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clc
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rtl
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mx %11
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interrupt_handler = *
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@ -588,9 +651,7 @@ interrupt_handler = *
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beq *+5
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brl :not_timer ; Only service timer interrupts
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; Update the frame counter. We double-count so that frame counter can be used directly to dispatch to the
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; appropriate tick handler
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; Update the frame counter and leave the doubled countin x-register for dispatch
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ldx apu_frame_counter
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inx
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inx
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@ -598,31 +659,30 @@ interrupt_handler = *
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bcc *+4
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ldx #0
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stx apu_frame_counter
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jmp (:frame_counter_proc,x)
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:frame_counter_proc da :quarter_frame,:half_frame,:quarter_frame,:no_frame,:half_frame
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; Figure out which speed we are dispatching
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lda apu_mode
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beq :do_240hz_mode
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jmp (:apu_120hz_table,x)
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:do_240hz_mode jmp (:apu_240hz_table,x)
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:apu_240hz_table da :quarter_frame_240,:half_frame_240,:quarter_frame_240,no_frame,:half_frame_240
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:apu_120hz_table da :quarter_frame_120,:half_frame_120,:quarter_frame_120,no_frame,:half_frame_120
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; Full speed emulation (240Hz)
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:half_frame jsr half_frame_clock
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:quarter_frame jsr quarter_frame_clock
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:half_frame_240 jsr half_frame_clock
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:quarter_frame_240 jsr quarter_frame_clock
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bra update_doc_registers
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; Half-speed interrupts (120Hz) -- clock twice in each handler
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;:half_frame
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;:quarter_frame
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; jsr half_frame_clock
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; jsr quarter_frame_clock
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; jsr quarter_frame_clock
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; Quarter-speed interrupts (60Hz) -- clock four times in each handler
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;:half_frame
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;:quarter_frame
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; jsr half_frame_clock
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; jsr quarter_frame_clock
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; jsr quarter_frame_clock
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; jsr half_frame_clock
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; jsr quarter_frame_clock
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; jsr quarter_frame_clock
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:half_frame_120
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:quarter_frame_120
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jsr half_frame_clock
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jsr quarter_frame_clock
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jsr quarter_frame_clock
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; Apply any changes to the DOC registers
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update_doc_registers
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jsr access_doc_registers
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; Set the parameters for the first square wave channel.
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@ -802,8 +862,8 @@ interrupt_handler = *
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:high_pitch pla
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sta sound_data
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:no_frame
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:not_timer
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no_frame
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ldal show_border
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beq :no_show2
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ldal border_color
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@ -988,8 +988,11 @@ ScreenOff sta Mirror_PPU_CTRL_REG2 ;save bits for later but not in registe
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lda #$00
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jsr InitScroll
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jsr OAM_ADDR_W ;reset spr-ram address register
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lda #$02 ;perform spr-ram DMA access on $0200-$02ff
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jsr SPR_DMA_W
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; PPU harness just reads from $200 before calling the NMI task
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; lda #$02 ;perform spr-ram DMA access on $0200-$02ff
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; jsr SPR_DMA_W
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ldx VRAM_Buffer_AddrCtrl ;load control for pointer to buffer contents
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lda VRAM_AddrTable_Low,x ;set indirect at $00 to pointer
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sta $00
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