68030tk/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt

@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
DMA working for GVP 2015-02-03 20:34:33 +00:00			`@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36\|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE`
			`@W: MT462 :\|Net RST_c appears to be an unidentified clock source. Assuming default frequency.`