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DMA working for GVP

This commit is contained in:
MHeinrichs 2015-02-03 21:34:33 +01:00
parent 57c9d31821
commit 2286431c0a
23 changed files with 11504 additions and 608 deletions
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36
Logic/68030-68000-bus.vhd
View File

@ -143,6 +143,7 @@ signal CLK_000_NE: STD_LOGIC := '0';
signal CLK_000_NE_D0: STD_LOGIC := '0';
signal DTACK_D0: STD_LOGIC := '1';
signal RESET_DLY: STD_LOGIC_VECTOR ( 5 downto 0 ) := "000000";
signal RESET_OUT: STD_LOGIC := '0';
--signal NO_RESET: STD_LOGIC := '0';
begin
@ -247,19 +248,23 @@ begin
begin
if(RST = '0' ) then
RESET_DLY <= "000000";
RESET_OUT <= '0';
elsif(rising_edge(CLK_OSZI)) then
--reset delay: wait 128 E-Clocks!
if(CLK_000_NE = '1' and cpu_est = E1) then
RESET_DLY <= RESET_DLY +1;
end if;
end if;
--reset buffer
if(RESET_DLY="111111")then
RESET_OUT <= '1';
end if;
end process reset_delay_machine;
--the state machine
state_machine: process(RST, CLK_OSZI)
state_machine: process(RESET_OUT, CLK_OSZI)
begin
if(RST = '0' ) then
RESET <= '0';
if(RESET_OUT = '0' ) then
VPA_D <= '1';
DTACK_D0 <= '1';
SM_AMIGA <= IDLE_P;
@ -290,10 +295,7 @@ begin
CLK_030_H <= '0';
CYCLE_DMA <= "00";
elsif(rising_edge(CLK_OSZI)) then
--reset buffer
--if(RESET_DLY="111111")then
RESET <= '1';
--end if;
--now: 68000 state machine and signals
@ -309,8 +311,8 @@ begin
if(BGACK_000='0') then
BGACK_030_INT <= '0';
elsif ( BGACK_000='1'
AND CLK_000_PE='1'
--AND CLK_000_D0='1' and CLK_000_D1='0'
--AND CLK_000_PE='1'
AND CLK_000_D0='1' and CLK_000_D1='0'
) then -- BGACK_000 is high here!
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
end if;
@ -323,8 +325,8 @@ begin
BG_000 <= '1';
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
and CLK_000_D0='1'
--and CLK_000_D0='1' AND CLK_000_D1='0'
--and CLK_000_D0='1'
and CLK_000_D0='0' AND CLK_000_D1='1'
) then --bus granted no local access and no AS_030 running!
BG_000 <= '0';
end if;
@ -461,7 +463,7 @@ begin
if(BGACK_030_INT='0' and AS_000='0')then
-- an 68000-memory cycle is three positive edges long!
if(CLK_000_PE='1')then
if(CLK_000_P_SYNC(10)='1')then
CYCLE_DMA <= CYCLE_DMA+1;
end if;
else
@ -470,7 +472,11 @@ begin
--dma stuff
--as can only be done if we know the uds/lds!
if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0') and not(CYCLE_DMA = "11"))then
if( BGACK_030_INT='0'
and AS_000='0'
and (UDS_000='0' or LDS_000='0')
and (CYCLE_DMA = "10" or CYCLE_DMA ="01")
)then
RW_000_DMA <= RW_000;
@ -521,8 +527,8 @@ begin
end process state_machine;
--RESET <= 'Z' when RESET_OUT ='1' else '0';
RESET <= RESET_OUT;
-- bus drivers
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;

2
Logic/68030_TK.STY
View File

@ -3,4 +3,4 @@ tool=Synplify
[STRATEGY-LIST]
Normal=True, 1412327082
[TOUCHED-REPORT]
Design.impFile=1422902358
Design.impFile=1422960966

8
Logic/68030_TK.lci
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 02/02/2015;
TIME = 19:39:18;
DATE = 02/03/2015;
TIME = 11:56:06;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -29,11 +29,11 @@ Zero_hold_time = Yes;
Max_pterm_split = 16;
Max_pterm_collapse = 16;
Nodes_collapsing_mode = Area;
Max_fanin = 33;
Max_fanin = 32;
Set_reset_dont_care = Yes;
Balanced_partitioning = Yes;
Max_macrocell_percent = 100;
Dt_synthesis = No;
Dt_synthesis = Yes;
[Location Assignments]
layer = OFF;

8
Logic/68030_TK.lct
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
[Revision]
Parent = m4a5.lci;
DATE = 02/02/2015;
TIME = 19:39:18;
DATE = 02/03/2015;
TIME = 11:56:06;
Source_Format = Pure_VHDL;
Synthesis = Synplify;
@ -29,11 +29,11 @@ Zero_hold_time = Yes;
Max_pterm_split = 16;
Max_pterm_collapse = 16;
Nodes_collapsing_mode = Area;
Max_fanin = 33;
Max_fanin = 32;
Set_reset_dont_care = Yes;
Balanced_partitioning = Yes;
Max_macrocell_percent = 100;
Dt_synthesis = No;
Dt_synthesis = Yes;
[Location Assignments]
layer = OFF;

10879
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

1095
Logic/68030_tk - DMA-Working@50MHz.jed
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File diff suppressed because it is too large Load Diff

5
Logic/68030_tk.crf
View File

@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Tue Feb 03 09:23:46 2015
// Design '68030_tk' created Tue Feb 03 20:27:50 2015
// LEGEND: '>' Functional Block Port Separator
@ -10,4 +10,5 @@
// Hierarchical Name Short Name
state_machine_un17_bgack_030_int_i_1_i_n U0_achine_un17_bgack_030_int_i_1
// *** Shortened names not required for this design. ***

2
Logic/68030_tk.ipr
View File

@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>63:21<4XlL27-y
<LATTICE_ENCRYPTED_BLIF>0642=<4cdCj

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Tue Feb 03 09:23:39 2015
#-- Written on Tue Feb 03 20:27:43 2015
#device options

25
Logic/bus68030.srf
View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Tue Feb 03 09:23:39 2015
#Tue Feb 03 20:27:43 2015
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -27,13 +27,13 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":248:2:248:3|Pruning register RESET_DLY(5 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":259:2:259:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
@ -48,7 +48,7 @@ State machine has 8 reachable states with original encodings of:
111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Feb 03 09:23:39 2015
# Tue Feb 03 20:27:43 2015
###########################################################]
Map & Optimize Report
@ -67,22 +67,25 @@ original code -> new code
101 -> 00100000
110 -> 01000000
111 -> 10000000
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":215:4:215:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
---------------------------------------
Resource Usage Report
Simple gate primitives:
DFFRH 12 uses
DFFRH 17 uses
DFF 33 uses
DFFSH 28 uses
BI_DIR 11 uses
IBUF 32 uses
OBUF 16 uses
BUFTH 2 uses
AND2 215 uses
INV 181 uses
XOR2 4 uses
OR2 21 uses
AND2 230 uses
INV 180 uses
DLATRH 1 use
OR2 20 uses
XOR2 9 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@ -92,6 +95,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Feb 03 09:23:41 2015
# Tue Feb 03 20:27:45 2015
###########################################################]

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Tue Feb 03 09:23:39 2015
#-- Written on Tue Feb 03 20:27:43 2015
#project files

17
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -12,22 +12,25 @@ original code -> new code
101 -> 00100000
110 -> 01000000
111 -> 10000000
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":215:4:215:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
---------------------------------------
Resource Usage Report
Simple gate primitives:
DFFRH 12 uses
DFFRH 17 uses
DFF 33 uses
DFFSH 28 uses
BI_DIR 11 uses
IBUF 32 uses
OBUF 16 uses
BUFTH 2 uses
AND2 215 uses
INV 181 uses
XOR2 4 uses
OR2 21 uses
AND2 230 uses
INV 180 uses
DLATRH 1 use
OR2 20 uses
XOR2 9 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@ -37,6 +40,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Feb 03 09:23:41 2015
# Tue Feb 03 20:27:45 2015
###########################################################]

7
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,4 +1,5 @@
@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":471:18:471:43|No matching overload for "or"
@E: CD308 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":471:18:471:43|Unable to evaluate expression type
@E: CD676 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":471:18:471:43|Can't implement expression (no function signature?)
@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":483:21:483:36|No matching overload for "<"
@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":492:19:492:38|No matching overload for "not"
@E: CD308 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":483:21:483:36|Unable to evaluate expression type
@E: CD676 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":483:21:483:36|Can't implement expression (no function signature?)

2
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1422951820</data>
<data type="timestamp">1422991663</data>
</info>
</job_info>
</job_run_status>

4
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -6,11 +6,11 @@
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":248:2:248:3|Pruning register RESET_DLY(5 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":259:2:259:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.

2
Logic/synlog/report/BUS68030_fpga_mapper_notes.txt
View File

@ -1,3 +1,3 @@
@N: MF248 |Running in 64-bit mode.
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":215:4:215:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.

4
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from mapper to be displayed as part of the
</report_link>
</info>
<info name="Warnings">
<data>0</data>
<data>2</data>
<report_link name="more">
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
</report_link>
@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>96MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1422951821</data>
<data type="timestamp">1422991665</data>
</info>
</job_info>
</job_run_status>

2
Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt
View File

@ -0,0 +1,2 @@
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Tue Feb 03 09:23:39 2015
Written on Tue Feb 03 20:27:43 2015
-->

2
Logic/synwork/BUS68030_compiler.fdep
View File

@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422951812
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422991652
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_compiler.fdeporig
View File

@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422951812
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422991652
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_compiler.srs
View File

Binary file not shown.

4
Logic/synwork/BUS68030_compiler.tlg
View File

@ -8,13 +8,13 @@
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":248:2:248:3|Pruning register RESET_DLY(5 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":259:2:259:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA