mirror of
https://github.com/kr239/68030tk.git
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DMA working for GVP
This commit is contained in:
MHeinrichs
parent
57c9d31821
commit
2286431c0a
@ -143,6 +143,7 @@ signal CLK_000_NE: STD_LOGIC := '0';
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signal CLK_000_NE_D0: STD_LOGIC := '0';
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signal DTACK_D0: STD_LOGIC := '1';
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signal RESET_DLY: STD_LOGIC_VECTOR ( 5 downto 0 ) := "000000";
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signal RESET_OUT: STD_LOGIC := '0';
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--signal NO_RESET: STD_LOGIC := '0';
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begin
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@ -247,19 +248,23 @@ begin
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begin
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if(RST = '0' ) then
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RESET_DLY <= "000000";
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RESET_OUT <= '0';
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elsif(rising_edge(CLK_OSZI)) then
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--reset delay: wait 128 E-Clocks!
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if(CLK_000_NE = '1' and cpu_est = E1) then
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RESET_DLY <= RESET_DLY +1;
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end if;
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end if;
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--reset buffer
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if(RESET_DLY="111111")then
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RESET_OUT <= '1';
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end if;
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end process reset_delay_machine;
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--the state machine
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state_machine: process(RST, CLK_OSZI)
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state_machine: process(RESET_OUT, CLK_OSZI)
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begin
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if(RST = '0' ) then
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RESET <= '0';
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if(RESET_OUT = '0' ) then
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VPA_D <= '1';
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DTACK_D0 <= '1';
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SM_AMIGA <= IDLE_P;
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@ -290,10 +295,7 @@ begin
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CLK_030_H <= '0';
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CYCLE_DMA <= "00";
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elsif(rising_edge(CLK_OSZI)) then
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--reset buffer
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--if(RESET_DLY="111111")then
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RESET <= '1';
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--end if;
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--now: 68000 state machine and signals
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@ -309,8 +311,8 @@ begin
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if(BGACK_000='0') then
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BGACK_030_INT <= '0';
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elsif ( BGACK_000='1'
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AND CLK_000_PE='1'
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--AND CLK_000_D0='1' and CLK_000_D1='0'
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--AND CLK_000_PE='1'
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AND CLK_000_D0='1' and CLK_000_D1='0'
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) then -- BGACK_000 is high here!
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BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
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end if;
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@ -323,8 +325,8 @@ begin
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BG_000 <= '1';
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elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
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and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
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and CLK_000_D0='1'
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--and CLK_000_D0='1' AND CLK_000_D1='0'
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--and CLK_000_D0='1'
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and CLK_000_D0='0' AND CLK_000_D1='1'
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) then --bus granted no local access and no AS_030 running!
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BG_000 <= '0';
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end if;
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@ -461,7 +463,7 @@ begin
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if(BGACK_030_INT='0' and AS_000='0')then
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-- an 68000-memory cycle is three positive edges long!
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if(CLK_000_PE='1')then
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if(CLK_000_P_SYNC(10)='1')then
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CYCLE_DMA <= CYCLE_DMA+1;
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end if;
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else
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@ -470,7 +472,11 @@ begin
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--dma stuff
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--as can only be done if we know the uds/lds!
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if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0') and not(CYCLE_DMA = "11"))then
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if( BGACK_030_INT='0'
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and AS_000='0'
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and (UDS_000='0' or LDS_000='0')
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and (CYCLE_DMA = "10" or CYCLE_DMA ="01")
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)then
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RW_000_DMA <= RW_000;
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@ -521,8 +527,8 @@ begin
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end process state_machine;
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--RESET <= 'Z' when RESET_OUT ='1' else '0';
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RESET <= RESET_OUT;
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-- bus drivers
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AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
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@ -3,4 +3,4 @@ tool=Synplify
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[STRATEGY-LIST]
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Normal=True, 1412327082
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[TOUCHED-REPORT]
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Design.impFile=1422902358
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Design.impFile=1422960966
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
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[Revision]
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Parent = m4a5.lci;
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DATE = 02/02/2015;
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TIME = 19:39:18;
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DATE = 02/03/2015;
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TIME = 11:56:06;
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Source_Format = Pure_VHDL;
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Synthesis = Synplify;
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@ -29,11 +29,11 @@ Zero_hold_time = Yes;
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Max_pterm_split = 16;
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Max_pterm_collapse = 16;
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Nodes_collapsing_mode = Area;
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Max_fanin = 33;
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Max_fanin = 32;
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Set_reset_dont_care = Yes;
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Balanced_partitioning = Yes;
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Max_macrocell_percent = 100;
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Dt_synthesis = No;
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Dt_synthesis = Yes;
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[Location Assignments]
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layer = OFF;
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
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[Revision]
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Parent = m4a5.lci;
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DATE = 02/02/2015;
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TIME = 19:39:18;
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DATE = 02/03/2015;
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TIME = 11:56:06;
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Source_Format = Pure_VHDL;
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Synthesis = Synplify;
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@ -29,11 +29,11 @@ Zero_hold_time = Yes;
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Max_pterm_split = 16;
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Max_pterm_collapse = 16;
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Nodes_collapsing_mode = Area;
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Max_fanin = 33;
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Max_fanin = 32;
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Set_reset_dont_care = Yes;
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Balanced_partitioning = Yes;
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Max_macrocell_percent = 100;
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Dt_synthesis = No;
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Dt_synthesis = Yes;
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[Location Assignments]
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layer = OFF;
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10879
Logic/68030_TK.tcl
10879
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
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// Signal Name Cross Reference File
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// ispLEVER Classic 1.7.00.05.28.13
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// Design '68030_tk' created Tue Feb 03 09:23:46 2015
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// Design '68030_tk' created Tue Feb 03 20:27:50 2015
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// LEGEND: '>' Functional Block Port Separator
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@ -10,4 +10,5 @@
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// Hierarchical Name Short Name
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state_machine_un17_bgack_030_int_i_1_i_n U0_achine_un17_bgack_030_int_i_1
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// *** Shortened names not required for this design. ***
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@ -1 +1 @@
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<LATTICE_ENCRYPTED_BLIF>63:21<4XlL27-y
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<LATTICE_ENCRYPTED_BLIF>0642=<4cdC j
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@ -1,6 +1,6 @@
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#-- Lattice Semiconductor Corporation Ltd.
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#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
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#-- Written on Tue Feb 03 09:23:39 2015
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#-- Written on Tue Feb 03 20:27:43 2015
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#device options
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@ -6,7 +6,7 @@
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#Implementation: logic
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$ Start of Compile
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#Tue Feb 03 09:23:39 2015
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#Tue Feb 03 20:27:43 2015
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Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
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@N|Running in 64-bit mode
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@ -27,13 +27,13 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
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Post processing for work.bus68030.behavioral
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":248:2:248:3|Pruning register RESET_DLY(5 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
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@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
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@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":259:2:259:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
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Extracted state machine for register SM_AMIGA
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@ -48,7 +48,7 @@ State machine has 8 reachable states with original encodings of:
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111
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@END
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Feb 03 09:23:39 2015
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# Tue Feb 03 20:27:43 2015
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###########################################################]
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Map & Optimize Report
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@ -67,22 +67,25 @@ original code -> new code
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101 -> 00100000
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110 -> 01000000
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111 -> 10000000
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":215:4:215:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
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@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
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---------------------------------------
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Resource Usage Report
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Simple gate primitives:
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DFFRH 12 uses
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DFFRH 17 uses
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DFF 33 uses
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DFFSH 28 uses
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BI_DIR 11 uses
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IBUF 32 uses
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OBUF 16 uses
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BUFTH 2 uses
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AND2 215 uses
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INV 181 uses
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XOR2 4 uses
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OR2 21 uses
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AND2 230 uses
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INV 180 uses
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DLATRH 1 use
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OR2 20 uses
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XOR2 9 uses
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@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
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@ -92,6 +95,6 @@ Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Feb 03 09:23:41 2015
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# Tue Feb 03 20:27:45 2015
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###########################################################]
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@ -1,7 +1,7 @@
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#-- Synopsys, Inc.
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#-- Version G-2012.09LC-SP1
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#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
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#-- Written on Tue Feb 03 09:23:39 2015
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#-- Written on Tue Feb 03 20:27:43 2015
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#project files
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@ -12,22 +12,25 @@ original code -> new code
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101 -> 00100000
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110 -> 01000000
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111 -> 10000000
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":215:4:215:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
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@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
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@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
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---------------------------------------
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Resource Usage Report
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Simple gate primitives:
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DFFRH 12 uses
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DFFRH 17 uses
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DFF 33 uses
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DFFSH 28 uses
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BI_DIR 11 uses
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IBUF 32 uses
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OBUF 16 uses
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BUFTH 2 uses
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AND2 215 uses
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INV 181 uses
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XOR2 4 uses
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OR2 21 uses
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AND2 230 uses
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INV 180 uses
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DLATRH 1 use
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OR2 20 uses
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XOR2 9 uses
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@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
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@ -37,6 +40,6 @@ Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Feb 03 09:23:41 2015
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# Tue Feb 03 20:27:45 2015
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###########################################################]
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@ -1,4 +1,5 @@
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@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":471:18:471:43|No matching overload for "or"
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@E: CD308 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":471:18:471:43|Unable to evaluate expression type
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@E: CD676 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":471:18:471:43|Can't implement expression (no function signature?)
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@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":483:21:483:36|No matching overload for "<"
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@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":492:19:492:38|No matching overload for "not"
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@E: CD308 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":483:21:483:36|Unable to evaluate expression type
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@E: CD676 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":483:21:483:36|Can't implement expression (no function signature?)
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@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
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<data>-</data>
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</info>
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<info name="Date &Time">
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<data type="timestamp">1422951820</data>
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<data type="timestamp">1422991663</data>
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</info>
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</job_info>
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</job_run_status>
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@ -6,11 +6,11 @@
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":248:2:248:3|Pruning register RESET_DLY(5 downto 0)
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
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@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
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@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":259:2:259:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
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@ -1,3 +1,3 @@
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@N: MF248 |Running in 64-bit mode.
|
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@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":215:4:215:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":216:4:216:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
||||
@ -18,7 +18,7 @@ The file contains the job information from mapper to be displayed as part of the
|
||||
</report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>0</data>
|
||||
<data>2</data>
|
||||
<report_link name="more">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
|
||||
</report_link>
|
||||
@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
|
||||
<data>96MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1422951821</data>
|
||||
<data type="timestamp">1422991665</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
||||
@ -0,0 +1,2 @@
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
|
||||
@ -3,7 +3,7 @@
|
||||
Synopsys, Inc.
|
||||
Version G-2012.09LC-SP1
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Tue Feb 03 09:23:39 2015
|
||||
Written on Tue Feb 03 20:27:43 2015
|
||||
|
||||
|
||||
-->
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422951812
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422991652
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
||||
@ -10,7 +10,7 @@
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422951812
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1422991652
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
||||
Binary file not shown.
@ -8,13 +8,13 @@
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":248:2:248:3|Pruning register RESET_DLY(5 downto 0)
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":259:2:259:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user