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68030tk/Logic/68030_tk.rpt

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There is a bug somewhere!!!
2014-10-10 20:41:57 +00:00
|--------------------------------------------|
|- ispLEVER Fitter Report File -|
|- Version 1.7.00.05.28.13 -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|
Project_Summary
~~~~~~~~~~~~~~~
Project Name : 68030_tk
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
Project Fitted on : Fri Oct 10 22:40:09 2014
Device : M4A5-128/64
Package : 100TQFP
Speed : -10
Partnumber : M4A5-128/64-10VC
Source Format : Pure_VHDL
// Project '68030_tk' was Fitted Successfully! //
Compilation_Times
~~~~~~~~~~~~~~~~~
Reading/DRC 0 sec
Partition 0 sec
Place 0 sec
Route 0 sec
Jedec/Report generation 0 sec
--------
Fitter 00:00:00
Design_Summary
~~~~~~~~~~~~~~
Total Input Pins : 31
Total Output Pins : 17
Total Bidir I/O Pins : 13
Total Flip-Flops : 80
Total Product Terms : 181
Total Reserved Pins : 0
Total Reserved Blocks : 0
Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
Total
Available Used Available Utilization
Dedicated Pins
Input-Only Pins 2 2 0 --> 100%
Clock/Input Pins 4 4 0 --> 100%
I/O Pins 64 55 9 --> 85%
Logic Macrocells 128 98 30 --> 76%
Input Registers 64 0 64 --> 0%
Unusable Macrocells .. 0 ..
CSM Outputs/Total Block Inputs 264 227 37 --> 85%
Logical Product Terms 640 192 448 --> 30%
Product Term Clusters 128 50 78 --> 39%

Blocks_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
# of PT
I/O Inp Macrocells Macrocells logic clusters
Fanin Pins Reg Used Unusable available PTs available Pwr
---------------------------------------------------------------------------------
Maximum 33 8 8 -- -- 16 80 16 -
---------------------------------------------------------------------------------
Block A 23 8 0 11 0 5 26 9 Lo
Block B 28 8 0 12 0 4 18 10 Lo
Block C 26 7 0 12 0 4 29 7 Lo
Block D 31 8 0 14 0 2 28 10 Lo
Block E 32 4 0 10 0 6 13 14 Lo
Block F 28 5 0 15 0 1 32 6 Lo
Block G 28 7 0 13 0 3 24 11 Lo
Block H 31 8 0 11 0 5 22 11 Lo
---------------------------------------------------------------------------------
<Note> Four rightmost columns above reflect last status of the placement process.
<Note> Pwr (Power) : Hi = High
Lo = Low.

Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment : Yes
Group Assignment : No
Pin Reservation : No (1)
Block Reservation : No
@Ignore_Project_Constraints :
Pin Assignments : No
Keep Block Assignment --
Keep Segment Assignment --
Group Assignments : No
Macrocell Assignment : No
Keep Block Assignment --
Keep Segment Assignment --
@Backannotate_Project_Constraints
Pin Assignments : No
Pin And Block Assignments : No
Pin, Macrocell and Block : No
@Timing_Constraints : No
@Global_Project_Optimization :
Balanced Partitioning : Yes
Spread Placement : Yes
Note :
Pack Design :
Balanced Partitioning = No
Spread Placement = No
Spread Design :
Balanced Partitioning = Yes
Spread Placement = Yes
@Logic_Synthesis :
Logic Reduction : Yes
Node Collapsing : Yes
D/T Synthesis : No
Clock Optimization : No
Input Register Optimization : Yes
XOR Synthesis : Yes
Max. P-Term for Collapsing : 16
Max. P-Term for Splitting : 16
Max. Equation Fanin : 32
Keep Xor : Yes
@Utilization_options
Max. % of macrocells used : 100
Max. % of block inputs used : 100
Max. % of segment lines used : ---
Max. % of macrocells used : ---
@Import_Source_Constraint_Option No
@Zero_Hold_Time Yes
@Pull_up Yes
@User_Signature #H0
@Output_Slew_Rate Default = Slow(2)
@Power Default = High(2)
Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output,
Bidir and Burried Signal Lists.

Pinout_Listing
~~~~~~~~~~~~~~
| Pin |Blk |Assigned|
Pin No| Type |Pad |Pin | Signal name
---------------------------------------------------------------
1 | GND | | |
2 | JTAG | | |
3 | I_O | B7 | * |RESET
4 | I_O | B6 | * |A_31_
5 | I_O | B5 | * |A_30_
6 | I_O | B4 | * |A_29_
7 | I_O | B3 | * |IPL_030_1_
8 | I_O | B2 | * |IPL_030_0_
9 | I_O | B1 | * |IPL_030_2_
10 | I_O | B0 | * |CLK_EXP
11 | CkIn | | * |CLK_000
12 | Vcc | | |
13 | GND | | |
14 | CkIn | | * |nEXP_SPACE
15 | I_O | C0 | * |A_28_
16 | I_O | C1 | * |A_27_
17 | I_O | C2 | * |A_26_
18 | I_O | C3 | * |A_25_
19 | I_O | C4 | * |A_24_
20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW
21 | I_O | C6 | * |BG_030
22 | I_O | C7 | |
23 | JTAG | | |
24 | JTAG | | |
25 | GND | | |
26 | GND | | |
27 | GND | | |
28 | I_O | D7 | * |BGACK_000
29 | I_O | D6 | * |BG_000
30 | I_O | D5 | * |DTACK
31 | I_O | D4 | * |LDS_000
32 | I_O | D3 | * |UDS_000
33 | I_O | D2 | * |AMIGA_ADDR_ENABLE
34 | I_O | D1 | * |AMIGA_BUS_ENABLE_HIGH
35 | I_O | D0 | * |VMA
36 | Inp | | * |VPA
37 | Vcc | | |
38 | GND | | |
39 | GND | | |
40 | Vcc | | |
41 | I_O | E0 | * |BERR
42 | I_O | E1 | * |AS_000
43 | I_O | E2 | |
44 | I_O | E3 | |
45 | I_O | E4 | |
46 | I_O | E5 | |
47 | I_O | E6 | * |CIIN
48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR
49 | GND | | |
50 | GND | | |
51 | GND | | |
52 | JTAG | | |
53 | I_O | F7 | |
54 | I_O | F6 | |
55 | I_O | F5 | |
56 | I_O | F4 | * |IPL_1_
57 | I_O | F3 | * |FC_0_
58 | I_O | F2 | * |FC_1_
59 | I_O | F1 | * |A_17_
60 | I_O | F0 | * |A1
61 | CkIn | | * |CLK_OSZI
62 | Vcc | | |
63 | GND | | |
64 | CkIn | | * |CLK_030
65 | I_O | G0 | * |CLK_DIV_OUT
66 | I_O | G1 | * |E
67 | I_O | G2 | * |IPL_0_
68 | I_O | G3 | * |IPL_2_
69 | I_O | G4 | * |A0
70 | I_O | G5 | * |SIZE_0_
71 | I_O | G6 | * |RW
72 | I_O | G7 | |
73 | JTAG | | |
74 | JTAG | | |
75 | GND | | |
76 | GND | | |
77 | GND | | |
78 | I_O | H7 | * |FPU_CS
79 | I_O | H6 | * |SIZE_1_
80 | I_O | H5 | * |RW_000
81 | I_O | H4 | * |DSACK1
82 | I_O | H3 | * |AS_030
83 | I_O | H2 | * |BGACK_030
84 | I_O | H1 | * |A_22_
85 | I_O | H0 | * |A_23_
86 | Inp | | * |RST
87 | Vcc | | |
88 | GND | | |
89 | GND | | |
90 | Vcc | | |
91 | I_O | A0 | * |FPU_SENSE
92 | I_O | A1 | * |AVEC
93 | I_O | A2 | * |A_20_
94 | I_O | A3 | * |A_21_
95 | I_O | A4 | * |A_18_
96 | I_O | A5 | * |A_16_
97 | I_O | A6 | * |A_19_
98 | I_O | A7 | * |DS_030
99 | GND | | |
100 | GND | | |
---------------------------------------------------------------------------
<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type :
CkIn : Dedicated input or clock pin
CLK : Dedicated clock pin
INP : Dedicated input pin
JTAG : JTAG Control and test pin
NC : No connected

Input_Signal_List
~~~~~~~~~~~~~~~~~
P R
Pin r e O Input
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
60 F . I/O A------- Low Slow A1
96 A . I/O ----E--H Low Slow A_16_
59 F . I/O ----E--H Low Slow A_17_
95 A . I/O ----E--H Low Slow A_18_
97 A . I/O ----E--H Low Slow A_19_
93 A . I/O ----E--- Low Slow A_20_
94 A . I/O ----E--- Low Slow A_21_
84 H . I/O ----E--- Low Slow A_22_
85 H . I/O ----E--- Low Slow A_23_
19 C . I/O ----E--- Low Slow A_24_
18 C . I/O ----E--- Low Slow A_25_
17 C . I/O ----E--- Low Slow A_26_
16 C . I/O ----E--- Low Slow A_27_
15 C . I/O ----E--- Low Slow A_28_
6 B . I/O ----E--- Low Slow A_29_
5 B . I/O ----E--- Low Slow A_30_
4 B . I/O ----E--- Low Slow A_31_
28 D . I/O ----E--H Low Slow BGACK_000
21 C . I/O ---D---- Low Slow BG_030
57 F . I/O ----E--H Low Slow FC_0_
58 F . I/O ----E--H Low Slow FC_1_
91 A . I/O ----E--H Low Slow FPU_SENSE
67 G . I/O -B------ Low Slow IPL_0_
56 F . I/O -B------ Low Slow IPL_1_
68 G . I/O -B------ Low Slow IPL_2_
11 . . Ck/I ---D---- - Slow CLK_000
14 . . Ck/I -B------ - Slow nEXP_SPACE
36 . . Ded -----F-- - Slow VPA
61 . . Ck/I ABCDEFGH - Slow CLK_OSZI
64 . . Ck/I A-----GH - Slow CLK_030
86 . . Ded ABCD-FGH - Slow RST
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Output_Signal_List
~~~~~~~~~~~~~~~~~~
P R
Pin r e O Output
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
33 D 3 DFF * -------- Low Fast AMIGA_ADDR_ENABLE
48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR
34 D 1 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH
20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW
92 A 1 COM -------- Low Fast AVEC
83 H 2 DFF * -------- Low Fast BGACK_030
29 D 2 DFF * -------- Low Fast BG_000
47 E 1 COM -------- Low Fast CIIN
65 G 1 COM -------- Low Fast CLK_DIV_OUT
10 B 1 COM -------- Low Fast CLK_EXP
66 G 3 DFF -------- Low Slow E
78 H 1 COM -------- Low Fast FPU_CS
8 B 2 DFF * -------- Low Fast IPL_030_0_
7 B 2 DFF * -------- Low Fast IPL_030_1_
9 B 2 DFF * -------- Low Fast IPL_030_2_
3 B 2 DFF * -------- Low Fast RESET
35 D 3 DFF * -------- Low Slow VMA
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Bidir_Signal_List
~~~~~~~~~~~~~~~~~
P R
Pin r e O Bidir
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
69 G 1 DFF * A------- Low Fast A0
42 E 1 COM A---E-G- Low Fast AS_000
82 H 1 COM ----E--H Low Fast AS_030
41 E 1 COM --C--F-H Low Fast BERR
81 H 4 DFF * ---D---- Low Fast DSACK1
98 A 7 DFF * ---D---H Low Fast DS_030
30 D 1 COM ---D---- Low Fast DTACK
31 D 1 COM A-----G- Low Fast LDS_000
71 G 4 DFF * --C----H Low Fast RW
80 H 3 DFF * A---E-G- Low Fast RW_000
70 G 1 COM A------- Low Fast SIZE_0_
79 H 1 COM A------- Low Fast SIZE_1_
32 D 1 COM A-----G- Low Fast UDS_000
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Buried_Signal_List
~~~~~~~~~~~~~~~~~~
P R
Pin r e O Node
#Mc Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
E9 E 3 COM ----E--- Low Slow CIIN_0
E2 E 1 DFF ------G- Low Slow CLK_000_N_SYNC_0_
H2 H 1 DFF A------- Low Slow CLK_000_N_SYNC_10_
A10 A 1 DFF ----E--- Low Slow CLK_000_N_SYNC_11_
G10 G 1 DFF -B------ Low Slow CLK_000_N_SYNC_1_
B2 B 1 DFF ------G- Low Slow CLK_000_N_SYNC_2_
G6 G 1 DFF ---D---- Low Slow CLK_000_N_SYNC_3_
D3 D 1 DFF -B------ Low Slow CLK_000_N_SYNC_4_
B13 B 1 DFF A------- Low Slow CLK_000_N_SYNC_5_
A2 A 1 DFF -----F-- Low Slow CLK_000_N_SYNC_6_
F14 F 1 DFF A------- Low Slow CLK_000_N_SYNC_7_
A1 A 1 DFF ----E--H Low Slow CLK_000_N_SYNC_8_
E13 E 1 DFF -------H Low Slow CLK_000_N_SYNC_9_
E6 E 1 DFF -B------ Low Slow CLK_000_P_SYNC_0_
B10 B 1 DFF A------- Low Slow CLK_000_P_SYNC_1_
A6 A 1 DFF ------G- Low Slow CLK_000_P_SYNC_2_
G14 G 1 DFF -B------ Low Slow CLK_000_P_SYNC_3_
B6 B 1 DFF --C----- Low Slow CLK_000_P_SYNC_4_
C14 C 1 DFF --C----- Low Slow CLK_000_P_SYNC_5_
C10 C 1 DFF --C----- Low Slow CLK_000_P_SYNC_6_
C6 C 1 DFF -----F-- Low Slow CLK_000_P_SYNC_7_
F3 F 1 DFF ------G- Low Slow CLK_000_P_SYNC_8_
G3 G 1 DFF --C----- Low Slow CLK_000_P_SYNC_9_
F8 F 1 DFF -B----GH Low Slow CLK_OUT_PRE_Dreg
F13 F 1 DFF * -B---FG- Low Slow RESET_DLY_0_
F9 F 1 DFF * -B---FG- Low Slow RESET_DLY_1_
F5 F 1 DFF * -B---FG- Low Slow RESET_DLY_2_
F1 F 1 DFF * -B---FG- Low Slow RESET_DLY_3_
F12 F 1 DFF * -B---FG- Low Slow RESET_DLY_4_
G13 G 1 DFF * -B----G- Low Slow RESET_DLY_5_
B9 B 1 DFF * -B------ Low Slow RESET_DLY_6_
B14 B 1 DFF * -B------ Low Slow RESET_DLY_7_
D5 D 3 DFF * ---D---- Low - RN_AMIGA_ADDR_ENABLE --> AMIGA_ADDR_ENABLE
H4 H 2 DFF * A-CDE-GH Low - RN_BGACK_030 --> BGACK_030
D1 D 2 DFF * ---D---- Low - RN_BG_000 --> BG_000
H12 H 4 DFF * -------H Low - RN_DSACK1 --> DSACK1
A0 A 7 DFF * A------- Low - RN_DS_030 --> DS_030
G4 G 3 DFF -B-D-FG- Low - RN_E --> E
B8 B 2 DFF * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_
B12 B 2 DFF * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_
B4 B 2 DFF * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_
B0 B 2 DFF * -B------ Low - RN_RESET --> RESET
G0 G 4 DFF * ------G- Low - RN_RW --> RW
H0 H 3 DFF * -------H Low - RN_RW_000 --> RW_000
D4 D 3 DFF * ---D-F-- Low - RN_VMA --> VMA
G2 G 1 DFF * ------GH Low Slow SIZE_DMA_0_
G9 G 2 DFF * ------GH Low Slow SIZE_DMA_1_
F4 F 2 DFF * --C--F-H Low Slow SM_AMIGA_0_
C8 C 2 DFF * --C--F-H Low Slow SM_AMIGA_1_
F6 F 3 DFF * --C--F-- Low Slow SM_AMIGA_2_
F2 F 6 DFF * --C--F-- Low Slow SM_AMIGA_3_
C5 C 2 DFF * --C--F-- Low Slow SM_AMIGA_4_
C2 C 2 DFF * --C----- Low Slow SM_AMIGA_5_
C12 C 2 DFF * A-C----H Low Slow SM_AMIGA_6_
F0 F 4 DFF * --CD---H Low Slow SM_AMIGA_7_
D6 D 2 DFF -B-D-FG- Low Slow cpu_est_0_
D13 D 5 DFF -B-D-FG- Low Slow cpu_est_1_
D2 D 4 DFF -B-D-FG- Low Slow cpu_est_2_
A13 A 2 DFF * ---D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH
A9 A 2 DFF * --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW
G5 G 4 DFF * A--D--GH Low Slow inst_AS_000_DMA
C9 C 2 DFF * --C-E--- Low Slow inst_AS_000_INT
H13 H 6 DFF * --CD---H Low Slow inst_AS_030_000_SYNC
H9 H 1 DFF * --CDE--H Low Slow inst_AS_030_D0
H6 H 1 DFF * ---D---- Low Slow inst_BGACK_030_INT_D
D14 D 1 DFF --CDE--- Low Slow inst_CLK_000_D0
E5 E 1 DFF --CDE--- Low Slow inst_CLK_000_D1
E8 E 1 DFF -BCD-F-- Low Slow inst_CLK_000_NE
D10 D 1 DFF -B-D-FG- Low Slow inst_CLK_000_NE_D0
C4 C 1 DFF --CD-F-H Low Slow inst_CLK_000_PE
A5 A 4 DFF * A------- Low Slow inst_CLK_030_H
F7 F 1 DFF -----F-- Low Slow inst_CLK_OUT_PRE
F11 F 1 DFF -----F-- Low Slow inst_CLK_OUT_PRE_50
C1 C 3 DFF * --CD---- Low Slow inst_DS_000_ENABLE
H10 H 1 DFF * A------- Low Slow inst_DS_030_D0
D7 D 1 DFF * -----F-- Low Slow inst_DTACK_D0
A8 A 3 DFF * A--D---- Low Slow inst_LDS_000_INT
A12 A 3 DFF * A--D---- Low Slow inst_UDS_000_INT
F10 F 1 DFF * ---D-F-- Low Slow inst_VPA_D
B5 B 1 DFF * A-CDE-GH Low Slow inst_nEXP_SPACE_D0
C13 C 11 COM -----F-- Low Slow sm_amiga_ns_0_3_0__n
----------------------------------------------------------------------
<Note> Power : Hi = High
MH = Medium High
ML = Medium Low
Lo = Low

Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source : Fanout List
-----------------------------------------------------------------------------
A_27_{ D}: CIIN{ E} CIIN_0{ E}
A_26_{ D}: CIIN{ E} CIIN_0{ E}
SIZE_1_{ I}:inst_LDS_000_INT{ A}
A_25_{ D}: CIIN{ E} CIIN_0{ E}
A_24_{ D}: CIIN{ E} CIIN_0{ E}
A_31_{ C}: CIIN{ E} CIIN_0{ E}
A_23_{ I}: CIIN{ E} CIIN_0{ E}
A_22_{ I}: CIIN{ E} CIIN_0{ E}
A_21_{ B}: CIIN{ E} CIIN_0{ E}
A_20_{ B}: CIIN{ E} CIIN_0{ E}
IPL_2_{ H}: IPL_030_2_{ B}
A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H}
: inst_AS_030_D0{ H} CIIN_0{ E}
A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
AS_000{ F}:AMIGA_BUS_DATA_DIR{ E} DS_030{ A} A0{ G}
: RW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}
:inst_AS_000_DMA{ G} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}
: inst_CLK_030_H{ A}
IPL_1_{ G}: IPL_030_1_{ B}
UDS_000{ E}: DS_030{ A} A0{ G} RW{ G}
:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}inst_AS_000_DMA{ G}
: SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
IPL_0_{ H}: IPL_030_0_{ B}
LDS_000{ E}: DS_030{ A} A0{ G} RW{ G}
:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}inst_AS_000_DMA{ G}
: SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}
nEXP_SPACE{. }:inst_nEXP_SPACE_D0{ B}
BERR{ F}: RW_000{ H} DSACK1{ H}inst_AS_000_INT{ C}
:inst_AS_030_000_SYNC{ H}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_7_{ F}
: SM_AMIGA_6_{ C} SM_AMIGA_4_{ C} SM_AMIGA_0_{ F}
:inst_DS_000_ENABLE{ C} SM_AMIGA_1_{ C} SM_AMIGA_5_{ C}
: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
BG_030{ D}: BG_000{ D}
BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H}
:inst_AS_030_000_SYNC{ H}
CLK_030{. }: DS_030{ A} DSACK1{ H} RW{ G}
:inst_AS_000_DMA{ G} inst_CLK_030_H{ A}
CLK_000{. }:inst_CLK_000_D0{ D}
FPU_SENSE{ B}: BERR{ E} FPU_CS{ H}
DTACK{ E}: inst_DTACK_D0{ D}
VPA{. }: inst_VPA_D{ F}
RST{. }: IPL_030_2_{ B} IPL_030_1_{ B} RW_000{ H}
: IPL_030_0_{ B} DS_030{ A} A0{ G}
: BG_000{ D} BGACK_030{ H} DSACK1{ H}
: VMA{ D} RESET{ B} RW{ G}
:AMIGA_ADDR_ENABLE{ D}inst_AS_000_INT{ C}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}
:inst_AMIGA_BUS_ENABLE_DMA_LOW{ A} inst_AS_030_D0{ H}inst_nEXP_SPACE_D0{ B}
: inst_DS_030_D0{ H}inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ H}
:inst_AS_000_DMA{ G} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}
: inst_VPA_D{ F}inst_UDS_000_INT{ A}inst_LDS_000_INT{ A}
: inst_DTACK_D0{ D} RESET_DLY_7_{ B} SM_AMIGA_7_{ F}
: SM_AMIGA_6_{ C} SM_AMIGA_4_{ C} SM_AMIGA_0_{ F}
: inst_CLK_030_H{ A} RESET_DLY_0_{ F} RESET_DLY_1_{ F}
: RESET_DLY_2_{ F} RESET_DLY_3_{ F} RESET_DLY_4_{ F}
: RESET_DLY_5_{ G} RESET_DLY_6_{ B}inst_DS_000_ENABLE{ C}
: SM_AMIGA_1_{ C} SM_AMIGA_5_{ C} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
SIZE_0_{ H}:inst_LDS_000_INT{ A}
A_30_{ C}: CIIN{ E} CIIN_0{ E}
A_29_{ C}: CIIN{ E} CIIN_0{ E}
A_28_{ D}: CIIN{ E} CIIN_0{ E}
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
RN_IPL_030_1_{ C}: IPL_030_1_{ B}
RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} DS_030{ A} RW{ G}
RN_RW_000{ I}: RW_000{ H}
RN_IPL_030_0_{ C}: IPL_030_0_{ B}
DS_030{ B}: UDS_000{ D} LDS_000{ D} inst_DS_030_D0{ H}
RN_DS_030{ B}: DS_030{ A}
A0{ H}:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A}
RN_BG_000{ E}: BG_000{ D}
RN_BGACK_030{ I}: SIZE_1_{ H} AS_030{ H} AS_000{ E}
: UDS_000{ D} LDS_000{ D} DTACK{ D}
:AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D}
: SIZE_0_{ G} RW_000{ H} DS_030{ A}
: A0{ G} BGACK_030{ H} RW{ G}
:AMIGA_ADDR_ENABLE{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}
:inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ G} SIZE_DMA_0_{ G}
: SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
DSACK1{ I}: DTACK{ D}
RN_DSACK1{ I}: DSACK1{ H}
RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D}
: RESET_DLY_7_{ B} SM_AMIGA_7_{ F} cpu_est_2_{ D}
: RESET_DLY_0_{ F} RESET_DLY_1_{ F} RESET_DLY_2_{ F}
: RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G}
: RESET_DLY_6_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
RN_VMA{ E}: VMA{ D} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
RN_RESET{ C}: RESET{ B}
RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ C}
RN_RW{ H}: RW{ G}
RN_AMIGA_ADDR_ENABLE{ E}:AMIGA_ADDR_ENABLE{ D}
cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D}
: cpu_est_1_{ D} RESET_DLY_7_{ B} SM_AMIGA_7_{ F}
: cpu_est_2_{ D} RESET_DLY_0_{ F} RESET_DLY_1_{ F}
: RESET_DLY_2_{ F} RESET_DLY_3_{ F} RESET_DLY_4_{ F}
: RESET_DLY_5_{ G} RESET_DLY_6_{ B} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D}
: RESET_DLY_7_{ B} SM_AMIGA_7_{ F} cpu_est_2_{ D}
: RESET_DLY_0_{ F} RESET_DLY_1_{ F} RESET_DLY_2_{ F}
: RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G}
: RESET_DLY_6_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C}
inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}:AMIGA_BUS_ENABLE_HIGH{ D}
inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}:AMIGA_BUS_ENABLE_LOW{ C}
inst_AS_030_D0{ I}: CIIN{ E} RW_000{ H} BG_000{ D}
: DSACK1{ H}inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ H}
:inst_DS_000_ENABLE{ C} CIIN_0{ E}
inst_nEXP_SPACE_D0{ C}: SIZE_1_{ H} AS_030{ H} DTACK{ D}
:AMIGA_BUS_DATA_DIR{ E} SIZE_0_{ G} DS_030{ A}
: A0{ G} BG_000{ D} DSACK1{ H}
:AMIGA_ADDR_ENABLE{ D}inst_AS_030_000_SYNC{ H}sm_amiga_ns_0_3_0__n{ C}
: SM_AMIGA_6_{ C} CIIN_0{ E}
inst_DS_030_D0{ I}:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A}
inst_AS_030_000_SYNC{ I}:AMIGA_ADDR_ENABLE{ D}inst_AS_030_000_SYNC{ H}sm_amiga_ns_0_3_0__n{ C}
: SM_AMIGA_6_{ C}
inst_BGACK_030_INT_D{ I}:AMIGA_ADDR_ENABLE{ D}
inst_AS_000_DMA{ H}: SIZE_1_{ H} AS_030{ H} DTACK{ D}
: SIZE_0_{ G} DS_030{ A} A0{ G}
:inst_AS_000_DMA{ G} inst_CLK_030_H{ A}
SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G}
SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G}
inst_VPA_D{ G}: VMA{ D} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
inst_UDS_000_INT{ B}: UDS_000{ D}inst_UDS_000_INT{ A}
inst_LDS_000_INT{ B}: LDS_000{ D}inst_LDS_000_INT{ A}
inst_DTACK_D0{ E}: SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
RESET_DLY_7_{ C}: RESET{ B} RESET_DLY_7_{ B}
inst_CLK_OUT_PRE_50{ G}:inst_CLK_OUT_PRE_50{ F}inst_CLK_OUT_PRE{ F}
inst_CLK_000_D1{ F}:AMIGA_ADDR_ENABLE{ D}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C}
:CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E}
inst_CLK_000_D0{ E}: BG_000{ D}AMIGA_ADDR_ENABLE{ D}inst_CLK_000_D1{ E}
:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C}CLK_000_P_SYNC_0_{ E}
:CLK_000_N_SYNC_0_{ E}
sm_amiga_ns_0_3_0__n{ D}: SM_AMIGA_7_{ F}
SM_AMIGA_7_{ G}: RW_000{ H}AMIGA_ADDR_ENABLE{ D}inst_AS_030_000_SYNC{ H}
: SM_AMIGA_6_{ C}
inst_CLK_OUT_PRE{ G}:CLK_OUT_PRE_Dreg{ F}
inst_CLK_000_PE{ D}: RW_000{ H} BGACK_030{ H} VMA{ D}
:inst_AS_000_INT{ C}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C}
: SM_AMIGA_4_{ C} SM_AMIGA_0_{ F}inst_DS_000_ENABLE{ C}
: SM_AMIGA_1_{ C} SM_AMIGA_5_{ C} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
CLK_000_P_SYNC_9_{ H}:inst_CLK_000_PE{ C}
inst_CLK_000_NE{ F}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B}
: VMA{ D}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_7_{ F}
:inst_CLK_000_NE_D0{ D} SM_AMIGA_4_{ C} SM_AMIGA_0_{ F}
: SM_AMIGA_1_{ C} SM_AMIGA_5_{ C} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
CLK_000_N_SYNC_11_{ B}:inst_CLK_000_NE{ E}
cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D}
: RESET_DLY_7_{ B} SM_AMIGA_7_{ F} cpu_est_2_{ D}
: RESET_DLY_0_{ F} RESET_DLY_1_{ F} RESET_DLY_2_{ F}
: RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G}
: RESET_DLY_6_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F}
inst_CLK_000_NE_D0{ E}: E{ G} cpu_est_0_{ D} cpu_est_1_{ D}
: RESET_DLY_7_{ B} cpu_est_2_{ D} RESET_DLY_0_{ F}
: RESET_DLY_1_{ F} RESET_DLY_2_{ F} RESET_DLY_3_{ F}
: RESET_DLY_4_{ F} RESET_DLY_5_{ G} RESET_DLY_6_{ B}
SM_AMIGA_6_{ D}: RW_000{ H}inst_AS_000_INT{ C}inst_UDS_000_INT{ A}
:inst_LDS_000_INT{ A}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C}
:inst_DS_000_ENABLE{ C} SM_AMIGA_5_{ C}
SM_AMIGA_4_{ D}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_4_{ C}inst_DS_000_ENABLE{ C}
: SM_AMIGA_3_{ F}
SM_AMIGA_0_{ G}: RW_000{ H}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_0_{ F}
inst_CLK_030_H{ B}: DS_030{ A} inst_CLK_030_H{ A}
CLK_000_P_SYNC_0_{ F}:CLK_000_P_SYNC_1_{ B}
CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ A}
CLK_000_P_SYNC_2_{ B}:CLK_000_P_SYNC_3_{ G}
CLK_000_P_SYNC_3_{ H}:CLK_000_P_SYNC_4_{ B}
CLK_000_P_SYNC_4_{ C}:CLK_000_P_SYNC_5_{ C}
CLK_000_P_SYNC_5_{ D}:CLK_000_P_SYNC_6_{ C}
CLK_000_P_SYNC_6_{ D}:CLK_000_P_SYNC_7_{ C}
CLK_000_P_SYNC_7_{ D}:CLK_000_P_SYNC_8_{ F}
CLK_000_P_SYNC_8_{ G}:CLK_000_P_SYNC_9_{ G}
CLK_000_N_SYNC_0_{ F}:CLK_000_N_SYNC_1_{ G}
CLK_000_N_SYNC_1_{ H}:CLK_000_N_SYNC_2_{ B}
CLK_000_N_SYNC_2_{ C}:CLK_000_N_SYNC_3_{ G}
CLK_000_N_SYNC_3_{ H}:CLK_000_N_SYNC_4_{ D}
CLK_000_N_SYNC_4_{ E}:CLK_000_N_SYNC_5_{ B}
CLK_000_N_SYNC_5_{ C}:CLK_000_N_SYNC_6_{ A}
CLK_000_N_SYNC_6_{ B}:CLK_000_N_SYNC_7_{ F}
CLK_000_N_SYNC_7_{ G}:CLK_000_N_SYNC_8_{ A}
CLK_000_N_SYNC_8_{ B}: DSACK1{ H}CLK_000_N_SYNC_9_{ E}
CLK_000_N_SYNC_9_{ F}: DSACK1{ H}CLK_000_N_SYNC_10_{ H}
CLK_000_N_SYNC_10_{ I}:CLK_000_N_SYNC_11_{ A}
RESET_DLY_0_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_0_{ F}
: RESET_DLY_1_{ F} RESET_DLY_2_{ F} RESET_DLY_3_{ F}
: RESET_DLY_4_{ F} RESET_DLY_5_{ G} RESET_DLY_6_{ B}
RESET_DLY_1_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_1_{ F}
: RESET_DLY_2_{ F} RESET_DLY_3_{ F} RESET_DLY_4_{ F}
: RESET_DLY_5_{ G} RESET_DLY_6_{ B}
RESET_DLY_2_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_2_{ F}
: RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G}
: RESET_DLY_6_{ B}
RESET_DLY_3_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_3_{ F}
: RESET_DLY_4_{ F} RESET_DLY_5_{ G} RESET_DLY_6_{ B}
RESET_DLY_4_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_4_{ F}
: RESET_DLY_5_{ G} RESET_DLY_6_{ B}
RESET_DLY_5_{ H}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_5_{ G}
: RESET_DLY_6_{ B}
RESET_DLY_6_{ C}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_6_{ B}
inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C}
SM_AMIGA_1_{ D}: DSACK1{ H}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_0_{ F}
: SM_AMIGA_1_{ C}
SM_AMIGA_5_{ D}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_4_{ C} SM_AMIGA_5_{ C}
SM_AMIGA_3_{ G}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F}
: SM_AMIGA_2_{ F}
SM_AMIGA_2_{ G}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_1_{ C} SM_AMIGA_2_{ F}
CLK_OUT_PRE_Dreg{ G}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H}
CIIN_0{ F}: CIIN{ E}
-----------------------------------------------------------------------------
<Note> {.} : Indicates block location of signal

Set_Reset_Summary
~~~~~~~~~~~~~~~~~
Block A
block level set pt : !RST
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | DS_030
| | | | | AVEC
| * | S | BS | BR | inst_LDS_000_INT
| * | S | BS | BR | inst_UDS_000_INT
| * | S | BR | BR | CLK_000_N_SYNC_8_
| * | S | BS | BR | RN_DS_030
| * | S | BR | BS | inst_CLK_030_H
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW
| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH
| * | S | BR | BR | CLK_000_N_SYNC_6_
| * | S | BR | BR | CLK_000_P_SYNC_2_
| * | S | BR | BR | CLK_000_N_SYNC_11_
| | | | | A_19_
| | | | | A_16_
| | | | | A_18_
| | | | | FPU_SENSE
| | | | | A_21_
| | | | | A_20_
Block B
block level set pt :
block level reset pt : !RST
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BR | BS | IPL_030_2_
| * | S | BR | BS | IPL_030_0_
| * | S | BR | BS | IPL_030_1_
| * | S | BS | BR | RESET
| | | | | CLK_EXP
| * | S | BR | BS | inst_nEXP_SPACE_D0
| * | S | BS | BR | RN_RESET
| * | S | BR | BS | RN_IPL_030_0_
| * | S | BR | BS | RN_IPL_030_1_
| * | S | BR | BS | RN_IPL_030_2_
| * | S | BS | BR | RESET_DLY_6_
| * | S | BS | BS | CLK_000_N_SYNC_5_
| * | S | BS | BS | CLK_000_N_SYNC_2_
| * | S | BS | BS | CLK_000_P_SYNC_4_
| * | S | BS | BS | CLK_000_P_SYNC_1_
| * | S | BS | BR | RESET_DLY_7_
| | | | | A_29_
| | | | | A_30_
| | | | | A_31_
Block C
block level set pt :
block level reset pt : !RST
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | AMIGA_BUS_ENABLE_LOW
| * | S | BS | BS | inst_CLK_000_PE
| * | S | BS | BR | SM_AMIGA_1_
| * | S | BS | BR | SM_AMIGA_6_
| * | S | BS | BR | inst_DS_000_ENABLE
| * | S | BS | BR | SM_AMIGA_4_
| * | S | BR | BS | inst_AS_000_INT
| | | | | sm_amiga_ns_0_3_0__n
| * | S | BS | BR | SM_AMIGA_5_
| * | S | BS | BS | CLK_000_P_SYNC_7_
| * | S | BS | BS | CLK_000_P_SYNC_6_
| * | S | BS | BS | CLK_000_P_SYNC_5_
| | | | | BG_030
| | | | | A_24_
| | | | | A_25_
| | | | | A_26_
| | | | | A_27_
| | | | | A_28_
Block D
block level set pt : !RST
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | UDS_000
| | | | | LDS_000
| | | | | DTACK
| * | S | BS | BR | VMA
| * | S | BS | BR | AMIGA_ADDR_ENABLE
| * | S | BS | BR | BG_000
| | | | | AMIGA_BUS_ENABLE_HIGH
| * | S | BR | BR | cpu_est_1_
| * | S | BR | BR | cpu_est_2_
| * | S | BR | BR | cpu_est_0_
| * | S | BR | BR | inst_CLK_000_NE_D0
| * | S | BR | BR | inst_CLK_000_D0
| * | S | BS | BR | RN_VMA
| * | S | BS | BR | RN_AMIGA_ADDR_ENABLE
| * | S | BS | BR | RN_BG_000
| * | S | BR | BR | CLK_000_N_SYNC_4_
| * | S | BS | BR | inst_DTACK_D0
| | | | | BGACK_000
Block E
block level set pt :
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| | | | | AS_000
| | | | | BERR
| | | | | AMIGA_BUS_DATA_DIR
| | | | | CIIN
| * | S | BS | BR | inst_CLK_000_NE
| * | S | BS | BR | inst_CLK_000_D1
| | | | | CIIN_0
| * | S | BS | BR | CLK_000_N_SYNC_9_
| * | S | BS | BR | CLK_000_N_SYNC_0_
| * | S | BS | BR | CLK_000_P_SYNC_0_
Block F
block level set pt :
block level reset pt : !RST
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BR | BS | SM_AMIGA_7_
| * | S | BS | BR | SM_AMIGA_0_
| * | S | BS | BS | CLK_OUT_PRE_Dreg
| * | S | BS | BR | RESET_DLY_4_
| * | S | BS | BR | RESET_DLY_3_
| * | S | BS | BR | RESET_DLY_2_
| * | S | BS | BR | RESET_DLY_1_
| * | S | BS | BR | RESET_DLY_0_
| * | S | BS | BR | SM_AMIGA_3_
| * | S | BS | BR | SM_AMIGA_2_
| * | S | BR | BS | inst_VPA_D
| * | S | BS | BS | CLK_000_N_SYNC_7_
| * | S | BS | BS | CLK_000_P_SYNC_8_
| * | S | BS | BS | inst_CLK_OUT_PRE
| * | S | BS | BS | inst_CLK_OUT_PRE_50
| | | | | A_17_
| | | | | FC_1_
| | | | | FC_0_
| | | | | A1
| | | | | IPL_1_
Block G
block level set pt : !RST
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | RW
| | | | | SIZE_0_
| * | S | BS | BR | A0
| * | S | BR | BR | E
| | | | | CLK_DIV_OUT
| * | S | BS | BR | inst_AS_000_DMA
| * | S | BR | BR | RN_E
| * | S | BS | BR | SIZE_DMA_1_
| * | S | BR | BS | RESET_DLY_5_
| * | S | BS | BR | SIZE_DMA_0_
| * | S | BS | BR | RN_RW
| * | S | BR | BR | CLK_000_N_SYNC_3_
| * | S | BR | BR | CLK_000_N_SYNC_1_
| * | S | BR | BR | CLK_000_P_SYNC_3_
| * | S | BR | BR | CLK_000_P_SYNC_9_
| | | | | IPL_2_
| | | | | IPL_0_
Block H
block level set pt : !RST
block level reset pt :
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | RW_000
| | | | | AS_030
| * | S | BS | BR | DSACK1
| | | | | SIZE_1_
| * | S | BS | BR | BGACK_030
| | | | | FPU_CS
| * | S | BS | BR | RN_BGACK_030
| * | S | BS | BR | inst_AS_030_D0
| * | S | BS | BR | inst_AS_030_000_SYNC
| * | S | BS | BR | RN_DSACK1
| * | S | BS | BR | RN_RW_000
| * | S | BR | BR | CLK_000_N_SYNC_10_
| * | S | BS | BR | inst_BGACK_030_INT_D
| * | S | BS | BR | inst_DS_030_D0
| | | | | A_23_
| | | | | A_22_
<Note> (S) means the macrocell is configured in synchronous mode
i.e. it uses the block-level set and reset pt.
(A) means the macrocell is configured in asynchronous mode
i.e. it can have its independant set or reset pt.
(BS) means the block-level set pt is selected.
(BR) means the block-level reset pt is selected.

BLOCK_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx A0 A0 pin 69 mx A17 SIZE_0_ pin 70
mx A1 ... ... mx A18 inst_DS_030_D0 mcell H10
mx A2 inst_CLK_030_H mcell A5 mx A19 ... ...
mx A3 A1 pin 60 mx A20 SIZE_1_ pin 79
mx A4 SM_AMIGA_6_ mcell C12 mx A21 RST pin 86
mx A5 ... ... mx A22 inst_AS_000_DMA mcell G5
mx A6 RW_000 pin 80 mx A23 RN_BGACK_030 mcell H4
mx A7 ... ... mx A24CLK_000_N_SYNC_7_ mcell F14
mx A8 UDS_000 pin 32 mx A25 ... ...
mx A9inst_UDS_000_INT mcell A12 mx A26 ... ...
mx A10CLK_000_N_SYNC_5_ mcell B13 mx A27 LDS_000 pin 31
mx A11 ... ... mx A28 CLK_030 pin 64
mx A12CLK_000_P_SYNC_1_ mcell B10 mx A29 ... ...
mx A13 ... ... mx A30inst_LDS_000_INT mcell A8
mx A14CLK_000_N_SYNC_10_ mcell H2 mx A31inst_nEXP_SPACE_D0 mcell B5
mx A15 RN_DS_030 mcell A0 mx A32 ... ...
mx A16 AS_000 pin 42
----------------------------------------------------------------------------
BLOCK_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx B0 IPL_0_ pin 67 mx B17 RN_IPL_030_0_ mcell B8
mx B1 RESET_DLY_4_ mcell F12 mx B18 RESET_DLY_1_ mcell F9
mx B2inst_CLK_000_NE_D0 mcell D10 mx B19CLK_000_P_SYNC_0_ mcell E6
mx B3 IPL_1_ pin 56 mx B20 RESET_DLY_7_ mcell B14
mx B4 cpu_est_0_ mcell D6 mx B21 RST pin 86
mx B5CLK_000_N_SYNC_1_ mcell G10 mx B22 IPL_2_ pin 68
mx B6 RESET_DLY_0_ mcell F13 mx B23 ... ...
mx B7 ... ... mx B24 ... ...
mx B8 inst_CLK_000_NE mcell E8 mx B25 ... ...
mx B9 RESET_DLY_5_ mcell G13 mx B26 RN_RESET mcell B0
mx B10CLK_000_P_SYNC_3_ mcell G14 mx B27 RN_IPL_030_2_ mcell B4
mx B11 RN_E mcell G4 mx B28 cpu_est_2_ mcell D2
mx B12 RN_IPL_030_1_ mcell B12 mx B29 cpu_est_1_ mcell D13
mx B13CLK_000_N_SYNC_4_ mcell D3 mx B30 RESET_DLY_3_ mcell F1
mx B14 RESET_DLY_2_ mcell F5 mx B31 ... ...
mx B15 nEXP_SPACE pin 14 mx B32CLK_OUT_PRE_Dreg mcell F8
mx B16 RESET_DLY_6_ mcell B9
----------------------------------------------------------------------------
BLOCK_C_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx C0 RST pin 86 mx C17 BERR pin 41
mx C1inst_DS_000_ENABLE mcell C1 mx C18CLK_000_P_SYNC_6_ mcell C10
mx C2CLK_000_P_SYNC_4_ mcell B6 mx C19inst_AMIGA_BUS_ENABLE_DMA_LOW mcell A9
mx C3 inst_AS_000_INT mcell C9 mx C20 RN_BGACK_030 mcell H4
mx C4 SM_AMIGA_6_ mcell C12 mx C21 ... ...
mx C5CLK_000_P_SYNC_9_ mcell G3 mx C22 SM_AMIGA_5_ mcell C2
mx C6 inst_CLK_000_PE mcell C4 mx C23 ... ...
mx C7CLK_000_P_SYNC_5_ mcell C14 mx C24 ... ...
mx C8 RW pin 71 mx C25 SM_AMIGA_7_ mcell F0
mx C9 SM_AMIGA_3_ mcell F2 mx C26 ... ...
mx C10 inst_CLK_000_D0 mcell D14 mx C27 inst_AS_030_D0 mcell H9
mx C11 SM_AMIGA_2_ mcell F6 mx C28inst_AS_030_000_SYNC mcell H13
mx C12 ... ... mx C29 SM_AMIGA_0_ mcell F4
mx C13 ... ... mx C30 inst_CLK_000_NE mcell E8
mx C14 inst_CLK_000_D1 mcell E5 mx C31inst_nEXP_SPACE_D0 mcell B5
mx C15 SM_AMIGA_4_ mcell C5 mx C32 ... ...
mx C16 SM_AMIGA_1_ mcell C8
----------------------------------------------------------------------------
BLOCK_D_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx D0inst_nEXP_SPACE_D0 mcell B5 mx D17 RN_BG_000 mcell D1
mx D1inst_DS_000_ENABLE mcell C1 mx D18inst_LDS_000_INT mcell A8
mx D2 RN_E mcell G4 mx D19 inst_VPA_D mcell F10
mx D3 CLK_000 pin 11 mx D20inst_CLK_000_NE_D0 mcell D10
mx D4 BG_030 pin 21 mx D21 RST pin 86
mx D5CLK_000_N_SYNC_3_ mcell G6 mx D22 inst_AS_000_DMA mcell G5
mx D6 inst_CLK_000_PE mcell C4 mx D23 RN_BGACK_030 mcell H4
mx D7inst_BGACK_030_INT_D mcell H6 mx D24 ... ...
mx D8 inst_CLK_000_NE mcell E8 mx D25inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell A13
mx D9 DTACK pin 30 mx D26 inst_CLK_000_D1 mcell E5
mx D10 inst_CLK_000_D0 mcell D14 mx D27 inst_AS_030_D0 mcell H9
mx D11RN_AMIGA_ADDR_ENABLE mcell D5 mx D28inst_AS_030_000_SYNC mcell H13
mx D12 DS_030 pin 98 mx D29 cpu_est_1_ mcell D13
mx D13 ... ... mx D30 cpu_est_0_ mcell D6
mx D14 RN_VMA mcell D4 mx D31 SM_AMIGA_7_ mcell F0
mx D15inst_UDS_000_INT mcell A12 mx D32 DSACK1 pin 81
mx D16 cpu_est_2_ mcell D2
----------------------------------------------------------------------------
BLOCK_E_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17
mx E1 FC_1_ pin 58 mx E18 BGACK_000 pin 28
mx E2 CIIN_0 mcell E9 mx E19 A_30_ pin 5
mx E3 A_27_ pin 16 mx E20 A_22_ pin 84
mx E4 A_29_ pin 6 mx E21CLK_000_N_SYNC_8_ mcell A1
mx E5 A_24_ pin 19 mx E22 A_25_ pin 18
mx E6 RW_000 pin 80 mx E23 inst_AS_000_INT mcell C9
mx E7 A_28_ pin 15 mx E24 FC_0_ pin 57
mx E8 FPU_SENSE pin 91 mx E25 A_31_ pin 4
mx E9 AS_030 pin 82 mx E26 inst_CLK_000_D1 mcell E5
mx E10 inst_CLK_000_D0 mcell D14 mx E27 inst_AS_030_D0 mcell H9
mx E11 A_16_ pin 96 mx E28inst_nEXP_SPACE_D0 mcell B5
mx E12 A_19_ pin 97 mx E29 A_20_ pin 93
mx E13 A_17_ pin 59 mx E30 ... ...
mx E14CLK_000_N_SYNC_11_ mcell A10 mx E31 A_18_ pin 95
mx E15 A_21_ pin 94 mx E32 A_23_ pin 85
mx E16 AS_000 pin 42
----------------------------------------------------------------------------
BLOCK_F_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx F0CLK_000_N_SYNC_6_ mcell A2 mx F17 BERR pin 41
mx F1 cpu_est_1_ mcell D13 mx F18 RESET_DLY_1_ mcell F9
mx F2 inst_VPA_D mcell F10 mx F19 SM_AMIGA_2_ mcell F6
mx F3inst_CLK_OUT_PRE_50 mcell F11 mx F20inst_CLK_000_NE_D0 mcell D10
mx F4 cpu_est_0_ mcell D6 mx F21 RN_E mcell G4
mx F5 ... ... mx F22 RESET_DLY_0_ mcell F13
mx F6 inst_CLK_000_PE mcell C4 mx F23 ... ...
mx F7 SM_AMIGA_1_ mcell C8 mx F24 RST pin 86
mx F8 inst_CLK_000_NE mcell E8 mx F25inst_CLK_OUT_PRE mcell F7
mx F9CLK_000_P_SYNC_7_ mcell C6 mx F26 ... ...
mx F10 VPA pin 36 mx F27 RESET_DLY_2_ mcell F5
mx F11sm_amiga_ns_0_3_0__n mcell C13 mx F28 SM_AMIGA_3_ mcell F2
mx F12 ... ... mx F29 SM_AMIGA_0_ mcell F4
mx F13 inst_DTACK_D0 mcell D7 mx F30 RESET_DLY_3_ mcell F1
mx F14 RN_VMA mcell D4 mx F31 RESET_DLY_4_ mcell F12
mx F15 SM_AMIGA_4_ mcell C5 mx F32 ... ...
mx F16 cpu_est_2_ mcell D2
----------------------------------------------------------------------------
BLOCK_G_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx G0 RN_BGACK_030 mcell H4 mx G17 RN_RW mcell G0
mx G1 RESET_DLY_1_ mcell F9 mx G18CLK_000_N_SYNC_2_ mcell B2
mx G2inst_CLK_000_NE_D0 mcell D10 mx G19 ... ...
mx G3CLK_000_N_SYNC_0_ mcell E2 mx G20 CLK_030 pin 64
mx G4 cpu_est_0_ mcell D6 mx G21 cpu_est_1_ mcell D13
mx G5 ... ... mx G22 inst_AS_000_DMA mcell G5
mx G6 RW_000 pin 80 mx G23 SIZE_DMA_0_ mcell G2
mx G7CLK_000_P_SYNC_8_ mcell F3 mx G24 RST pin 86
mx G8 UDS_000 pin 32 mx G25 ... ...
mx G9 RESET_DLY_5_ mcell G13 mx G26 AS_000 pin 42
mx G10CLK_000_P_SYNC_2_ mcell A6 mx G27 LDS_000 pin 31
mx G11 RN_E mcell G4 mx G28inst_nEXP_SPACE_D0 mcell B5
mx G12 SIZE_DMA_1_ mcell G9 mx G29 ... ...
mx G13 ... ... mx G30 RESET_DLY_3_ mcell F1
mx G14 RESET_DLY_2_ mcell F5 mx G31 RESET_DLY_4_ mcell F12
mx G15 RESET_DLY_0_ mcell F13 mx G32CLK_OUT_PRE_Dreg mcell F8
mx G16 cpu_est_2_ mcell D2
----------------------------------------------------------------------------
BLOCK_H_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx H0 RN_BGACK_030 mcell H4 mx H17 A_18_ pin 95
mx H1 BERR pin 41 mx H18 DS_030 pin 98
mx H2CLK_OUT_PRE_Dreg mcell F8 mx H19 AS_030 pin 82
mx H3 inst_AS_000_DMA mcell G5 mx H20 CLK_030 pin 64
mx H4 SM_AMIGA_6_ mcell C12 mx H21 RST pin 86
mx H5 inst_AS_030_D0 mcell H9 mx H22 ... ...
mx H6 FC_0_ pin 57 mx H23CLK_000_N_SYNC_9_ mcell E13
mx H7inst_AS_030_000_SYNC mcell H13 mx H24 ... ...
mx H8 FPU_SENSE pin 91 mx H25 SM_AMIGA_7_ mcell F0
mx H9CLK_000_N_SYNC_8_ mcell A1 mx H26 A_16_ pin 96
mx H10 SIZE_DMA_1_ mcell G9 mx H27 A_19_ pin 97
mx H11 RW pin 71 mx H28inst_nEXP_SPACE_D0 mcell B5
mx H12 FC_1_ pin 58 mx H29 inst_CLK_000_PE mcell C4
mx H13 A_17_ pin 59 mx H30 RN_RW_000 mcell H0
mx H14 SM_AMIGA_0_ mcell F4 mx H31 SIZE_DMA_0_ mcell G2
mx H15 RN_DSACK1 mcell H12 mx H32 BGACK_000 pin 28
mx H16 SM_AMIGA_1_ mcell C8
----------------------------------------------------------------------------
<Note> CSM indicates the mux inputs from the Central Switch Matrix.
<Note> Source indicates where the signal comes from (pin or macrocell).

PostFit_Equations
~~~~~~~~~~~~~~~~~
P-Terms Fan-in Fan-out Type Name (attributes)
--------- ------ ------- ---- -----------------
1 2 1 Pin SIZE_1_-
1 3 1 Pin SIZE_1_.OE
0 0 1 Pin AS_030
1 3 1 Pin AS_030.OE
1 2 1 Pin AS_000-
1 1 1 Pin AS_000.OE
1 3 1 Pin UDS_000-
1 1 1 Pin UDS_000.OE
1 3 1 Pin LDS_000-
1 1 1 Pin LDS_000.OE
0 0 1 Pin BERR
1 9 1 Pin BERR.OE
1 1 1 Pin CLK_DIV_OUT
1 1 1 Pin CLK_EXP
1 9 1 Pin FPU_CS-
1 1 1 Pin DTACK
1 3 1 Pin DTACK.OE
1 0 1 Pin AVEC
2 4 1 Pin AMIGA_BUS_DATA_DIR
1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
1 2 1 Pin AMIGA_BUS_ENABLE_HIGH
1 13 1 Pin CIIN
1 1 1 Pin CIIN.OE
1 2 1 Pin SIZE_0_-
1 3 1 Pin SIZE_0_.OE
2 3 1 Pin IPL_030_2_.D
1 1 1 Pin IPL_030_2_.AP
1 1 1 Pin IPL_030_2_.C
2 3 1 Pin IPL_030_1_.D
1 1 1 Pin IPL_030_1_.AP
1 1 1 Pin IPL_030_1_.C
1 1 1 Pin RW_000.OE
3 8 1 Pin RW_000.D-
1 1 1 Pin RW_000.AP
1 1 1 Pin RW_000.C
2 3 1 Pin IPL_030_0_.D
1 1 1 Pin IPL_030_0_.AP
1 1 1 Pin IPL_030_0_.C
1 3 1 Pin DS_030.OE
7 9 1 Pin DS_030.D
1 1 1 Pin DS_030.AP
1 1 1 Pin DS_030.C
1 3 1 Pin A0.OE
1 4 1 Pin A0.D
1 1 1 Pin A0.AP
1 1 1 Pin A0.C
2 5 1 Pin BG_000.D-
1 1 1 Pin BG_000.AP
1 1 1 Pin BG_000.C
2 3 1 Pin BGACK_030.D
1 1 1 Pin BGACK_030.AP
1 1 1 Pin BGACK_030.C
1 1 1 Pin DSACK1.OE
4 8 1 Pin DSACK1.D-
1 1 1 Pin DSACK1.AP
1 1 1 Pin DSACK1.C
3 5 1 PinX1 E.D.X1
1 5 1 PinX2 E.D.X2
1 1 1 Pin E.C
3 8 1 PinX1 VMA.D.X1
1 2 1 PinX2 VMA.D.X2
1 1 1 Pin VMA.AP
1 1 1 Pin VMA.C
1 1 1 Pin RESET.AR
2 9 1 Pin RESET.D
1 1 1 Pin RESET.C
1 1 1 Pin RW.OE
4 7 1 Pin RW.D-
1 1 1 Pin RW.AP
1 1 1 Pin RW.C
3 8 1 Pin AMIGA_ADDR_ENABLE.D-
1 1 1 Pin AMIGA_ADDR_ENABLE.AP
1 1 1 Pin AMIGA_ADDR_ENABLE.C
2 2 1 Node cpu_est_0_.D
1 1 1 Node cpu_est_0_.C
5 5 1 Node cpu_est_1_.D-
1 1 1 Node cpu_est_1_.C
2 5 1 Node inst_AS_000_INT.D-
1 1 1 Node inst_AS_000_INT.AP
1 1 1 Node inst_AS_000_INT.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.AP
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.AP
1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
1 1 1 Node inst_AS_030_D0.D
1 1 1 Node inst_AS_030_D0.AP
1 1 1 Node inst_AS_030_D0.C
1 1 1 Node inst_nEXP_SPACE_D0.D
1 1 1 Node inst_nEXP_SPACE_D0.AP
1 1 1 Node inst_nEXP_SPACE_D0.C
1 1 1 Node inst_DS_030_D0.D
1 1 1 Node inst_DS_030_D0.AP
1 1 1 Node inst_DS_030_D0.C
6 12 1 Node inst_AS_030_000_SYNC.D
1 1 1 Node inst_AS_030_000_SYNC.AP
1 1 1 Node inst_AS_030_000_SYNC.C
1 1 1 Node inst_BGACK_030_INT_D.D
1 1 1 Node inst_BGACK_030_INT_D.AP
1 1 1 Node inst_BGACK_030_INT_D.C
4 6 1 Node inst_AS_000_DMA.D
1 1 1 Node inst_AS_000_DMA.AP
1 1 1 Node inst_AS_000_DMA.C
1 4 1 Node SIZE_DMA_0_.D-
1 1 1 Node SIZE_DMA_0_.AP
1 1 1 Node SIZE_DMA_0_.C
2 4 1 Node SIZE_DMA_1_.D-
1 1 1 Node SIZE_DMA_1_.AP
1 1 1 Node SIZE_DMA_1_.C
1 1 1 Node inst_VPA_D.D
1 1 1 Node inst_VPA_D.AP
1 1 1 Node inst_VPA_D.C
3 4 1 Node inst_UDS_000_INT.D
1 1 1 Node inst_UDS_000_INT.AP
1 1 1 Node inst_UDS_000_INT.C
3 6 1 Node inst_LDS_000_INT.D
1 1 1 Node inst_LDS_000_INT.AP
1 1 1 Node inst_LDS_000_INT.C
1 1 1 Node inst_DTACK_D0.D
1 1 1 Node inst_DTACK_D0.AP
1 1 1 Node inst_DTACK_D0.C
1 12 1 NodeX1 RESET_DLY_7_.D.X1
1 1 1 NodeX2 RESET_DLY_7_.D.X2
1 1 1 Node RESET_DLY_7_.AR
1 1 1 Node RESET_DLY_7_.C
1 1 1 Node inst_CLK_OUT_PRE_50.D
1 1 1 Node inst_CLK_OUT_PRE_50.C
1 1 1 Node inst_CLK_000_D1.D
1 1 1 Node inst_CLK_000_D1.C
1 1 1 Node inst_CLK_000_D0.D
1 1 1 Node inst_CLK_000_D0.C
11 14 1 Node sm_amiga_ns_0_3_0__n-
4 11 1 Node SM_AMIGA_7_.D-
1 1 1 Node SM_AMIGA_7_.AP
1 1 1 Node SM_AMIGA_7_.C
1 1 1 Node inst_CLK_OUT_PRE.D
1 1 1 Node inst_CLK_OUT_PRE.C
1 1 1 Node inst_CLK_000_PE.D
1 1 1 Node inst_CLK_000_PE.C
1 1 1 Node CLK_000_P_SYNC_9_.D
1 1 1 Node CLK_000_P_SYNC_9_.C
1 1 1 Node inst_CLK_000_NE.D
1 1 1 Node inst_CLK_000_NE.C
1 1 1 Node CLK_000_N_SYNC_11_.D
1 1 1 Node CLK_000_N_SYNC_11_.C
4 5 1 Node cpu_est_2_.D
1 1 1 Node cpu_est_2_.C
1 1 1 Node inst_CLK_000_NE_D0.D
1 1 1 Node inst_CLK_000_NE_D0.C
1 1 1 Node SM_AMIGA_6_.AR
2 8 1 Node SM_AMIGA_6_.D
1 1 1 Node SM_AMIGA_6_.C
1 1 1 Node SM_AMIGA_4_.AR
2 5 1 Node SM_AMIGA_4_.D
1 1 1 Node SM_AMIGA_4_.C
1 1 1 Node SM_AMIGA_0_.AR
2 5 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
1 1 1 Node inst_CLK_030_H.AR
4 7 1 Node inst_CLK_030_H.D
1 1 1 Node inst_CLK_030_H.C
1 2 1 Node CLK_000_P_SYNC_0_.D
1 1 1 Node CLK_000_P_SYNC_0_.C
1 1 1 Node CLK_000_P_SYNC_1_.D
1 1 1 Node CLK_000_P_SYNC_1_.C
1 1 1 Node CLK_000_P_SYNC_2_.D
1 1 1 Node CLK_000_P_SYNC_2_.C
1 1 1 Node CLK_000_P_SYNC_3_.D
1 1 1 Node CLK_000_P_SYNC_3_.C
1 1 1 Node CLK_000_P_SYNC_4_.D
1 1 1 Node CLK_000_P_SYNC_4_.C
1 1 1 Node CLK_000_P_SYNC_5_.D
1 1 1 Node CLK_000_P_SYNC_5_.C
1 1 1 Node CLK_000_P_SYNC_6_.D
1 1 1 Node CLK_000_P_SYNC_6_.C
1 1 1 Node CLK_000_P_SYNC_7_.D
1 1 1 Node CLK_000_P_SYNC_7_.C
1 1 1 Node CLK_000_P_SYNC_8_.D
1 1 1 Node CLK_000_P_SYNC_8_.C
1 2 1 Node CLK_000_N_SYNC_0_.D
1 1 1 Node CLK_000_N_SYNC_0_.C
1 1 1 Node CLK_000_N_SYNC_1_.D
1 1 1 Node CLK_000_N_SYNC_1_.C
1 1 1 Node CLK_000_N_SYNC_2_.D
1 1 1 Node CLK_000_N_SYNC_2_.C
1 1 1 Node CLK_000_N_SYNC_3_.D
1 1 1 Node CLK_000_N_SYNC_3_.C
1 1 1 Node CLK_000_N_SYNC_4_.D
1 1 1 Node CLK_000_N_SYNC_4_.C
1 1 1 Node CLK_000_N_SYNC_5_.D
1 1 1 Node CLK_000_N_SYNC_5_.C
1 1 1 Node CLK_000_N_SYNC_6_.D
1 1 1 Node CLK_000_N_SYNC_6_.C
1 1 1 Node CLK_000_N_SYNC_7_.D
1 1 1 Node CLK_000_N_SYNC_7_.C
1 1 1 Node CLK_000_N_SYNC_8_.D
1 1 1 Node CLK_000_N_SYNC_8_.C
1 1 1 Node CLK_000_N_SYNC_9_.D
1 1 1 Node CLK_000_N_SYNC_9_.C
1 1 1 Node CLK_000_N_SYNC_10_.D
1 1 1 Node CLK_000_N_SYNC_10_.C
1 5 1 NodeX1 RESET_DLY_0_.D.X1
1 1 1 NodeX2 RESET_DLY_0_.D.X2
1 1 1 Node RESET_DLY_0_.AR
1 1 1 Node RESET_DLY_0_.C
1 6 1 NodeX1 RESET_DLY_1_.D.X1
1 1 1 NodeX2 RESET_DLY_1_.D.X2
1 1 1 Node RESET_DLY_1_.AR
1 1 1 Node RESET_DLY_1_.C
1 7 1 NodeX1 RESET_DLY_2_.D.X1
1 1 1 NodeX2 RESET_DLY_2_.D.X2
1 1 1 Node RESET_DLY_2_.AR
1 1 1 Node RESET_DLY_2_.C
1 8 1 NodeX1 RESET_DLY_3_.D.X1
1 1 1 NodeX2 RESET_DLY_3_.D.X2
1 1 1 Node RESET_DLY_3_.AR
1 1 1 Node RESET_DLY_3_.C
1 9 1 NodeX1 RESET_DLY_4_.D.X1
1 1 1 NodeX2 RESET_DLY_4_.D.X2
1 1 1 Node RESET_DLY_4_.AR
1 1 1 Node RESET_DLY_4_.C
1 10 1 NodeX1 RESET_DLY_5_.D.X1
1 1 1 NodeX2 RESET_DLY_5_.D.X2
1 1 1 Node RESET_DLY_5_.AR
1 1 1 Node RESET_DLY_5_.C
1 11 1 NodeX1 RESET_DLY_6_.D.X1
1 1 1 NodeX2 RESET_DLY_6_.D.X2
1 1 1 Node RESET_DLY_6_.AR
1 1 1 Node RESET_DLY_6_.C
1 1 1 Node inst_DS_000_ENABLE.AR
3 7 1 Node inst_DS_000_ENABLE.D
1 1 1 Node inst_DS_000_ENABLE.C
1 1 1 Node SM_AMIGA_1_.AR
2 5 1 Node SM_AMIGA_1_.D
1 1 1 Node SM_AMIGA_1_.C
1 1 1 Node SM_AMIGA_5_.AR
2 5 1 Node SM_AMIGA_5_.D
1 1 1 Node SM_AMIGA_5_.C
6 12 1 NodeX1 SM_AMIGA_3_.D.X1
1 2 1 NodeX2 SM_AMIGA_3_.D.X2
1 1 1 Node SM_AMIGA_3_.AR
1 1 1 Node SM_AMIGA_3_.C
1 1 1 Node SM_AMIGA_2_.AR
3 12 1 Node SM_AMIGA_2_.D
1 1 1 Node SM_AMIGA_2_.C
1 1 1 Node CLK_OUT_PRE_Dreg.D
1 1 1 Node CLK_OUT_PRE_Dreg.C
3 15 1 Node CIIN_0
=========
330 P-Term Total: 330
Total Pins: 61
Total Nodes: 68
Average P-Term/Output: 1
Equations:
!SIZE_1_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q);
AS_030 = (0);
AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q);
!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
AS_000.OE = (BGACK_030.Q);
!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);
UDS_000.OE = (BGACK_030.Q);
!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);
LDS_000.OE = (BGACK_030.Q);
BERR = (0);
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
CLK_DIV_OUT = (CLK_OUT_PRE_Dreg.Q);
CLK_EXP = (CLK_OUT_PRE_Dreg.Q);
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
DTACK = (DSACK1.PIN);
DTACK.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q);
AVEC = (1);
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
# !BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !AS_000.PIN & RW_000.PIN);
!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
CIIN.OE = (CIIN_0);
!SIZE_0_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q);
IPL_030_2_.D = (IPL_2_ & inst_CLK_000_NE.Q
# !inst_CLK_000_NE.Q & IPL_030_2_.Q);
IPL_030_2_.AP = (!RST);
IPL_030_2_.C = (CLK_OSZI);
IPL_030_1_.D = (IPL_1_ & inst_CLK_000_NE.Q
# !inst_CLK_000_NE.Q & IPL_030_1_.Q);
IPL_030_1_.AP = (!RST);
IPL_030_1_.C = (CLK_OSZI);
RW_000.OE = (BGACK_030.Q);
!RW_000.D = (inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !RW.PIN
# !inst_AS_030_D0.Q & !SM_AMIGA_7_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & BERR.PIN
# !inst_AS_030_D0.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & BERR.PIN);
RW_000.AP = (!RST);
RW_000.C = (CLK_OSZI);
IPL_030_0_.D = (IPL_0_ & inst_CLK_000_NE.Q
# !inst_CLK_000_NE.Q & IPL_030_0_.Q);
IPL_030_0_.AP = (!RST);
IPL_030_0_.C = (CLK_OSZI);
DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q);
DS_030.D = (BGACK_030.Q
# AS_000.PIN
# inst_AS_000_DMA.Q & RW_000.PIN
# UDS_000.PIN & LDS_000.PIN
# CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q
# !CLK_030 & DS_030.Q & !RW_000.PIN
# !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN);
DS_030.AP = (!RST);
DS_030.C = (CLK_OSZI);
A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q);
A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
A0.AP = (!RST);
A0.C = (CLK_OSZI);
!BG_000.D = (!BG_030 & !BG_000.Q
# !BG_030 & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0.Q & inst_CLK_000_D0.Q);
BG_000.AP = (!RST);
BG_000.C = (CLK_OSZI);
BGACK_030.D = (BGACK_000 & BGACK_030.Q
# BGACK_000 & inst_CLK_000_PE.Q);
BGACK_030.AP = (!RST);
BGACK_030.C = (CLK_OSZI);
DSACK1.OE = (inst_nEXP_SPACE_D0.Q);
!DSACK1.D = (CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
# !CLK_030 & CLK_000_N_SYNC_8_.Q & SM_AMIGA_1_.Q
# CLK_000_N_SYNC_8_.Q & SM_AMIGA_1_.Q & CLK_OUT_PRE_Dreg.Q
# !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
DSACK1.AP = (!RST);
DSACK1.C = (CLK_OSZI);
E.D.X1 = (E.Q
# cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
# !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
E.D.X2 = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
E.C = (CLK_OSZI);
VMA.D.X1 = (E.Q & VMA.Q
# !E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q
# VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q);
VMA.D.X2 = (!E.Q & VMA.Q);
VMA.AP = (!RST);
VMA.C = (CLK_OSZI);
RESET.AR = (!RST);
RESET.D = (RESET.Q
# !RESET_DLY_7_.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q & RESET_DLY_6_.Q);
RESET.C = (CLK_OSZI);
RW.OE = (!BGACK_030.Q);
!RW.D = (!CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN
# CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN
# !CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN
# CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN);
RW.AP = (!RST);
RW.C = (CLK_OSZI);
!AMIGA_ADDR_ENABLE.D = (!BGACK_030.Q
# !AMIGA_ADDR_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q
# inst_nEXP_SPACE_D0.Q & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q);
AMIGA_ADDR_ENABLE.AP = (!RST);
AMIGA_ADDR_ENABLE.C = (CLK_OSZI);
cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
# cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
cpu_est_0_.C = (CLK_OSZI);
!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
# E.Q & cpu_est_0_.Q & !cpu_est_1_.Q
# !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q
# E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
# !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
cpu_est_1_.C = (CLK_OSZI);
!inst_AS_000_INT.D = (inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
# !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
inst_AS_000_INT.AP = (!RST);
inst_AS_000_INT.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN
# !A1 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN);
inst_AMIGA_BUS_ENABLE_DMA_HIGH.AP = (!RST);
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN
# A1 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN);
inst_AMIGA_BUS_ENABLE_DMA_LOW.AP = (!RST);
inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
inst_AS_030_D0.D = (AS_030.PIN);
inst_AS_030_D0.AP = (!RST);
inst_AS_030_D0.C = (CLK_OSZI);
inst_nEXP_SPACE_D0.D = (nEXP_SPACE);
inst_nEXP_SPACE_D0.AP = (!RST);
inst_nEXP_SPACE_D0.C = (CLK_OSZI);
inst_DS_030_D0.D = (DS_030.PIN);
inst_DS_030_D0.AP = (!RST);
inst_DS_030_D0.C = (CLK_OSZI);
inst_AS_030_000_SYNC.D = (inst_AS_030_D0.Q
# !BERR.PIN
# !BGACK_000 & inst_AS_030_000_SYNC.Q
# !inst_nEXP_SPACE_D0.Q & inst_AS_030_000_SYNC.Q
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q
# FC_1_ & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q);
inst_AS_030_000_SYNC.AP = (!RST);
inst_AS_030_000_SYNC.C = (CLK_OSZI);
inst_BGACK_030_INT_D.D = (BGACK_030.Q);
inst_BGACK_030_INT_D.AP = (!RST);
inst_BGACK_030_INT_D.C = (CLK_OSZI);
inst_AS_000_DMA.D = (BGACK_030.Q
# AS_000.PIN
# !CLK_030 & inst_AS_000_DMA.Q
# UDS_000.PIN & LDS_000.PIN);
inst_AS_000_DMA.AP = (!RST);
inst_AS_000_DMA.C = (CLK_OSZI);
!SIZE_DMA_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN);
SIZE_DMA_0_.AP = (!RST);
SIZE_DMA_0_.C = (CLK_OSZI);
!SIZE_DMA_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN
# !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN);
SIZE_DMA_1_.AP = (!RST);
SIZE_DMA_1_.C = (CLK_OSZI);
inst_VPA_D.D = (VPA);
inst_VPA_D.AP = (!RST);
inst_VPA_D.C = (CLK_OSZI);
inst_UDS_000_INT.D = (inst_DS_030_D0.Q & inst_UDS_000_INT.Q
# inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
# !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & A0.PIN);
inst_UDS_000_INT.AP = (!RST);
inst_UDS_000_INT.C = (CLK_OSZI);
inst_LDS_000_INT.D = (inst_DS_030_D0.Q & inst_LDS_000_INT.Q
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
# !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
inst_LDS_000_INT.AP = (!RST);
inst_LDS_000_INT.C = (CLK_OSZI);
inst_DTACK_D0.D = (DTACK.PIN);
inst_DTACK_D0.AP = (!RST);
inst_DTACK_D0.C = (CLK_OSZI);
RESET_DLY_7_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q & RESET_DLY_6_.Q);
RESET_DLY_7_.D.X2 = (RESET_DLY_7_.Q);
RESET_DLY_7_.AR = (!RST);
RESET_DLY_7_.C = (CLK_OSZI);
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
inst_CLK_000_D1.C = (CLK_OSZI);
inst_CLK_000_D0.D = (CLK_000);
inst_CLK_000_D0.C = (CLK_OSZI);
!sm_amiga_ns_0_3_0__n = (inst_CLK_000_PE.Q & SM_AMIGA_0_.Q
# SM_AMIGA_0_.Q & !BERR.PIN
# !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !BERR.PIN
# !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN
# !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !BERR.PIN
# !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q & !BERR.PIN
# !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & !BERR.PIN
# !inst_nEXP_SPACE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# !inst_CLK_000_D1.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
# inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
!SM_AMIGA_7_.D = (sm_amiga_ns_0_3_0__n & !SM_AMIGA_3_.Q
# sm_amiga_ns_0_3_0__n & BERR.PIN
# inst_VPA_D.Q & !inst_DTACK_D0.Q & sm_amiga_ns_0_3_0__n & inst_CLK_000_NE.Q
# E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & sm_amiga_ns_0_3_0__n & inst_CLK_000_NE.Q & cpu_est_2_.Q);
SM_AMIGA_7_.AP = (!RST);
SM_AMIGA_7_.C = (CLK_OSZI);
inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_50.Q);
inst_CLK_OUT_PRE.C = (CLK_OSZI);
inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
inst_CLK_000_PE.C = (CLK_OSZI);
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
inst_CLK_000_NE.C = (CLK_OSZI);
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q
# cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
# E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
# !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
cpu_est_2_.C = (CLK_OSZI);
inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);
inst_CLK_000_NE_D0.C = (CLK_OSZI);
SM_AMIGA_6_.AR = (!RST);
SM_AMIGA_6_.D = (!inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
# inst_nEXP_SPACE_D0.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q);
SM_AMIGA_6_.C = (CLK_OSZI);
SM_AMIGA_4_.AR = (!RST);
SM_AMIGA_4_.D = (inst_CLK_000_NE.Q & SM_AMIGA_5_.Q
# !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);
SM_AMIGA_4_.C = (CLK_OSZI);
SM_AMIGA_0_.AR = (!RST);
SM_AMIGA_0_.D = (inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
# !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);
SM_AMIGA_0_.C = (CLK_OSZI);
inst_CLK_030_H.AR = (!RST);
inst_CLK_030_H.D = (!BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
# !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
# !CLK_030 & !BGACK_030.Q & !inst_AS_000_DMA.Q & !AS_000.PIN & !UDS_000.PIN
# !CLK_030 & !BGACK_030.Q & !inst_AS_000_DMA.Q & !AS_000.PIN & !LDS_000.PIN);
inst_CLK_030_H.C = (CLK_OSZI);
CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
CLK_000_P_SYNC_0_.C = (CLK_OSZI);
CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
CLK_000_P_SYNC_1_.C = (CLK_OSZI);
CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
CLK_000_P_SYNC_2_.C = (CLK_OSZI);
CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
CLK_000_P_SYNC_3_.C = (CLK_OSZI);
CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
CLK_000_P_SYNC_4_.C = (CLK_OSZI);
CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
CLK_000_P_SYNC_5_.C = (CLK_OSZI);
CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
CLK_000_P_SYNC_6_.C = (CLK_OSZI);
CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
CLK_000_P_SYNC_7_.C = (CLK_OSZI);
CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
CLK_000_P_SYNC_8_.C = (CLK_OSZI);
CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
CLK_000_N_SYNC_1_.C = (CLK_OSZI);
CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
CLK_000_N_SYNC_2_.C = (CLK_OSZI);
CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
CLK_000_N_SYNC_3_.C = (CLK_OSZI);
CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
CLK_000_N_SYNC_4_.C = (CLK_OSZI);
CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
CLK_000_N_SYNC_5_.C = (CLK_OSZI);
CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
CLK_000_N_SYNC_6_.C = (CLK_OSZI);
CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
CLK_000_N_SYNC_7_.C = (CLK_OSZI);
CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
CLK_000_N_SYNC_8_.C = (CLK_OSZI);
CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
CLK_000_N_SYNC_9_.C = (CLK_OSZI);
CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
CLK_000_N_SYNC_10_.C = (CLK_OSZI);
RESET_DLY_0_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
RESET_DLY_0_.D.X2 = (RESET_DLY_0_.Q);
RESET_DLY_0_.AR = (!RST);
RESET_DLY_0_.C = (CLK_OSZI);
RESET_DLY_1_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q);
RESET_DLY_1_.D.X2 = (RESET_DLY_1_.Q);
RESET_DLY_1_.AR = (!RST);
RESET_DLY_1_.C = (CLK_OSZI);
RESET_DLY_2_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q);
RESET_DLY_2_.D.X2 = (RESET_DLY_2_.Q);
RESET_DLY_2_.AR = (!RST);
RESET_DLY_2_.C = (CLK_OSZI);
RESET_DLY_3_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q);
RESET_DLY_3_.D.X2 = (RESET_DLY_3_.Q);
RESET_DLY_3_.AR = (!RST);
RESET_DLY_3_.C = (CLK_OSZI);
RESET_DLY_4_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q);
RESET_DLY_4_.D.X2 = (RESET_DLY_4_.Q);
RESET_DLY_4_.AR = (!RST);
RESET_DLY_4_.C = (CLK_OSZI);
RESET_DLY_5_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q);
RESET_DLY_5_.D.X2 = (RESET_DLY_5_.Q);
RESET_DLY_5_.AR = (!RST);
RESET_DLY_5_.C = (CLK_OSZI);
RESET_DLY_6_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q);
RESET_DLY_6_.D.X2 = (RESET_DLY_6_.Q);
RESET_DLY_6_.AR = (!RST);
RESET_DLY_6_.C = (CLK_OSZI);
inst_DS_000_ENABLE.AR = (!RST);
inst_DS_000_ENABLE.D = (inst_CLK_000_PE.Q & SM_AMIGA_4_.Q
# !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
# inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & RW.PIN);
inst_DS_000_ENABLE.C = (CLK_OSZI);
SM_AMIGA_1_.AR = (!RST);
SM_AMIGA_1_.D = (inst_CLK_000_PE.Q & SM_AMIGA_2_.Q
# !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN);
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_5_.AR = (!RST);
SM_AMIGA_5_.D = (inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
# !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q & BERR.PIN);
SM_AMIGA_5_.C = (CLK_OSZI);
SM_AMIGA_3_.D.X1 = (inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
# inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN
# inst_VPA_D.Q & !inst_DTACK_D0.Q & !inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & BERR.PIN
# inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & BERR.PIN
# E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & BERR.PIN
# E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & BERR.PIN);
SM_AMIGA_3_.D.X2 = (SM_AMIGA_3_.Q & BERR.PIN);
SM_AMIGA_3_.AR = (!RST);
SM_AMIGA_3_.C = (CLK_OSZI);
SM_AMIGA_2_.AR = (!RST);
SM_AMIGA_2_.D = (!inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
# inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q
# E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
CLK_OUT_PRE_Dreg.D = (inst_CLK_OUT_PRE.Q);
CLK_OUT_PRE_Dreg.C = (CLK_OSZI);
CIIN_0 = (inst_nEXP_SPACE_D0.Q & AS_030.PIN
# !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & inst_nEXP_SPACE_D0.Q
# !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
Reverse-Polarity Equations:
Reference in New Issue Copy Permalink