mirror of https://github.com/kr239/68030tk.git
There is a bug somewhere!!!
This commit is contained in:
MHeinrichs
parent
419cf9809f
commit
40e9ea0f2e
|
|
@ -326,7 +326,7 @@ begin
|
|||
DSACK1_INT <= '1';
|
||||
AS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
|
||||
RW_000_INT <= '1';
|
||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030_D0 = '0' AND --as set
|
||||
BGACK_000='1' AND --no dma -cycle
|
||||
|
|
@ -494,7 +494,7 @@ begin
|
|||
|
||||
-- bus drivers
|
||||
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' AND AMIGA_BUS_ENABLE_INT ='0' ELSE
|
||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' ELSE
|
||||
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
||||
'1';
|
||||
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
|
||||
|
|
|
|||
|
|
@ -279512,3 +279512,719 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
|
|||
|
||||
########## Tcl recorder end at 10/05/14 21:32:32 ###########
|
||||
|
||||
|
||||
########## Tcl recorder starts at 10/09/14 13:40:38 ##########
|
||||
|
||||
# Commands to make the Process:
|
||||
# JEDEC File
|
||||
if [catch {open BUS68030.cmd w} rspFile] {
|
||||
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "STYFILENAME: 68030_tk.sty
|
||||
PROJECT: BUS68030
|
||||
WORKING_PATH: \"$proj_dir\"
|
||||
MODULE: BUS68030
|
||||
VHDL_FILE_LIST: 68030-68000-bus.vhd
|
||||
OUTPUT_FILE_NAME: BUS68030
|
||||
SUFFIX_NAME: edi
|
||||
PART: M4A5-128/64-10VC
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete BUS68030.cmd
|
||||
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [catch {open 68030_tk.rsp w} rspFile] {
|
||||
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete 68030_tk.rsp
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
########## Tcl recorder end at 10/09/14 13:40:38 ###########
|
||||
|
||||
|
||||
########## Tcl recorder starts at 10/10/14 22:35:33 ##########
|
||||
|
||||
# Commands to make the Process:
|
||||
# Hierarchy
|
||||
if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
########## Tcl recorder end at 10/10/14 22:35:33 ###########
|
||||
|
||||
|
||||
########## Tcl recorder starts at 10/10/14 22:35:33 ##########
|
||||
|
||||
# Commands to make the Process:
|
||||
# JEDEC File
|
||||
if [catch {open BUS68030.cmd w} rspFile] {
|
||||
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "STYFILENAME: 68030_tk.sty
|
||||
PROJECT: BUS68030
|
||||
WORKING_PATH: \"$proj_dir\"
|
||||
MODULE: BUS68030
|
||||
VHDL_FILE_LIST: 68030-68000-bus.vhd
|
||||
OUTPUT_FILE_NAME: BUS68030
|
||||
SUFFIX_NAME: edi
|
||||
PART: M4A5-128/64-10VC
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete BUS68030.cmd
|
||||
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [catch {open 68030_tk.rsp w} rspFile] {
|
||||
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete 68030_tk.rsp
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
########## Tcl recorder end at 10/10/14 22:35:33 ###########
|
||||
|
||||
|
||||
########## Tcl recorder starts at 10/10/14 22:38:12 ##########
|
||||
|
||||
# Commands to make the Process:
|
||||
# Hierarchy
|
||||
if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
########## Tcl recorder end at 10/10/14 22:38:12 ###########
|
||||
|
||||
|
||||
########## Tcl recorder starts at 10/10/14 22:38:12 ##########
|
||||
|
||||
# Commands to make the Process:
|
||||
# JEDEC File
|
||||
if [catch {open BUS68030.cmd w} rspFile] {
|
||||
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "STYFILENAME: 68030_tk.sty
|
||||
PROJECT: BUS68030
|
||||
WORKING_PATH: \"$proj_dir\"
|
||||
MODULE: BUS68030
|
||||
VHDL_FILE_LIST: 68030-68000-bus.vhd
|
||||
OUTPUT_FILE_NAME: BUS68030
|
||||
SUFFIX_NAME: edi
|
||||
PART: M4A5-128/64-10VC
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete BUS68030.cmd
|
||||
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [catch {open 68030_tk.rsp w} rspFile] {
|
||||
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete 68030_tk.rsp
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
########## Tcl recorder end at 10/10/14 22:38:12 ###########
|
||||
|
||||
|
||||
########## Tcl recorder starts at 10/10/14 22:39:56 ##########
|
||||
|
||||
# Commands to make the Process:
|
||||
# Hierarchy
|
||||
if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
########## Tcl recorder end at 10/10/14 22:39:56 ###########
|
||||
|
||||
|
||||
########## Tcl recorder starts at 10/10/14 22:39:56 ##########
|
||||
|
||||
# Commands to make the Process:
|
||||
# JEDEC File
|
||||
if [catch {open BUS68030.cmd w} rspFile] {
|
||||
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "STYFILENAME: 68030_tk.sty
|
||||
PROJECT: BUS68030
|
||||
WORKING_PATH: \"$proj_dir\"
|
||||
MODULE: BUS68030
|
||||
VHDL_FILE_LIST: 68030-68000-bus.vhd
|
||||
OUTPUT_FILE_NAME: BUS68030
|
||||
SUFFIX_NAME: edi
|
||||
PART: M4A5-128/64-10VC
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete BUS68030.cmd
|
||||
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [catch {open 68030_tk.rsp w} rspFile] {
|
||||
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
|
||||
} else {
|
||||
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
|
||||
"
|
||||
close $rspFile
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
file delete 68030_tk.rsp
|
||||
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
|
||||
return
|
||||
} else {
|
||||
vwait done
|
||||
if [checkResult $done] {
|
||||
return
|
||||
}
|
||||
}
|
||||
|
||||
########## Tcl recorder end at 10/10/14 22:39:56 ###########
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
// Signal Name Cross Reference File
|
||||
// ispLEVER Classic 1.7.00.05.28.13
|
||||
|
||||
// Design '68030_tk' created Sun Oct 05 21:32:39 2014
|
||||
// Design '68030_tk' created Fri Oct 10 22:40:03 2014
|
||||
|
||||
|
||||
// LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
|
|
@ -0,0 +1,29 @@
|
|||
|
||||
GROUP MACH_SEG_A DS_030 RN_DS_030 inst_CLK_030_H inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_UDS_000_INT AVEC CLK_000_N_SYNC_11_
|
||||
CLK_000_P_SYNC_2_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_8_
|
||||
GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_
|
||||
IPL_030_2_ RN_IPL_030_2_ RESET_DLY_7_ RESET_DLY_6_ inst_nEXP_SPACE_D0
|
||||
CLK_EXP CLK_000_P_SYNC_1_ CLK_000_P_SYNC_4_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_5_
|
||||
|
||||
GROUP MACH_SEG_C SM_AMIGA_6_ inst_DS_000_ENABLE inst_AS_000_INT SM_AMIGA_4_
|
||||
SM_AMIGA_1_ SM_AMIGA_5_ AMIGA_BUS_ENABLE_LOW sm_amiga_ns_0_3_0__n
|
||||
inst_CLK_000_PE CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_
|
||||
|
||||
GROUP MACH_SEG_D AMIGA_ADDR_ENABLE RN_AMIGA_ADDR_ENABLE VMA RN_VMA BG_000
|
||||
RN_BG_000 inst_DTACK_D0 LDS_000 UDS_000 DTACK AMIGA_BUS_ENABLE_HIGH
|
||||
cpu_est_1_ cpu_est_2_ cpu_est_0_ inst_CLK_000_D0 CLK_000_N_SYNC_4_
|
||||
inst_CLK_000_NE_D0
|
||||
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 CLK_000_P_SYNC_0_
|
||||
CLK_000_N_SYNC_0_ inst_CLK_000_NE CLK_000_N_SYNC_9_ inst_CLK_000_D1
|
||||
|
||||
GROUP MACH_SEG_F SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_7_ RESET_DLY_4_ RESET_DLY_3_
|
||||
RESET_DLY_2_ RESET_DLY_1_ RESET_DLY_0_ SM_AMIGA_0_ inst_VPA_D CLK_000_P_SYNC_8_
|
||||
CLK_000_N_SYNC_7_ CLK_OUT_PRE_Dreg inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE
|
||||
|
||||
GROUP MACH_SEG_G RW RN_RW A0 RESET_DLY_5_ inst_AS_000_DMA SIZE_DMA_1_ SIZE_DMA_0_
|
||||
E RN_E SIZE_0_ CLK_DIV_OUT CLK_000_P_SYNC_9_ CLK_000_P_SYNC_3_ CLK_000_N_SYNC_1_
|
||||
CLK_000_N_SYNC_3_
|
||||
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030
|
||||
inst_AS_030_000_SYNC inst_DS_030_D0 inst_AS_030_D0 inst_BGACK_030_INT_D
|
||||
FPU_CS SIZE_1_ AS_030 CLK_000_N_SYNC_10_
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,254 @@
|
|||
[DEVICE]
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = No;
|
||||
Pin_MC_1to1 = No;
|
||||
EN_PinReserve_IO = Yes;
|
||||
EN_PinReserve_BIDIR = Yes;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
DATE = 10/10/14;
|
||||
TIME = 22:40:09;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
Pin_Block = No;
|
||||
Pin_Macrocell_Block = No;
|
||||
Routing = No;
|
||||
|
||||
[GLOBAL CONSTRAINTS]
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_GLB_Input_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Logic_Reduction = Yes;
|
||||
XOR_Synthesis = Yes;
|
||||
DT_Synthesis = No;
|
||||
Node_Collapse = Yes;
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = Yes;
|
||||
Clock_Optimize = No;
|
||||
In_Reg_Optimize = Yes;
|
||||
Balanced_Partitioning = Yes;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode = 0;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[LOCATION ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
A_27_ = pin,16,-,C,-;
|
||||
A_26_ = pin,17,-,C,-;
|
||||
SIZE_1_ = pin,79,-,H,-;
|
||||
A_25_ = pin,18,-,C,-;
|
||||
A_24_ = pin,19,-,C,-;
|
||||
A_31_ = pin,4,-,B,-;
|
||||
A_23_ = pin,85,-,H,-;
|
||||
A_22_ = pin,84,-,H,-;
|
||||
A_21_ = pin,94,-,A,-;
|
||||
A_20_ = pin,93,-,A,-;
|
||||
IPL_2_ = pin,68,-,G,-;
|
||||
A_19_ = pin,97,-,A,-;
|
||||
A_18_ = pin,95,-,A,-;
|
||||
FC_1_ = pin,58,-,F,-;
|
||||
A_17_ = pin,59,-,F,-;
|
||||
AS_030 = pin,82,-,H,-;
|
||||
A_16_ = pin,96,-,A,-;
|
||||
AS_000 = pin,42,-,E,-;
|
||||
IPL_1_ = pin,56,-,F,-;
|
||||
UDS_000 = pin,32,-,D,-;
|
||||
IPL_0_ = pin,67,-,G,-;
|
||||
LDS_000 = pin,31,-,D,-;
|
||||
FC_0_ = pin,57,-,F,-;
|
||||
A1 = pin,60,-,F,-;
|
||||
nEXP_SPACE = pin,14,-,-,-;
|
||||
BERR = pin,41,-,E,-;
|
||||
BG_030 = pin,21,-,C,-;
|
||||
BGACK_000 = pin,28,-,D,-;
|
||||
CLK_030 = pin,64,-,-,-;
|
||||
CLK_000 = pin,11,-,-,-;
|
||||
CLK_OSZI = pin,61,-,-,-;
|
||||
CLK_DIV_OUT = pin,65,-,G,-;
|
||||
CLK_EXP = pin,10,-,B,-;
|
||||
FPU_CS = pin,78,-,H,-;
|
||||
FPU_SENSE = pin,91,-,A,-;
|
||||
DTACK = pin,30,-,D,-;
|
||||
AVEC = pin,92,-,A,-;
|
||||
VPA = pin,36,-,-,-;
|
||||
RST = pin,86,-,-,-;
|
||||
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
|
||||
CIIN = pin,47,-,E,-;
|
||||
SIZE_0_ = pin,70,-,G,-;
|
||||
A_30_ = pin,5,-,B,-;
|
||||
A_29_ = pin,6,-,B,-;
|
||||
A_28_ = pin,15,-,C,-;
|
||||
IPL_030_2_ = pin,9,-,B,-;
|
||||
IPL_030_1_ = pin,7,-,B,-;
|
||||
RW_000 = pin,80,-,H,-;
|
||||
IPL_030_0_ = pin,8,-,B,-;
|
||||
DS_030 = pin,98,-,A,-;
|
||||
A0 = pin,69,-,G,-;
|
||||
BG_000 = pin,29,-,D,-;
|
||||
BGACK_030 = pin,83,-,H,-;
|
||||
DSACK1 = pin,81,-,H,-;
|
||||
E = pin,66,-,G,-;
|
||||
VMA = pin,35,-,D,-;
|
||||
RESET = pin,3,-,B,-;
|
||||
RW = pin,71,-,G,-;
|
||||
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
|
||||
cpu_est_0_ = node,-,-,D,6;
|
||||
cpu_est_1_ = node,-,-,D,13;
|
||||
inst_AS_000_INT = node,-,-,C,9;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,A,13;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,A,9;
|
||||
inst_AS_030_D0 = node,-,-,H,9;
|
||||
inst_nEXP_SPACE_D0 = node,-,-,B,5;
|
||||
inst_DS_030_D0 = node,-,-,H,10;
|
||||
inst_AS_030_000_SYNC = node,-,-,H,13;
|
||||
inst_BGACK_030_INT_D = node,-,-,H,6;
|
||||
inst_AS_000_DMA = node,-,-,G,5;
|
||||
SIZE_DMA_0_ = node,-,-,G,2;
|
||||
SIZE_DMA_1_ = node,-,-,G,9;
|
||||
inst_VPA_D = node,-,-,F,10;
|
||||
inst_UDS_000_INT = node,-,-,A,12;
|
||||
inst_LDS_000_INT = node,-,-,A,8;
|
||||
inst_DTACK_D0 = node,-,-,D,7;
|
||||
RESET_DLY_7_ = node,-,-,B,14;
|
||||
inst_CLK_OUT_PRE_50 = node,-,-,F,11;
|
||||
inst_CLK_000_D1 = node,-,-,E,5;
|
||||
inst_CLK_000_D0 = node,-,-,D,14;
|
||||
sm_amiga_ns_0_3_0__n = node,-,-,C,13;
|
||||
SM_AMIGA_7_ = node,-,-,F,0;
|
||||
inst_CLK_OUT_PRE = node,-,-,F,7;
|
||||
inst_CLK_000_PE = node,-,-,C,4;
|
||||
CLK_000_P_SYNC_9_ = node,-,-,G,3;
|
||||
inst_CLK_000_NE = node,-,-,E,8;
|
||||
CLK_000_N_SYNC_11_ = node,-,-,A,10;
|
||||
cpu_est_2_ = node,-,-,D,2;
|
||||
inst_CLK_000_NE_D0 = node,-,-,D,10;
|
||||
SM_AMIGA_6_ = node,-,-,C,12;
|
||||
SM_AMIGA_4_ = node,-,-,C,5;
|
||||
SM_AMIGA_0_ = node,-,-,F,4;
|
||||
inst_CLK_030_H = node,-,-,A,5;
|
||||
CLK_000_P_SYNC_0_ = node,-,-,E,6;
|
||||
CLK_000_P_SYNC_1_ = node,-,-,B,10;
|
||||
CLK_000_P_SYNC_2_ = node,-,-,A,6;
|
||||
CLK_000_P_SYNC_3_ = node,-,-,G,14;
|
||||
CLK_000_P_SYNC_4_ = node,-,-,B,6;
|
||||
CLK_000_P_SYNC_5_ = node,-,-,C,14;
|
||||
CLK_000_P_SYNC_6_ = node,-,-,C,10;
|
||||
CLK_000_P_SYNC_7_ = node,-,-,C,6;
|
||||
CLK_000_P_SYNC_8_ = node,-,-,F,3;
|
||||
CLK_000_N_SYNC_0_ = node,-,-,E,2;
|
||||
CLK_000_N_SYNC_1_ = node,-,-,G,10;
|
||||
CLK_000_N_SYNC_2_ = node,-,-,B,2;
|
||||
CLK_000_N_SYNC_3_ = node,-,-,G,6;
|
||||
CLK_000_N_SYNC_4_ = node,-,-,D,3;
|
||||
CLK_000_N_SYNC_5_ = node,-,-,B,13;
|
||||
CLK_000_N_SYNC_6_ = node,-,-,A,2;
|
||||
CLK_000_N_SYNC_7_ = node,-,-,F,14;
|
||||
CLK_000_N_SYNC_8_ = node,-,-,A,1;
|
||||
CLK_000_N_SYNC_9_ = node,-,-,E,13;
|
||||
CLK_000_N_SYNC_10_ = node,-,-,H,2;
|
||||
RESET_DLY_0_ = node,-,-,F,13;
|
||||
RESET_DLY_1_ = node,-,-,F,9;
|
||||
RESET_DLY_2_ = node,-,-,F,5;
|
||||
RESET_DLY_3_ = node,-,-,F,1;
|
||||
RESET_DLY_4_ = node,-,-,F,12;
|
||||
RESET_DLY_5_ = node,-,-,G,13;
|
||||
RESET_DLY_6_ = node,-,-,B,9;
|
||||
inst_DS_000_ENABLE = node,-,-,C,1;
|
||||
SM_AMIGA_1_ = node,-,-,C,8;
|
||||
SM_AMIGA_5_ = node,-,-,C,2;
|
||||
SM_AMIGA_3_ = node,-,-,F,2;
|
||||
SM_AMIGA_2_ = node,-,-,F,6;
|
||||
CLK_OUT_PRE_Dreg = node,-,-,F,8;
|
||||
CIIN_0 = node,-,-,E,9;
|
||||
|
||||
[GROUP ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
|
||||
[RESOURCE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[SLEWRATE]
|
||||
Default = SLOW;
|
||||
FAST = AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AVEC,BG_000,LDS_000,UDS_000,DTACK,RW_000,AS_000,CLK_DIV_OUT,CLK_EXP,FPU_CS,AS_030,RW,SIZE_1_,SIZE_0_,BGACK_030,IPL_030_0_,IPL_030_1_,IPL_030_2_,RESET,CIIN,DS_030,BERR,A0,DSACK1;
|
||||
|
||||
[PULLUP]
|
||||
Default = Up;
|
||||
|
||||
[NETLIST/DELAY FORMAT]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
|
||||
[OSM BYPASS]
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Prefit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
||||
|
|
@ -0,0 +1,166 @@
|
|||
|--------------------------------------------|
|
||||
|- ispLEVER Fitter Report File -|
|
||||
|- Version 1.7.00.05.28.13 -|
|
||||
|- (c)Copyright, Lattice Semiconductor 2002 -|
|
||||
|--------------------------------------------|
|
||||
|
||||
|
||||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Fri Oct 10 22:40:09 2014
|
||||
|
||||
|
||||
Pin 16 A_27_
|
||||
Pin 17 A_26_
|
||||
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 271
|
||||
Pin 18 A_25_
|
||||
Pin 19 A_24_
|
||||
Pin 4 A_31_
|
||||
Pin 85 A_23_
|
||||
Pin 84 A_22_
|
||||
Pin 94 A_21_
|
||||
Pin 93 A_20_
|
||||
Pin 68 IPL_2_
|
||||
Pin 97 A_19_
|
||||
Pin 95 A_18_
|
||||
Pin 58 FC_1_
|
||||
Pin 59 A_17_
|
||||
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
|
||||
Pin 96 A_16_
|
||||
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
|
||||
Pin 56 IPL_1_
|
||||
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
|
||||
Pin 67 IPL_0_
|
||||
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
|
||||
Pin 57 FC_0_
|
||||
Pin 60 A1
|
||||
Pin 14 nEXP_SPACE
|
||||
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
|
||||
Pin 21 BG_030
|
||||
Pin 28 BGACK_000
|
||||
Pin 64 CLK_030
|
||||
Pin 11 CLK_000
|
||||
Pin 61 CLK_OSZI
|
||||
Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247
|
||||
Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127
|
||||
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 277
|
||||
Pin 91 FPU_SENSE
|
||||
Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173
|
||||
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
|
||||
Pin 36 VPA
|
||||
Pin 86 RST
|
||||
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
|
||||
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 187
|
||||
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
|
||||
Pin 5 A_30_
|
||||
Pin 6 A_29_
|
||||
Pin 15 A_28_
|
||||
Pin 9 IPL_030_2_ Reg ; S6=0 S9=1 Pair 131
|
||||
Pin 7 IPL_030_1_ Reg ; S6=0 S9=1 Pair 143
|
||||
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
|
||||
Pin 8 IPL_030_0_ Reg ; S6=0 S9=1 Pair 137
|
||||
Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 101
|
||||
Pin 69 A0 Reg ; S6=1 S9=1 Pair 257
|
||||
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
|
||||
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
|
||||
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 287
|
||||
Pin 66 E Reg ; S6=1 S9=1 Pair 251
|
||||
Pin 35 VMA Reg ; S6=1 S9=1 Pair 179
|
||||
Pin 3 RESET Reg ; S6=1 S9=1 Pair 125
|
||||
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
|
||||
Pin 33 AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1 Pair 181
|
||||
Node 271 RN_SIZE_1_ Comb ; S6=1 S9=1
|
||||
Node 281 RN_AS_030 Comb ; S6=1 S9=1
|
||||
Node 203 RN_AS_000 Comb ; S6=1 S9=1
|
||||
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
|
||||
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
|
||||
Node 197 RN_BERR Comb ; S6=1 S9=1
|
||||
Node 173 RN_DTACK Comb ; S6=1 S9=1
|
||||
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
|
||||
Node 131 RN_IPL_030_2_ Reg ; S6=0 S9=1
|
||||
Node 143 RN_IPL_030_1_ Reg ; S6=0 S9=1
|
||||
Node 269 RN_RW_000 Reg ; S6=1 S9=1
|
||||
Node 137 RN_IPL_030_0_ Reg ; S6=0 S9=1
|
||||
Node 101 RN_DS_030 Reg ; S6=1 S9=1
|
||||
Node 257 RN_A0 Reg ; S6=1 S9=1
|
||||
Node 175 RN_BG_000 Reg ; S6=1 S9=1
|
||||
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
|
||||
Node 287 RN_DSACK1 Reg ; S6=1 S9=1
|
||||
Node 251 RN_E Reg ; S6=1 S9=1
|
||||
Node 179 RN_VMA Reg ; S6=1 S9=1
|
||||
Node 125 RN_RESET Reg ; S6=1 S9=1
|
||||
Node 245 RN_RW Reg ; S6=1 S9=1
|
||||
Node 181 RN_AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1
|
||||
Node 182 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 193 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 163 inst_AS_000_INT Reg ; S6=0 S9=1
|
||||
Node 121 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
|
||||
Node 115 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
|
||||
Node 283 inst_AS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 133 inst_nEXP_SPACE_D0 Reg ; S6=0 S9=1
|
||||
Node 284 inst_DS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 289 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 278 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
|
||||
Node 253 inst_AS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 236 inst_VPA_D Reg ; S6=0 S9=1
|
||||
Node 119 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 113 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 184 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 146 RESET_DLY_7_ Reg ; S6=1 S9=1
|
||||
Node 238 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 205 inst_CLK_000_D1 Reg ; S6=1 S9=1
|
||||
Node 194 inst_CLK_000_D0 Reg ; S6=1 S9=1
|
||||
Node 169 sm_amiga_ns_0_3_0__n Comb ; S6=1 S9=1
|
||||
Node 221 SM_AMIGA_7_ Reg ; S6=0 S9=1
|
||||
Node 232 inst_CLK_OUT_PRE Reg ; S6=1 S9=1
|
||||
Node 155 inst_CLK_000_PE Reg ; S6=1 S9=1
|
||||
Node 250 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 209 inst_CLK_000_NE Reg ; S6=1 S9=1
|
||||
Node 116 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1
|
||||
Node 176 cpu_est_2_ Reg ; S6=1 S9=1
|
||||
Node 188 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
|
||||
Node 167 SM_AMIGA_6_ Reg ; S6=1 S9=1
|
||||
Node 157 SM_AMIGA_4_ Reg ; S6=1 S9=1
|
||||
Node 227 SM_AMIGA_0_ Reg ; S6=1 S9=1
|
||||
Node 109 inst_CLK_030_H Reg ; S6=0 S9=1
|
||||
Node 206 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 140 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 110 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 266 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 134 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 170 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 164 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 158 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 226 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 200 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 260 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 128 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 254 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 178 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 145 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 104 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 242 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 103 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 217 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1
|
||||
Node 241 RESET_DLY_0_ Reg ; S6=1 S9=1
|
||||
Node 235 RESET_DLY_1_ Reg ; S6=1 S9=1
|
||||
Node 229 RESET_DLY_2_ Reg ; S6=1 S9=1
|
||||
Node 223 RESET_DLY_3_ Reg ; S6=1 S9=1
|
||||
Node 239 RESET_DLY_4_ Reg ; S6=1 S9=1
|
||||
Node 265 RESET_DLY_5_ Reg ; S6=0 S9=1
|
||||
Node 139 RESET_DLY_6_ Reg ; S6=1 S9=1
|
||||
Node 151 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 161 SM_AMIGA_1_ Reg ; S6=1 S9=1
|
||||
Node 152 SM_AMIGA_5_ Reg ; S6=1 S9=1
|
||||
Node 224 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 230 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 233 CLK_OUT_PRE_Dreg Reg ; S6=1 S9=1
|
||||
Node 211 CIIN_0 Comb ; S6=1 S9=1
|
||||
; Unused Pins & Nodes
|
||||
; -> None Found.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,2 @@
|
|||
Part Number: M4A5-128/64-10VC
|
||||
Need not generate svf file according to the constraints, exit
|
||||
|
|
@ -0,0 +1,136 @@
|
|||
|
||||
|
||||
Design Name = 68030_tk.tt4
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
||||
*******************
|
||||
* TIMING ANALYSIS *
|
||||
*******************
|
||||
|
||||
Timing Analysis KEY:
|
||||
One unit of delay time is equivalent to one pass
|
||||
through the Central Switch Matrix.
|
||||
.. Delay ( in this column ) not applicable to the indicated signal.
|
||||
TSU, Set-Up Time ( 0 for input-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and a register setup before clock.
|
||||
TSU is reported on the register.
|
||||
TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and an output pin.
|
||||
TCO is reported on the register.
|
||||
TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and an output pin.
|
||||
TPD is reported on the output pin.
|
||||
TCR, Clocked Output-to-Register Time,
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and the register it drives ( before clock ).
|
||||
TCR is reported on the driving register.
|
||||
|
||||
TSU TCO TPD TCR
|
||||
#passes #passes #passes #passes
|
||||
SIGNAL NAME min max min max min max min max
|
||||
AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. ..
|
||||
DS_030 1 2 0 0 .. .. 1 1
|
||||
RN_DS_030 1 2 0 0 .. .. 1 1
|
||||
A0 1 2 0 0 .. .. .. ..
|
||||
RW 1 2 0 0 .. .. 1 1
|
||||
RN_RW 1 2 0 0 .. .. 1 1
|
||||
inst_AS_000_INT 1 1 1 2 .. .. 2 2
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 2 1 1 .. .. .. ..
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW 1 2 1 1 .. .. .. ..
|
||||
inst_nEXP_SPACE_D0 1 1 1 1 .. .. 1 2
|
||||
inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
|
||||
inst_AS_000_DMA 1 2 .. .. .. .. 1 1
|
||||
SIZE_DMA_0_ 1 2 1 1 .. .. 2 2
|
||||
SIZE_DMA_1_ 1 2 1 1 .. .. 2 2
|
||||
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_DTACK_D0 1 2 .. .. .. .. 1 1
|
||||
inst_CLK_000_D1 .. .. .. .. .. .. 1 2
|
||||
inst_CLK_000_D0 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_7_ 1 2 .. .. .. .. 1 1
|
||||
inst_CLK_000_PE .. .. .. .. .. .. 1 2
|
||||
inst_CLK_000_NE .. .. .. .. .. .. 1 2
|
||||
SM_AMIGA_6_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_4_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_0_ 1 1 .. .. .. .. 1 2
|
||||
inst_CLK_030_H 1 2 .. .. .. .. 1 1
|
||||
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
|
||||
SM_AMIGA_1_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_5_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_3_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_2_ 1 1 .. .. .. .. 1 2
|
||||
AS_000 .. .. .. .. 1 1 .. ..
|
||||
UDS_000 .. .. .. .. 1 1 .. ..
|
||||
LDS_000 .. .. .. .. 1 1 .. ..
|
||||
FPU_CS .. .. .. .. 1 1 .. ..
|
||||
DTACK .. .. .. .. 1 1 .. ..
|
||||
CIIN .. .. .. .. 1 1 .. ..
|
||||
IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RW_000 1 1 0 0 .. .. 1 1
|
||||
RN_RW_000 1 1 0 0 .. .. 1 1
|
||||
IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
BG_000 1 1 0 0 .. .. 1 1
|
||||
RN_BG_000 1 1 0 0 .. .. 1 1
|
||||
BGACK_030 1 1 0 1 .. .. 1 1
|
||||
RN_BGACK_030 1 1 0 1 .. .. 1 1
|
||||
DSACK1 1 1 0 0 .. .. 1 1
|
||||
RN_DSACK1 1 1 0 0 .. .. 1 1
|
||||
E .. .. 0 0 .. .. 1 1
|
||||
RN_E .. .. 0 0 .. .. 1 1
|
||||
VMA .. .. 0 0 .. .. 1 1
|
||||
RN_VMA .. .. 0 0 .. .. 1 1
|
||||
RESET .. .. 0 0 .. .. 1 1
|
||||
RN_RESET .. .. 0 0 .. .. 1 1
|
||||
AMIGA_ADDR_ENABLE .. .. 0 0 .. .. 1 1
|
||||
RN_AMIGA_ADDR_ENABLE .. .. 0 0 .. .. 1 1
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_1_ .. .. .. .. .. .. 1 1
|
||||
inst_AS_030_D0 1 1 1 1 .. .. 1 1
|
||||
inst_DS_030_D0 1 1 .. .. .. .. 1 1
|
||||
inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1
|
||||
inst_VPA_D 1 1 .. .. .. .. 1 1
|
||||
RESET_DLY_7_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
|
||||
sm_amiga_ns_0_3_0__n .. .. .. .. 1 1 .. ..
|
||||
inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_2_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_0_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_1_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_2_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_3_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_4_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_5_ .. .. .. .. .. .. 1 1
|
||||
RESET_DLY_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_OUT_PRE_Dreg .. .. 1 1 .. .. 1 1
|
||||
CIIN_0 .. .. .. .. 1 1 .. ..
|
||||
|
|
@ -0,0 +1,269 @@
|
|||
[DEVICE]
|
||||
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = NO;
|
||||
Pin_MC_1to1 = NO;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 10/10/14;
|
||||
TIME = 22:40:09;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
|
||||
Netlist = VHDL;
|
||||
Delay_File = SDF;
|
||||
Generic_VCC = ;
|
||||
Generic_GND = ;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignment = NO;
|
||||
Pin_Block = NO;
|
||||
Pin_Macrocell_Block = NO;
|
||||
Routing = NO;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
|
||||
Balanced_Partitioning = YES;
|
||||
Spread_Placement = YES;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Inter_Seg_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
|
||||
Fitter_Options = YES;
|
||||
Pinout_Diagram = NO;
|
||||
Pinout_Listing = YES;
|
||||
Detailed_Block_Segment_Summary = YES;
|
||||
Input_Signal_List = YES;
|
||||
Output_Signal_List = YES;
|
||||
Bidir_Signal_List = YES;
|
||||
Node_Signal_List = YES;
|
||||
Signal_Fanout_List = YES;
|
||||
Block_Segment_Fanin_List = YES;
|
||||
Prefit_Eqn = YES;
|
||||
Postfit_Eqn = YES;
|
||||
Page_Break = YES;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
|
||||
Logic_Reduction = YES;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = YES;
|
||||
Node_Collapse = Yes;
|
||||
DT_Synthesis = No;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = YES;
|
||||
In_Reg_Optimize = YES;
|
||||
Clock_Optimize = NO;
|
||||
Conf_Unused_IOs = OUT_LOW;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low, High;
|
||||
Default = High;
|
||||
Low = 8, H, G, F, E, D, C, B, A;
|
||||
Type = GLB;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW, FAST, 28, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE,
|
||||
AMIGA_BUS_ENABLE_HIGH, AVEC, BG_000, LDS_000, UDS_000, DTACK, RW_000, AS_000,
|
||||
CLK_DIV_OUT, CLK_EXP, FPU_CS, AS_030, RW, SIZE_1_, SIZE_0_, BGACK_030,
|
||||
IPL_030_0_, IPL_030_1_, IPL_030_2_, RESET, CIIN, DS_030, BERR, A0, DSACK1;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
|
||||
Layer = OFF;
|
||||
A_27_ = INPUT,16, C,-;
|
||||
A_26_ = INPUT,17, C,-;
|
||||
SIZE_1_ = BIDIR,79, H,-;
|
||||
A_25_ = INPUT,18, C,-;
|
||||
A_24_ = INPUT,19, C,-;
|
||||
A_31_ = INPUT,4, B,-;
|
||||
A_23_ = INPUT,85, H,-;
|
||||
A_22_ = INPUT,84, H,-;
|
||||
A_21_ = INPUT,94, A,-;
|
||||
A_20_ = INPUT,93, A,-;
|
||||
IPL_2_ = INPUT,68, G,-;
|
||||
A_19_ = INPUT,97, A,-;
|
||||
A_18_ = INPUT,95, A,-;
|
||||
FC_1_ = INPUT,58, F,-;
|
||||
A_17_ = INPUT,59, F,-;
|
||||
AS_030 = BIDIR,82, H,-;
|
||||
A_16_ = INPUT,96, A,-;
|
||||
AS_000 = BIDIR,42, E,-;
|
||||
IPL_1_ = INPUT,56, F,-;
|
||||
UDS_000 = BIDIR,32, D,-;
|
||||
IPL_0_ = INPUT,67, G,-;
|
||||
LDS_000 = BIDIR,31, D,-;
|
||||
FC_0_ = INPUT,57, F,-;
|
||||
A1 = INPUT,60, F,-;
|
||||
nEXP_SPACE = INPUT,14,-,-;
|
||||
BERR = BIDIR,41, E,-;
|
||||
BG_030 = INPUT,21, C,-;
|
||||
BGACK_000 = INPUT,28, D,-;
|
||||
CLK_030 = INPUT,64,-,-;
|
||||
CLK_000 = INPUT,11,-,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||
CLK_EXP = OUTPUT,10, B,-;
|
||||
FPU_CS = OUTPUT,78, H,-;
|
||||
FPU_SENSE = INPUT,91, A,-;
|
||||
DTACK = BIDIR,30, D,-;
|
||||
AVEC = OUTPUT,92, A,-;
|
||||
VPA = INPUT,36,-,-;
|
||||
RST = INPUT,86,-,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
|
||||
CIIN = OUTPUT,47, E,-;
|
||||
SIZE_0_ = BIDIR,70, G,-;
|
||||
A_30_ = INPUT,5, B,-;
|
||||
A_29_ = INPUT,6, B,-;
|
||||
A_28_ = INPUT,15, C,-;
|
||||
IPL_030_2_ = OUTPUT,9, B,-;
|
||||
IPL_030_1_ = OUTPUT,7, B,-;
|
||||
RW_000 = BIDIR,80, H,-;
|
||||
IPL_030_0_ = OUTPUT,8, B,-;
|
||||
DS_030 = BIDIR,98, A,-;
|
||||
A0 = BIDIR,69, G,-;
|
||||
BG_000 = OUTPUT,29, D,-;
|
||||
BGACK_030 = OUTPUT,83, H,-;
|
||||
DSACK1 = BIDIR,81, H,-;
|
||||
E = OUTPUT,66, G,-;
|
||||
VMA = OUTPUT,35, D,-;
|
||||
RESET = OUTPUT,3, B,-;
|
||||
RW = BIDIR,71, G,-;
|
||||
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
|
||||
cpu_est_0_ = NODE,6, D,-;
|
||||
cpu_est_1_ = NODE,13, D,-;
|
||||
inst_AS_000_INT = NODE,9, C,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,13, A,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,9, A,-;
|
||||
inst_AS_030_D0 = NODE,9, H,-;
|
||||
inst_nEXP_SPACE_D0 = NODE,5, B,-;
|
||||
inst_DS_030_D0 = NODE,10, H,-;
|
||||
inst_AS_030_000_SYNC = NODE,13, H,-;
|
||||
inst_BGACK_030_INT_D = NODE,6, H,-;
|
||||
inst_AS_000_DMA = NODE,5, G,-;
|
||||
SIZE_DMA_0_ = NODE,2, G,-;
|
||||
SIZE_DMA_1_ = NODE,9, G,-;
|
||||
inst_VPA_D = NODE,10, F,-;
|
||||
inst_UDS_000_INT = NODE,12, A,-;
|
||||
inst_LDS_000_INT = NODE,8, A,-;
|
||||
inst_DTACK_D0 = NODE,7, D,-;
|
||||
RESET_DLY_7_ = NODE,14, B,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,11, F,-;
|
||||
inst_CLK_000_D1 = NODE,5, E,-;
|
||||
inst_CLK_000_D0 = NODE,14, D,-;
|
||||
sm_amiga_ns_0_3_0__n = NODE,13, C,-;
|
||||
SM_AMIGA_7_ = NODE,0, F,-;
|
||||
inst_CLK_OUT_PRE = NODE,7, F,-;
|
||||
inst_CLK_000_PE = NODE,4, C,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,3, G,-;
|
||||
inst_CLK_000_NE = NODE,8, E,-;
|
||||
CLK_000_N_SYNC_11_ = NODE,10, A,-;
|
||||
cpu_est_2_ = NODE,2, D,-;
|
||||
inst_CLK_000_NE_D0 = NODE,10, D,-;
|
||||
SM_AMIGA_6_ = NODE,12, C,-;
|
||||
SM_AMIGA_4_ = NODE,5, C,-;
|
||||
SM_AMIGA_0_ = NODE,4, F,-;
|
||||
inst_CLK_030_H = NODE,5, A,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,6, E,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,10, B,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,6, A,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,14, G,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,6, B,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,14, C,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,10, C,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,6, C,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,3, F,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,2, E,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,10, G,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,2, B,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,6, G,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,3, D,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,13, B,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,2, A,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,14, F,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,1, A,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,13, E,-;
|
||||
CLK_000_N_SYNC_10_ = NODE,2, H,-;
|
||||
RESET_DLY_0_ = NODE,13, F,-;
|
||||
RESET_DLY_1_ = NODE,9, F,-;
|
||||
RESET_DLY_2_ = NODE,5, F,-;
|
||||
RESET_DLY_3_ = NODE,1, F,-;
|
||||
RESET_DLY_4_ = NODE,12, F,-;
|
||||
RESET_DLY_5_ = NODE,13, G,-;
|
||||
RESET_DLY_6_ = NODE,9, B,-;
|
||||
inst_DS_000_ENABLE = NODE,1, C,-;
|
||||
SM_AMIGA_1_ = NODE,8, C,-;
|
||||
SM_AMIGA_5_ = NODE,2, C,-;
|
||||
SM_AMIGA_3_ = NODE,2, F,-;
|
||||
SM_AMIGA_2_ = NODE,6, F,-;
|
||||
CLK_OUT_PRE_Dreg = NODE,8, F,-;
|
||||
CIIN_0 = NODE,9, E,-;
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
[DEVICE]
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = No;
|
||||
Pin_MC_1to1 = No;
|
||||
EN_PinReserve_IO = Yes;
|
||||
EN_PinReserve_BIDIR = Yes;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
DATE = 10/02/2014;
|
||||
TIME = 23:53:03;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
Pin_Block = No;
|
||||
Pin_Macrocell_Block = No;
|
||||
Routing = No;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
Balanced_Partitioning = Yes;
|
||||
Spread_Placement = Yes;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
Logic_Reduction = Yes;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = Yes;
|
||||
EN_XOR_Synthesis = Yes;
|
||||
XOR_Gate = Yes;
|
||||
Node_Collapse = Yes;
|
||||
Keep_XOR = Yes;
|
||||
DT_Synthesis = No;
|
||||
Clock_PTerm = Min;
|
||||
Reset_PTerm = On;
|
||||
Preset_PTerm = On;
|
||||
Clock_Enable_PTerm = On;
|
||||
Output_Enable_PTerm = On;
|
||||
EN_DT_Synthesis = Yes;
|
||||
Cluster_PTerm = 5;
|
||||
FF_inv = No;
|
||||
EN_Use_CE = No;
|
||||
Use_CE = No;
|
||||
Use_Internal_COM_FB = Yes;
|
||||
EN_use_Internal_COM_FB = Yes;
|
||||
Set_Reset_Swap = No;
|
||||
EN_Set_Reset_Swap = No;
|
||||
Density = No;
|
||||
DeMorgan = Yes;
|
||||
T_FF = Yes;
|
||||
Max_Symbols = 32;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = Yes;
|
||||
EN_Set_Reset_Dont_Care = Yes;
|
||||
In_Reg_Optimize = Yes;
|
||||
EN_In_Reg_Optimize = No;
|
||||
Clock_Optimize = No;
|
||||
Global_Clock_As_Pterm = No;
|
||||
Show_Iterations = No;
|
||||
Routing_Attempts = 2;
|
||||
Conf_Unused_IOs = Out_Low;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW,FAST,28,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AVEC,BG_000,LDS_000,UDS_000,DTACK,RW_000,AS_000,CLK_DIV_OUT,CLK_EXP,FPU_CS,AS_030,RW,SIZE_1_,SIZE_0_,BGACK_030,IPL_030_0_,IPL_030_1_,IPL_030_2_,RESET,CIIN,DS_030,BERR,A0,DSACK1;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
AS_030 = input,82,H,-;
|
||||
A_16_ = input,96,A,-;
|
||||
A_17_ = input,59,F,-;
|
||||
A_18_ = input,95,A,-;
|
||||
A_19_ = input,97,A,-;
|
||||
BGACK_000 = input,28,D,-;
|
||||
BG_030 = input,21,C,-;
|
||||
CLK_000 = input,11,-,-;
|
||||
CLK_030 = input,64,-,-;
|
||||
CLK_OSZI = input,61,-,-;
|
||||
FC_0_ = input,57,F,-;
|
||||
FC_1_ = input,58,F,-;
|
||||
IPL_0_ = input,67,G,-;
|
||||
IPL_1_ = input,56,F,-;
|
||||
IPL_2_ = input,68,G,-;
|
||||
RST = input,86,-,-;
|
||||
RW = input,71,G,-;
|
||||
SIZE_1_ = input,79,H,-;
|
||||
SIZE_0_ = input,70,G,-;
|
||||
VPA = input,36,-,-;
|
||||
AVEC = input,92,A,-;
|
||||
BGACK_030 = input,83,H,-;
|
||||
BG_000 = input,29,D,-;
|
||||
CLK_DIV_OUT = input,65,G,-;
|
||||
CLK_EXP = input,10,B,-;
|
||||
E = input,66,G,-;
|
||||
FPU_CS = input,78,H,-;
|
||||
IPL_030_0_ = input,8,B,-;
|
||||
IPL_030_1_ = input,7,B,-;
|
||||
IPL_030_2_ = input,9,B,-;
|
||||
LDS_000 = input,31,D,-;
|
||||
UDS_000 = input,32,D,-;
|
||||
DTACK = input,30,D,-;
|
||||
RESET = input,3,B,-;
|
||||
AMIGA_BUS_DATA_DIR = input,48,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = input,20,C,-;
|
||||
CIIN = input,47,E,-;
|
||||
A_20_ = input,93,A,-;
|
||||
A_21_ = input,94,A,-;
|
||||
A_22_ = input,84,H,-;
|
||||
A_24_ = input,19,C,-;
|
||||
A_25_ = input,18,C,-;
|
||||
A_26_ = input,17,C,-;
|
||||
A_27_ = input,16,C,-;
|
||||
A_28_ = input,15,C,-;
|
||||
A_29_ = input,6,B,-;
|
||||
A_30_ = input,5,B,-;
|
||||
A_31_ = input,4,B,-;
|
||||
DS_030 = input,98,A,-;
|
||||
BERR = input,41,E,-;
|
||||
nEXP_SPACE = input,14,-,-;
|
||||
A0 = input,69,G,-;
|
||||
DSACK1 = input,81,H,-;
|
||||
RW_000 = input,80,H,-;
|
||||
AS_000 = input,42,E,-;
|
||||
AMIGA_ADDR_ENABLE = input,33,D,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = input,34,D,-;
|
||||
A_23_ = input,85,H,-;
|
||||
FPU_SENSE = input,91,A,-;
|
||||
A1 = input,60,F,-;
|
||||
VMA = input,35,D,-;
|
||||
|
||||
[GROUP ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
|
||||
[SPACE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
VCC_GND = Cell;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = 8,H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
Import_source_constraint = Yes;
|
||||
Disable_warning_message = No;
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
||||
[INPUT REGISTERS]
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
Signal Name Cross Reference File
|
||||
|
||||
ispLEVER Classic 1.7.00.05.28.13
|
||||
|
||||
Design '68030_tk' created Fri Oct 10 22:40:03 2014
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
'/' Hierarchy Path Separator
|
||||
'@' Automatically Generated Node
|
||||
|
||||
|
||||
Short Name Hierarchical Name
|
||||
---------- -----------------
|
||||
|
||||
*** Shortened names not required for this design. ***
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,61 @@
|
|||
AS_030 b
|
||||
AS_000 b
|
||||
RW_000 b
|
||||
DS_030 b
|
||||
UDS_000 b
|
||||
LDS_000 b
|
||||
SIZE[1] b
|
||||
SIZE[0] b
|
||||
A[31] i
|
||||
A[30] i
|
||||
A[29] i
|
||||
A[28] i
|
||||
A[27] i
|
||||
A[26] i
|
||||
A[25] i
|
||||
A[24] i
|
||||
A[23] i
|
||||
A[22] i
|
||||
A[21] i
|
||||
A[20] i
|
||||
A[19] i
|
||||
A[18] i
|
||||
A[17] i
|
||||
A[16] i
|
||||
A0 b
|
||||
A1 i
|
||||
nEXP_SPACE i
|
||||
BERR b
|
||||
BG_030 i
|
||||
BG_000 o
|
||||
BGACK_030 o
|
||||
BGACK_000 i
|
||||
CLK_030 i
|
||||
CLK_000 i
|
||||
CLK_OSZI i
|
||||
CLK_DIV_OUT o
|
||||
CLK_EXP o
|
||||
FPU_CS o
|
||||
FPU_SENSE i
|
||||
IPL_030[2] o
|
||||
IPL_030[1] o
|
||||
IPL_030[0] o
|
||||
IPL[2] i
|
||||
IPL[1] i
|
||||
IPL[0] i
|
||||
DSACK1 b
|
||||
DTACK b
|
||||
AVEC o
|
||||
E o
|
||||
VPA i
|
||||
VMA o
|
||||
RST i
|
||||
RESET o
|
||||
RW b
|
||||
FC[1] i
|
||||
FC[0] i
|
||||
AMIGA_ADDR_ENABLE o
|
||||
AMIGA_BUS_DATA_DIR o
|
||||
AMIGA_BUS_ENABLE_LOW o
|
||||
AMIGA_BUS_ENABLE_HIGH o
|
||||
CIIN o
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Sun Oct 05 21:32:32 2014
|
||||
#-- Written on Fri Oct 10 22:39:56 2014
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Sun Oct 05 21:32:33 2014
|
||||
#Fri Oct 10 22:39:57 2014
|
||||
|
||||
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -16,6 +16,7 @@ Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentatio
|
|||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
|
||||
|
|
@ -46,7 +47,7 @@ State machine has 8 reachable states with original encodings of:
|
|||
111
|
||||
@END
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Oct 05 21:32:33 2014
|
||||
# Fri Oct 10 22:39:57 2014
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -70,17 +71,17 @@ original code -> new code
|
|||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFFSH 28 uses
|
||||
DFFRH 18 uses
|
||||
DFFSH 28 uses
|
||||
DFF 34 uses
|
||||
BI_DIR 13 uses
|
||||
IBUF 31 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 1 use
|
||||
AND2 231 uses
|
||||
INV 181 uses
|
||||
OR2 23 uses
|
||||
AND2 228 uses
|
||||
INV 189 uses
|
||||
XOR2 9 uses
|
||||
OR2 21 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -90,6 +91,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Oct 05 21:32:34 2014
|
||||
# Fri Oct 10 22:39:58 2014
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version G-2012.09LC-SP1
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Sun Oct 05 21:32:33 2014
|
||||
#-- Written on Fri Oct 10 22:39:56 2014
|
||||
|
||||
|
||||
#project files
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||
DIOEDA_ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||
DIOEDA_ActiveHDL=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||
DIOEDA_ActiveHDLPath=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||
DIOEDA_AppNotes=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Bin=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Config=C:\Program Files (x86)\ispLever\ispcpld\config
|
||||
DIOEDA_CONTEXT=ispLEVER CLASSIC
|
||||
DIOEDA_DSPPATH=C:\Program Files (x86)\ispLever\ispLeverDSP
|
||||
DIOEDA_EPICPATH=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_Examples=C:\Program Files (x86)\ispLever\examples
|
||||
DIOEDA_FPGABinPath=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_FPGAPath=C:\Program Files (x86)\ispLever\ispfpga
|
||||
DIOEDA_HDLExplorer=C:\Program Files (x86)\ispLever\hdle\win32
|
||||
DIOEDA_INI=C:\lsc_env
|
||||
DIOEDA_ispVM=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||
DIOEDA_ispVMSystem=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||
DIOEDA_License=C:\Program Files (x86)\ispLever\license
|
||||
DIOEDA_MachPath=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Manuals=C:\Program Files (x86)\ispLever\ispcpld\manuals
|
||||
DIOEDA_ModelSim=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||
DIOEDA_ModelsimPath=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||
DIOEDA_PDSPath=C:\Program Files (x86)\ispLever\ispcomp
|
||||
DIOEDA_Precision=C:\isptools\precision
|
||||
DIOEDA_PrecisionPath=C:\isptools\precision
|
||||
DIOEDA_ProductName=ispLEVER
|
||||
DIOEDA_ProductPrefix=SYN
|
||||
DIOEDA_ProductTitle=ispLEVER
|
||||
DIOEDA_ProductType=1.7.00.05.28.13_LS_HDL_BASE_PC_N
|
||||
DIOEDA_ProductVersion=1.7.00.05
|
||||
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.7
|
||||
DIOEDA_Root=C:\Program Files (x86)\ispLever\ispcpld
|
||||
DIOEDA_Spectrum=C:\isptools\spectrum
|
||||
DIOEDA_SpectrumPath=C:\isptools\spectrum
|
||||
DIOEDA_Synplify=C:\Program Files (x86)\ispLever\synpbase
|
||||
DIOEDA_SynplifyPath=C:\Program Files (x86)\ispLever\synpbase
|
||||
DIOEDA_Tutorial=C:\Program Files (x86)\ispLever\ispcpld\tutorial
|
||||
DIOPRODUCT=ispLEVER
|
||||
PATH=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
|
|
@ -17,17 +17,17 @@ original code -> new code
|
|||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFFSH 28 uses
|
||||
DFFRH 18 uses
|
||||
DFFSH 28 uses
|
||||
DFF 34 uses
|
||||
BI_DIR 13 uses
|
||||
IBUF 31 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 1 use
|
||||
AND2 231 uses
|
||||
INV 181 uses
|
||||
OR2 23 uses
|
||||
AND2 228 uses
|
||||
INV 189 uses
|
||||
XOR2 9 uses
|
||||
OR2 21 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -37,6 +37,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Oct 05 21:32:34 2014
|
||||
# Fri Oct 10 22:39:58 2014
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1412537553</data>
|
||||
<data type="timestamp">1412973597</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>96MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1412537554</data>
|
||||
<data type="timestamp">1412973598</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
Synopsys, Inc.
|
||||
Version G-2012.09LC-SP1
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Sun Oct 05 21:32:33 2014
|
||||
Written on Fri Oct 10 22:39:57 2014
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412537547
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412973591
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412537547
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412973591
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
Binary file not shown.
Loading…
Reference in New Issue