68030tk/Logic/68030_tk.rpt

|--------------------------------------------|
|- ispLEVER Fitter Report File              -|
|- Version 1.8.00.04.29.14                       -|
|- (c)Copyright, Lattice Semiconductor 2002 -|
|--------------------------------------------|




Project_Summary
~~~~~~~~~~~~~~~

Project Name :          68030_tk
Project Path :          C:\Users\Matze\Documents\GitHub\68030tk\Logic
Project Fitted on :     Thu Jul 09 18:49:07 2015

Device :                M4A5-128/64
Package :               100TQFP
Speed :                 -10
Partnumber :            M4A5-128/64-10VC
Source Format :         Pure_VHDL


// Project '68030_tk' was Fitted Successfully! //


Compilation_Times
~~~~~~~~~~~~~~~~~
Reading/DRC                                   0 sec
Partition                                     0 sec
Place                                         0 sec
Route                                         0 sec
Jedec/Report generation                       0 sec
                                         --------
Fitter                                   00:00:00


Design_Summary
~~~~~~~~~~~~~~
  Total Input Pins :                 28
  Total Output Pins :                18
  Total Bidir I/O Pins :             11
  Total Flip-Flops :                 83
  Total Product Terms :             252
  Total Reserved Pins :               0
  Total Reserved Blocks :             0


Device_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
                                 Total
                               Available  Used  Available  Utilization
Dedicated Pins
  Input-Only Pins                 2        2      0    -->   100%
  Clock/Input Pins                4        4      0    -->   100%
I/O Pins                         64       51     13    -->    79%
Logic Macrocells                128      101     27    -->    78%
  Input Registers                64        0     64    -->     0%
  Unusable Macrocells            ..        0     ..

CSM Outputs/Total Block Inputs  264      228     36    -->    86%
Logical Product Terms           640      253    387    -->    39%
Product Term Clusters           128       58     70    -->    45%


Blocks_Resource_Summary
~~~~~~~~~~~~~~~~~~~~~~~
                                                                  # of PT  
                   I/O    Inp    Macrocells   Macrocells   logic  clusters 
          Fanin    Pins   Reg   Used Unusable  available    PTs   available  Pwr
---------------------------------------------------------------------------------
Maximum     33      8      8     --     --         16       80       16       -
---------------------------------------------------------------------------------
Block  A    30      6      0     16      0          0       47        5       Lo 
Block  B    29      8      0     16      0          0       62        1       Lo 
Block  C    28      7      0      9      0          7       20       11       Lo 
Block  D    28      8      0     16      0          0       28       10       Lo 
Block  E    27      4      0      7      0          9        8       15       Lo 
Block  F    28      5      0     11      0          5       43        5       Lo 
Block  G    27      7      0     16      0          0       29        9       Lo 
Block  H    31      6      0     10      0          6       16       13       Lo 
---------------------------------------------------------------------------------

<Note> Four rightmost columns above reflect last status of the placement process.
<Note> Pwr (Power) : Hi = High
                     Lo = Low.


Optimizer_and_Fitter_Options
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Pin Assignment :                       Yes
Group Assignment :                     No
Pin Reservation :                      No (1)
Block Reservation :                    No

@Ignore_Project_Constraints :
  Pin Assignments :                    No
      Keep Block Assignment            --
      Keep Segment Assignment          --
  Group Assignments :                  No
  Macrocell Assignment :               No
      Keep Block Assignment            --
      Keep Segment Assignment          --

@Backannotate_Project_Constraints
  Pin Assignments :                    No
  Pin And Block Assignments :          No
  Pin, Macrocell and Block :           No

@Timing_Constraints :                  No

@Global_Project_Optimization :
  Balanced Partitioning :              Yes
  Spread Placement :                   Yes

  Note :
    Pack Design :
       Balanced Partitioning = No
       Spread Placement      = No
    Spread Design :
       Balanced Partitioning = Yes
       Spread Placement      = Yes

@Logic_Synthesis :
  Logic Reduction :                    Yes
  Node Collapsing :                    Yes
  D/T Synthesis :                      Yes
  Clock Optimization :                 No
  Input Register Optimization :        Yes
  XOR Synthesis :                      Yes
  Max. P-Term for Collapsing :         16
  Max. P-Term for Splitting :          16
  Max. Equation Fanin :                32
  Keep Xor :                           Yes

@Utilization_options
  Max. % of macrocells used :          100
  Max. % of block inputs used :        100
  Max. % of segment lines used :       ---
  Max. % of macrocells used :          ---


@Import_Source_Constraint_Option       No

@Zero_Hold_Time                        Yes

@Pull_up                               Yes

@User_Signature                        #H0

@Output_Slew_Rate                      Default = Slow(2)

@Power                                 Default = High(2)


Device Options:
<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
           follow the drive level set for the Global Configure Unused I/O Option.
<Note> 2 : For user-specified constraints on individual signals, refer to the Output, 
           Bidir and Burried Signal Lists.




Pinout_Listing
~~~~~~~~~~~~~~
      | Pin  |Blk |Assigned|
Pin No| Type |Pad |Pin     | Signal name
---------------------------------------------------------------
    1 |  GND |    |        |
    2 | JTAG |    |        |
    3 |  I_O | B7 |   *    |RESET
4     |  I_O | B6 |   *    |A_31_
5     |  I_O | B5 |   *    |A_30_
6     |  I_O | B4 |   *    |A_29_
7     |  I_O | B3 |   *    |IPL_030_1_
8     |  I_O | B2 |   *    |IPL_030_0_
9     |  I_O | B1 |   *    |IPL_030_2_
10    |  I_O | B0 |   *    |CLK_EXP
11    | CkIn |    |   *    |CLK_000
12    |  Vcc |    |        |
13    |  GND |    |        |
14    | CkIn |    |   *    |nEXP_SPACE
15    |  I_O | C0 |   *    |A_28_
16    |  I_O | C1 |   *    |A_27_
17    |  I_O | C2 |   *    |A_26_
18    |  I_O | C3 |   *    |A_25_
19    |  I_O | C4 |   *    |A_24_
20    |  I_O | C5 |   *    |AMIGA_BUS_ENABLE_LOW
21    |  I_O | C6 |   *    |BG_030
22    |  I_O | C7 |        |
23    | JTAG |    |        |
24    | JTAG |    |        |
25    |  GND |    |        |
26    |  GND |    |        |
27    |  GND |    |        |
28    |  I_O | D7 |   *    |BGACK_000
29    |  I_O | D6 |   *    |BG_000
30    |  I_O | D5 |   *    |DTACK
31    |  I_O | D4 |   *    |LDS_000
32    |  I_O | D3 |   *    |UDS_000
33    |  I_O | D2 |   *    |AMIGA_ADDR_ENABLE
34    |  I_O | D1 |   *    |AMIGA_BUS_ENABLE_HIGH
35    |  I_O | D0 |   *    |VMA
36    |  Inp |    |   *    |VPA
37    |  Vcc |    |        |
38    |  GND |    |        |
39    |  GND |    |        |
40    |  Vcc |    |        |
41    |  I_O | E0 |   *    |BERR
42    |  I_O | E1 |   *    |AS_000
43    |  I_O | E2 |        |
44    |  I_O | E3 |        |
45    |  I_O | E4 |        |
46    |  I_O | E5 |        |
47    |  I_O | E6 |   *    |CIIN
48    |  I_O | E7 |   *    |AMIGA_BUS_DATA_DIR
49    |  GND |    |        |
50    |  GND |    |        |
51    |  GND |    |        |
52    | JTAG |    |        |
53    |  I_O | F7 |        |
54    |  I_O | F6 |        |
55    |  I_O | F5 |        |
56    |  I_O | F4 |   *    |IPL_1_
57    |  I_O | F3 |   *    |FC_0_
58    |  I_O | F2 |   *    |FC_1_
59    |  I_O | F1 |   *    |A_17_
60    |  I_O | F0 |   *    |A1
61    | CkIn |    |   *    |CLK_OSZI
62    |  Vcc |    |        |
63    |  GND |    |        |
64    | CkIn |    |   *    |CLK_030
65    |  I_O | G0 |   *    |CLK_DIV_OUT
66    |  I_O | G1 |   *    |E
67    |  I_O | G2 |   *    |IPL_0_
68    |  I_O | G3 |   *    |IPL_2_
69    |  I_O | G4 |   *    |A0
70    |  I_O | G5 |   *    |SIZE_0_
71    |  I_O | G6 |   *    |RW
72    |  I_O | G7 |        |
73    | JTAG |    |        |
74    | JTAG |    |        |
75    |  GND |    |        |
76    |  GND |    |        |
77    |  GND |    |        |
78    |  I_O | H7 |   *    |FPU_CS
79    |  I_O | H6 |   *    |SIZE_1_
80    |  I_O | H5 |   *    |RW_000
81    |  I_O | H4 |   *    |DSACK1
82    |  I_O | H3 |   *    |AS_030
83    |  I_O | H2 |   *    |BGACK_030
84    |  I_O | H1 |        |
85    |  I_O | H0 |        |
86    |  Inp |    |   *    |RST
87    |  Vcc |    |        |
88    |  GND |    |        |
89    |  GND |    |        |
90    |  Vcc |    |        |
91    |  I_O | A0 |   *    |FPU_SENSE
92    |  I_O | A1 |   *    |AVEC
93    |  I_O | A2 |        |
94    |  I_O | A3 |        |
95    |  I_O | A4 |   *    |A_18_
96    |  I_O | A5 |   *    |A_16_
97    |  I_O | A6 |   *    |A_19_
98    |  I_O | A7 |   *    |DS_030
99    |  GND |    |        |
100   |  GND |    |        |

---------------------------------------------------------------------------

<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
<Note> Pin Type : 
           CkIn : Dedicated input or clock pin 
           CLK  : Dedicated clock pin
           INP  : Dedicated input pin
           JTAG : JTAG Control and test pin
           NC   : No connected



Input_Signal_List
~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Input 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 60  F   .  I/O          ------G-  Low Slow      A1   
 96  A   .  I/O          --C-E--H  Low Slow      A_16_   
 59  F   .  I/O          --C-E--H  Low Slow      A_17_   
 95  A   .  I/O          --C-E--H  Low Slow      A_18_   
 97  A   .  I/O          --C-E--H  Low Slow      A_19_   
 19  C   .  I/O          ----E---  Low Slow      A_24_   
 18  C   .  I/O          ----E---  Low Slow      A_25_   
 17  C   .  I/O          ----E---  Low Slow      A_26_   
 16  C   .  I/O          ----E---  Low Slow      A_27_   
 15  C   .  I/O          ----E---  Low Slow      A_28_   
  6  B   .  I/O          ----E---  Low Slow      A_29_   
  5  B   .  I/O          ----E---  Low Slow      A_30_   
  4  B   .  I/O          ----E---  Low Slow      A_31_   
 28  D   .  I/O          ----E--H  Low Slow      BGACK_000   
 21  C   .  I/O          ---D----  Low Slow      BG_030   
 30  D   .  I/O          ---D----  Low Slow      DTACK   
 57  F   .  I/O          --C-E--H  Low Slow      FC_0_   
 58  F   .  I/O          --C-E--H  Low Slow      FC_1_   
 91  A   .  I/O          ----E--H  Low Slow      FPU_SENSE   
 67  G   .  I/O          -B------  Low Slow      IPL_0_   
 56  F   .  I/O          -BC-----  Low Slow      IPL_1_   
 68  G   .  I/O          -B------  Low Slow      IPL_2_   
 11  .   . Ck/I          ------G-   -  Slow      CLK_000   
 14  .   . Ck/I          ------G-   -  Slow      nEXP_SPACE   
 36  .   .  Ded          -----F--   -  Slow      VPA   
 61  .   . Ck/I          ABCDEFGH   -  Slow      CLK_OSZI   
 64  .   . Ck/I          AB-----H   -  Slow      CLK_030   
 86  .   .  Ded          ABCD-FGH   -  Slow      RST   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Output_Signal_List
~~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Output 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 33  D   1  COM          --------  Low Fast      AMIGA_ADDR_ENABLE   
 48  E   2  COM          --------  Low Fast      AMIGA_BUS_DATA_DIR   
 34  D   2  COM          --------  Low Fast      AMIGA_BUS_ENABLE_HIGH   
 20  C   1  COM          --------  Low Fast      AMIGA_BUS_ENABLE_LOW   
 92  A   1  COM          --------  Low Slow      AVEC   
 83  H   2  DFF  * *     --------  Low Slow      BGACK_030   
 29  D   2  DFF  * *     --------  Low Slow      BG_000   
 47  E   1  COM          --------  Low Slow      CIIN   
 65  G   1  COM          --------  Low Fast      CLK_DIV_OUT   
 10  B   1  COM          --------  Low Fast      CLK_EXP   
 81  H   4  DFF  * *     --------  Low Slow      DSACK1   
 66  G   5  DFF  * *     --------  Low Slow      E   
 78  H   1  COM          --------  Low Fast      FPU_CS   
  8  B  10  DFF  * *     --------  Low Slow      IPL_030_0_   
  7  B  10  DFF  * *     --------  Low Slow      IPL_030_1_   
  9  B  10  DFF  * *     --------  Low Slow      IPL_030_2_   
  3  B   2  DFF  * *     --------  Low Slow      RESET   
 35  D   3  TFF  * *     --------  Low Slow      VMA   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Bidir_Signal_List
~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Bidir 
Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 69  G   3  DFF  * *     -B---F--  Low Slow      A0   
 42  E   1  COM          A---E--H  Low Slow      AS_000   
 82  H   1  COM          ----E--H  Low Slow      AS_030   
 41  E   1  COM          --C--F-H  Low Slow      BERR   
 98  A   1  COM          ---D----  Low Slow      DS_030   
 31  D   1  COM          A-----G-  Low Slow      LDS_000   
 71  G   2  DFF  * *     --C----H  Low Slow      RW   
 80  H   3  DFF  * *     A---E-G-  Low Slow      RW_000   
 70  G   1  COM          -B------  Low Slow      SIZE_0_   
 79  H   1  COM          -B------  Low Slow      SIZE_1_   
 32  D   1  COM          A-----G-  Low Slow      UDS_000   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low



Buried_Signal_List
~~~~~~~~~~~~~~~~~~
                 P R
            Pin  r e O   Node 
#Mc Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
----------------------------------------------------------------------
 D7  D   1  DFF  * *     A-------  Low Slow      CLK_000_N_SYNC_0_   
 H2  H   1  DFF  * *     -------H  Low Slow      CLK_000_N_SYNC_10_   
 H6  H   1  DFF  * *     ------G-  Low Slow      CLK_000_N_SYNC_11_   
 A15  A   1  DFF  * *     A-------  Low Slow      CLK_000_N_SYNC_1_   
 A11  A   1  DFF  * *     A-------  Low Slow      CLK_000_N_SYNC_2_   
 A7  A   1  DFF  * *     ---D----  Low Slow      CLK_000_N_SYNC_3_   
 D3  D   1  DFF  * *     A-------  Low Slow      CLK_000_N_SYNC_4_   
 A3  A   1  DFF  * *     ---D----  Low Slow      CLK_000_N_SYNC_5_   
 D14  D   1  DFF  * *     ----E---  Low Slow      CLK_000_N_SYNC_6_   
 E8  E   1  DFF  * *     A-------  Low Slow      CLK_000_N_SYNC_7_   
 A14  A   1  DFF  * *     ------G-  Low Slow      CLK_000_N_SYNC_8_   
 G3  G   1  DFF  * *     -------H  Low Slow      CLK_000_N_SYNC_9_   
 D11  D   1  DFF  * *     ------G-  Low Slow      CLK_000_P_SYNC_0_   
 G11  G   1  DFF  * *     -B------  Low Slow      CLK_000_P_SYNC_1_   
 B3  B   1  DFF  * *     --C-----  Low Slow      CLK_000_P_SYNC_2_   
 C9  C   1  DFF  * *     -B------  Low Slow      CLK_000_P_SYNC_3_   
 B4  B   1  DFF  * *     ----E---  Low Slow      CLK_000_P_SYNC_4_   
 E9  E   1  DFF  * *     ----E---  Low Slow      CLK_000_P_SYNC_5_   
 E5  E   1  DFF  * *     ------G-  Low Slow      CLK_000_P_SYNC_6_   
 G7  G   1  DFF  * *     --C-----  Low Slow      CLK_000_P_SYNC_7_   
 C5  C   1  DFF  * *     --C-----  Low Slow      CLK_000_P_SYNC_8_   
 C2  C   1  DFF  * *     ---D----  Low Slow      CLK_000_P_SYNC_9_   
 A10  A   2  DFF  * *     A-------  Low Slow      CYCLE_DMA_0_   
 A6  A   3  DFF  * *     A-------  Low Slow      CYCLE_DMA_1_   
 B7  B   1  DFF  * *     -B------  Low Slow      IPL_D0_0_   
 C13  C   1  DFF  * *     -B------  Low Slow      IPL_D0_1_   
 B13  B   1  DFF  * *     -B------  Low Slow      IPL_D0_2_   
 F6  F   4  COM          -----F--  Low Slow      N_165   
 G8  G   3  DFF  * *     ------G-  Low  -        RN_A0   --> A0
 H4  H   2  DFF  * *     A-CDE-GH  Low  -        RN_BGACK_030   --> BGACK_030
 D1  D   2  DFF  * *     ---D----  Low  -        RN_BG_000   --> BG_000
 H9  H   4  DFF  * *     -------H  Low  -        RN_DSACK1   --> DSACK1
 G4  G   5  DFF  * *     ---D-FG-  Low  -        RN_E   --> E
 B8  B  10  DFF  * *     -B------  Low  -        RN_IPL_030_0_   --> IPL_030_0_
 B6  B  10  DFF  * *     -B------  Low  -        RN_IPL_030_1_   --> IPL_030_1_
 B2  B  10  DFF  * *     -B------  Low  -        RN_IPL_030_2_   --> IPL_030_2_
 B14  B   2  DFF  * *     AB-DE-GH  Low  -        RN_RESET   --> RESET
 G0  G   2  DFF  * *     ------G-  Low  -        RN_RW   --> RW
 H0  H   3  DFF  * *     -------H  Low  -        RN_RW_000   --> RW_000
 D0  D   3  TFF  * *     ---D-F--  Low  -        RN_VMA   --> VMA
 B10  B   3  DFF  * *     AB------  Low Slow      RST_DLY_0_   
 A1  A   4  DFF  * *     AB------  Low Slow      RST_DLY_1_   
 B5  B   5  DFF  * *     AB------  Low Slow      RST_DLY_2_   
 B0  B   6  DFF  * *     AB------  Low Slow      RST_DLY_3_   
 B12  B   2  TFF  * *     AB------  Low Slow      RST_DLY_4_   
 A12  A   4  TFF  * *     AB------  Low Slow      RST_DLY_5_   
 B11  B   3  TFF  * *     AB------  Low Slow      RST_DLY_6_   
 A5  A   2  DFF  * *     AB------  Low Slow      RST_DLY_7_   
 G6  G   3  DFF  * *     ------GH  Low Slow      SIZE_DMA_0_   
 G2  G   3  DFF  * *     ------GH  Low Slow      SIZE_DMA_1_   
 F9  F   2  DFF  * *     -----F-H  Low Slow      SM_AMIGA_0_   
 F1  F   3  DFF  * *     -----F-H  Low Slow      SM_AMIGA_1_   
 F2  F   4  DFF  * *     -----F--  Low Slow      SM_AMIGA_2_   
 F12  F   5  TFF  * *     --C--F--  Low Slow      SM_AMIGA_3_   
 F10  F   3  DFF  * *     -----F--  Low Slow      SM_AMIGA_4_   
 F4  F   3  DFF  * *     --C--F-H  Low Slow      SM_AMIGA_5_   
 C4  C   3  DFF  * *     -BC--F--  Low Slow      SM_AMIGA_6_   
 F0  F  14  DFF  * *     --CD---H  Low Slow      SM_AMIGA_i_7_   
 D6  D   2  DFF  * *     ---D-FG-  Low Slow      cpu_est_0_   
 D13  D   5  DFF  * *     ---D-FG-  Low Slow      cpu_est_1_   
 D2  D   4  DFF  * *     ---D-FG-  Low Slow      cpu_est_2_   
 G10  G   2  DFF  * *     ---D--G-  Low Slow      inst_AMIGA_BUS_ENABLE_DMA_HIGH   
 G14  G   2  DFF  * *     --C---G-  Low Slow      inst_AMIGA_BUS_ENABLE_DMA_LOW   
 A8  A   7  DFF  * *     A------H  Low Slow      inst_AS_000_DMA   
 C1  C   2  DFF  * *     --C-E---  Low Slow      inst_AS_000_INT   
 C8  C   7  DFF  * *     --C--F--  Low Slow      inst_AS_030_000_SYNC   
 H5  H   1  DFF  * *     --CDE--H  Low Slow      inst_AS_030_D0   
 H13  H   1  DFF  * *     --C---G-  Low Slow      inst_BGACK_030_INT_D   
 G13  G   1  DFF  * *     --CD-F--  Low Slow      inst_CLK_000_D0   
 F8  F   1  DFF  * *     --CD-F--  Low Slow      inst_CLK_000_D1   
 G9  G   1  DFF  * *     AB-D-F--  Low Slow      inst_CLK_000_NE   
 B15  B   1  DFF  * *     ---D-FG-  Low Slow      inst_CLK_000_NE_D0   
 D9  D   1  DFF  * *     A-CD-F-H  Low Slow      inst_CLK_000_PE   
 A2  A   8  DFF  * *     A-------  Low Slow      inst_CLK_030_H   
 A9  A   1  DFF  * *     A-----G-  Low Slow      inst_CLK_OUT_PRE_50   
 G15  G   1  DFF  * *     -------H  Low Slow      inst_CLK_OUT_PRE_D   
 A13  A   9  DFF  * *     A-------  Low Slow      inst_DS_000_DMA   
 C12  C   3  DFF  * *     --CD----  Low Slow      inst_DS_000_ENABLE   
 D10  D   1  DFF  * *     -B---F--  Low Slow      inst_DS_030_D0   
 D15  D   1  DFF  * *     -----F--  Low Slow      inst_DTACK_D0   
 B9  B   4  DFF  * *     -B-D----  Low Slow      inst_LDS_000_INT   
 F5  F   3  DFF  * *     ---D-F--  Low Slow      inst_UDS_000_INT   
 F13  F   1  DFF  * *     ---D-F--  Low Slow      inst_VPA_D   
 G5  G   1  DFF  * *     A-CDEFGH  Low Slow      inst_nEXP_SPACE_D0reg   
----------------------------------------------------------------------

<Note> Power : Hi = High
               MH = Medium High
               ML = Medium Low
               Lo = Low




Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source  :    Fanout List
-----------------------------------------------------------------------------
    SIZE_0_{ H}:inst_LDS_000_INT{ B}
      A_30_{ C}:           CIIN{ E}
    SIZE_1_{ I}:inst_LDS_000_INT{ B}
      A_29_{ C}:           CIIN{ E}
      A_28_{ D}:           CIIN{ E}
      A_31_{ C}:           CIIN{ E}
      A_27_{ D}:           CIIN{ E}
      A_26_{ D}:           CIIN{ E}
      A_25_{ D}:           CIIN{ E}
      A_24_{ D}:           CIIN{ E}
     IPL_2_{ H}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
               :      IPL_D0_2_{ B}
      FC_1_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
     AS_030{ I}:         AS_000{ E}           BERR{ E}         FPU_CS{ H}
               : inst_AS_030_D0{ H}
     AS_000{ F}:         AS_030{ H}         DS_030{ A}AMIGA_BUS_DATA_DIR{ E}
               :inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}   CYCLE_DMA_0_{ A}
               :   CYCLE_DMA_1_{ A} inst_CLK_030_H{ A}
      A_19_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
      A_18_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
     DS_030{ B}:        UDS_000{ D}        LDS_000{ D} inst_DS_030_D0{ D}
      A_17_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
    UDS_000{ E}:             A0{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
               :    SIZE_DMA_0_{ G}    SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
      A_16_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
    LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}    SIZE_DMA_0_{ G}
               :    SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
         A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
 nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ G}
       BERR{ F}:         DSACK1{ H}inst_AS_000_INT{ C}    SM_AMIGA_5_{ F}
               :inst_AS_030_000_SYNC{ C}    SM_AMIGA_3_{ F}    SM_AMIGA_0_{ F}
               :    SM_AMIGA_6_{ C}    SM_AMIGA_1_{ F}    SM_AMIGA_4_{ F}
               :    SM_AMIGA_2_{ F}inst_DS_000_ENABLE{ C}  SM_AMIGA_i_7_{ F}
     BG_030{ D}:         BG_000{ D}
  BGACK_000{ E}:           BERR{ E}         FPU_CS{ H}      BGACK_030{ H}
    CLK_030{. }:        CLK_EXP{ B}         DSACK1{ H}inst_AS_000_DMA{ A}
               :inst_DS_000_DMA{ A} inst_CLK_030_H{ A}
    CLK_000{. }:inst_CLK_000_D0{ G}
  FPU_SENSE{ B}:           BERR{ E}         FPU_CS{ H}
     IPL_1_{ G}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
               :      IPL_D0_1_{ C}
      DTACK{ E}:  inst_DTACK_D0{ D}
     IPL_0_{ H}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
               :      IPL_D0_0_{ B}
      FC_0_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
        VPA{. }:     inst_VPA_D{ F}
        RST{. }:     IPL_030_2_{ B}         RW_000{ H}             A0{ G}
               :         BG_000{ D}      BGACK_030{ H}     IPL_030_1_{ B}
               :     IPL_030_0_{ B}         DSACK1{ H}            VMA{ D}
               :          RESET{ B}             RW{ G}inst_AS_000_INT{ C}
               :    SM_AMIGA_5_{ F}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G} inst_AS_030_D0{ H}
               :inst_nEXP_SPACE_D0reg{ G} inst_DS_030_D0{ D}inst_AS_030_000_SYNC{ C}
               :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
               :   CYCLE_DMA_0_{ A}   CYCLE_DMA_1_{ A}    SIZE_DMA_0_{ G}
               :    SIZE_DMA_1_{ G}     inst_VPA_D{ F}inst_UDS_000_INT{ F}
               :inst_LDS_000_INT{ B}  inst_DTACK_D0{ D}      IPL_D0_0_{ B}
               :      IPL_D0_1_{ C}      IPL_D0_2_{ B}    SM_AMIGA_3_{ F}
               :    SM_AMIGA_0_{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}    SM_AMIGA_6_{ C}
               :     RST_DLY_0_{ B}     RST_DLY_1_{ A}     RST_DLY_2_{ B}
               :     RST_DLY_3_{ B}     RST_DLY_4_{ B}     RST_DLY_5_{ A}
               :     RST_DLY_6_{ B}     RST_DLY_7_{ A} inst_CLK_030_H{ A}
               :    SM_AMIGA_1_{ F}    SM_AMIGA_4_{ F}    SM_AMIGA_2_{ F}
               :inst_DS_000_ENABLE{ C}  SM_AMIGA_i_7_{ F}
RN_IPL_030_2_{ C}:     IPL_030_2_{ B}
     RW_000{ I}:AMIGA_BUS_DATA_DIR{ E}             RW{ G}inst_DS_000_DMA{ A}
  RN_RW_000{ I}:         RW_000{ H}
         A0{ H}:inst_UDS_000_INT{ F}inst_LDS_000_INT{ B}
      RN_A0{ H}:             A0{ G}
  RN_BG_000{ E}:         BG_000{ D}
RN_BGACK_030{ I}:        SIZE_0_{ G}        SIZE_1_{ H}         AS_030{ H}
               :         AS_000{ E}         DS_030{ A}        UDS_000{ D}
               :        LDS_000{ D}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}
               :AMIGA_BUS_ENABLE_HIGH{ D}         RW_000{ H}             A0{ G}
               :      BGACK_030{ H}             RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}
               :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}
               :inst_DS_000_DMA{ A}   CYCLE_DMA_0_{ A}   CYCLE_DMA_1_{ A}
               :    SIZE_DMA_0_{ G}    SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
               : inst_CLK_030_H{ A}
RN_IPL_030_1_{ C}:     IPL_030_1_{ B}
RN_IPL_030_0_{ C}:     IPL_030_0_{ B}
  RN_DSACK1{ I}:         DSACK1{ H}
       RN_E{ H}:              E{ G}            VMA{ D}     cpu_est_1_{ D}
               :     cpu_est_2_{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
     RN_VMA{ E}:            VMA{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
   RN_RESET{ C}:         AS_030{ H}         AS_000{ E}         DS_030{ A}
               :        UDS_000{ D}        LDS_000{ D}         RW_000{ H}
               :             A0{ G}          RESET{ B}             RW{ G}
         RW{ H}:         RW_000{ H}inst_DS_000_ENABLE{ C}
      RN_RW{ H}:             RW{ G}
      N_165{ G}:  SM_AMIGA_i_7_{ F}
 cpu_est_0_{ E}:              E{ G}            VMA{ D}     cpu_est_0_{ D}
               :     cpu_est_1_{ D}     cpu_est_2_{ D}    SM_AMIGA_3_{ F}
               :    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
 cpu_est_1_{ E}:              E{ G}            VMA{ D}     cpu_est_1_{ D}
               :     cpu_est_2_{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
inst_AS_000_INT{ D}:         AS_000{ E}inst_AS_000_INT{ C}
SM_AMIGA_5_{ G}:         RW_000{ H}          N_165{ F}inst_AS_000_INT{ C}
               :    SM_AMIGA_5_{ F}    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
               :  SM_AMIGA_i_7_{ F}
inst_AMIGA_BUS_ENABLE_DMA_LOW{ H}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}
inst_AS_030_D0{ I}:           CIIN{ E}         BG_000{ D}         DSACK1{ H}
               :inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ C}
inst_nEXP_SPACE_D0reg{ H}:        SIZE_0_{ G}        SIZE_1_{ H}         AS_030{ H}
               :         DS_030{ A}AMIGA_BUS_DATA_DIR{ E}           CIIN{ E}
               :             A0{ G}         BG_000{ D}         DSACK1{ H}
               :          N_165{ F}inst_AS_030_000_SYNC{ C}    SM_AMIGA_6_{ C}
inst_DS_030_D0{ E}:inst_UDS_000_INT{ F}inst_LDS_000_INT{ B}
inst_AS_030_000_SYNC{ D}:          N_165{ F}inst_AS_030_000_SYNC{ C}    SM_AMIGA_6_{ C}
inst_BGACK_030_INT_D{ I}:             A0{ G}             RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ G}
               :inst_AS_030_000_SYNC{ C}    SIZE_DMA_0_{ G}    SIZE_DMA_1_{ G}
               :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
inst_AS_000_DMA{ B}:         AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
               : inst_CLK_030_H{ A}
inst_DS_000_DMA{ B}:         DS_030{ A}inst_DS_000_DMA{ A}
CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}   CYCLE_DMA_0_{ A}
               :   CYCLE_DMA_1_{ A} inst_CLK_030_H{ A}
CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}   CYCLE_DMA_1_{ A}
               : inst_CLK_030_H{ A}
SIZE_DMA_0_{ H}:        SIZE_0_{ G}        SIZE_1_{ H}    SIZE_DMA_0_{ G}
SIZE_DMA_1_{ H}:        SIZE_0_{ G}        SIZE_1_{ H}    SIZE_DMA_1_{ G}
 inst_VPA_D{ G}:            VMA{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
inst_UDS_000_INT{ G}:        UDS_000{ D}inst_UDS_000_INT{ F}
inst_LDS_000_INT{ C}:        LDS_000{ D}inst_LDS_000_INT{ B}
inst_CLK_OUT_PRE_D{ H}:         DSACK1{ H}
inst_DTACK_D0{ E}:    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
inst_CLK_OUT_PRE_50{ B}:inst_CLK_OUT_PRE_D{ G}inst_CLK_OUT_PRE_50{ A}
inst_CLK_000_D1{ G}:          N_165{ F}    SM_AMIGA_6_{ C}CLK_000_P_SYNC_0_{ D}
               :CLK_000_N_SYNC_0_{ D}
inst_CLK_000_D0{ H}:         BG_000{ D}          N_165{ F}inst_CLK_000_D1{ F}
               :    SM_AMIGA_6_{ C}CLK_000_P_SYNC_0_{ D}CLK_000_N_SYNC_0_{ D}
inst_CLK_000_PE{ E}:         RW_000{ H}      BGACK_030{ H}            VMA{ D}
               :    SM_AMIGA_5_{ F}   CYCLE_DMA_0_{ A}   CYCLE_DMA_1_{ A}
               :    SM_AMIGA_3_{ F}    SM_AMIGA_0_{ F}    SM_AMIGA_6_{ C}
               :    SM_AMIGA_1_{ F}    SM_AMIGA_4_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
CLK_000_P_SYNC_9_{ D}:inst_CLK_000_PE{ D}
inst_CLK_000_NE{ H}:            VMA{ D}          RESET{ B}    SM_AMIGA_5_{ F}
               :inst_CLK_000_NE_D0{ B}    SM_AMIGA_0_{ F}     RST_DLY_0_{ B}
               :     RST_DLY_1_{ A}     RST_DLY_2_{ B}     RST_DLY_3_{ B}
               :     RST_DLY_4_{ B}     RST_DLY_5_{ A}     RST_DLY_6_{ B}
               :     RST_DLY_7_{ A}    SM_AMIGA_1_{ F}    SM_AMIGA_4_{ F}
               :  SM_AMIGA_i_7_{ F}
CLK_000_N_SYNC_11_{ I}:inst_CLK_000_NE{ G}
 cpu_est_2_{ E}:              E{ G}            VMA{ D}     cpu_est_1_{ D}
               :     cpu_est_2_{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
  IPL_D0_0_{ C}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
  IPL_D0_1_{ D}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
  IPL_D0_2_{ C}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
SM_AMIGA_3_{ G}:          N_165{ F}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :inst_DS_000_ENABLE{ C}  SM_AMIGA_i_7_{ F}
inst_CLK_000_NE_D0{ C}:              E{ G}     cpu_est_0_{ D}     cpu_est_1_{ D}
               :     cpu_est_2_{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
SM_AMIGA_0_{ G}:         RW_000{ H}          N_165{ F}    SM_AMIGA_0_{ F}
               :  SM_AMIGA_i_7_{ F}
inst_AMIGA_BUS_ENABLE_DMA_HIGH{ H}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ G}
SM_AMIGA_6_{ D}:          N_165{ F}    SM_AMIGA_5_{ F}inst_UDS_000_INT{ F}
               :inst_LDS_000_INT{ B}    SM_AMIGA_6_{ C}  SM_AMIGA_i_7_{ F}
 RST_DLY_0_{ C}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
 RST_DLY_1_{ B}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
 RST_DLY_2_{ C}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
 RST_DLY_3_{ C}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
 RST_DLY_4_{ C}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
 RST_DLY_5_{ B}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
 RST_DLY_6_{ C}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
 RST_DLY_7_{ B}:          RESET{ B}     RST_DLY_0_{ B}     RST_DLY_1_{ A}
               :     RST_DLY_2_{ B}     RST_DLY_3_{ B}     RST_DLY_4_{ B}
               :     RST_DLY_5_{ A}     RST_DLY_6_{ B}     RST_DLY_7_{ A}
CLK_000_P_SYNC_0_{ E}:CLK_000_P_SYNC_1_{ G}
CLK_000_P_SYNC_1_{ H}:CLK_000_P_SYNC_2_{ B}
CLK_000_P_SYNC_2_{ C}:CLK_000_P_SYNC_3_{ C}
CLK_000_P_SYNC_3_{ D}:CLK_000_P_SYNC_4_{ B}
CLK_000_P_SYNC_4_{ C}:CLK_000_P_SYNC_5_{ E}
CLK_000_P_SYNC_5_{ F}:CLK_000_P_SYNC_6_{ E}
CLK_000_P_SYNC_6_{ F}:CLK_000_P_SYNC_7_{ G}
CLK_000_P_SYNC_7_{ H}:CLK_000_P_SYNC_8_{ C}
CLK_000_P_SYNC_8_{ D}:CLK_000_P_SYNC_9_{ C}
CLK_000_N_SYNC_0_{ E}:CLK_000_N_SYNC_1_{ A}
CLK_000_N_SYNC_1_{ B}:CLK_000_N_SYNC_2_{ A}
CLK_000_N_SYNC_2_{ B}:CLK_000_N_SYNC_3_{ A}
CLK_000_N_SYNC_3_{ B}:CLK_000_N_SYNC_4_{ D}
CLK_000_N_SYNC_4_{ E}:CLK_000_N_SYNC_5_{ A}
CLK_000_N_SYNC_5_{ B}:CLK_000_N_SYNC_6_{ D}
CLK_000_N_SYNC_6_{ E}:CLK_000_N_SYNC_7_{ E}
CLK_000_N_SYNC_7_{ F}:CLK_000_N_SYNC_8_{ A}
CLK_000_N_SYNC_8_{ B}:CLK_000_N_SYNC_9_{ G}
CLK_000_N_SYNC_9_{ H}:         DSACK1{ H}CLK_000_N_SYNC_10_{ H}
CLK_000_N_SYNC_10_{ I}:         DSACK1{ H}CLK_000_N_SYNC_11_{ H}
inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A}
SM_AMIGA_1_{ G}:         DSACK1{ H}          N_165{ F}    SM_AMIGA_0_{ F}
               :    SM_AMIGA_1_{ F}  SM_AMIGA_i_7_{ F}
SM_AMIGA_4_{ G}:          N_165{ F}    SM_AMIGA_3_{ F}    SM_AMIGA_4_{ F}
               :  SM_AMIGA_i_7_{ F}
SM_AMIGA_2_{ G}:          N_165{ F}    SM_AMIGA_1_{ F}    SM_AMIGA_2_{ F}
               :  SM_AMIGA_i_7_{ F}
inst_DS_000_ENABLE{ D}:        UDS_000{ D}        LDS_000{ D}inst_DS_000_ENABLE{ C}
SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D}         RW_000{ H}inst_AS_030_000_SYNC{ C}
               :    SM_AMIGA_6_{ C}
-----------------------------------------------------------------------------

<Note> {.} : Indicates block location of signal


Set_Reset_Summary
~~~~~~~~~~~~~~~~~

Block  A
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | DS_030
|     |     |     |     | AVEC
|  *  |  S  | BS  | BR  | inst_AS_000_DMA
|  *  |  S  | BS  | BR  | RST_DLY_5_
|  *  |  S  | BS  | BR  | RST_DLY_1_
|  *  |  S  | BS  | BR  | RST_DLY_7_
|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_50
|  *  |  S  | BS  | BR  | inst_DS_000_DMA
|  *  |  S  | BS  | BR  | inst_CLK_030_H
|  *  |  S  | BS  | BR  | CYCLE_DMA_1_
|  *  |  S  | BS  | BR  | CYCLE_DMA_0_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_8_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_5_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_3_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_2_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_1_
|     |     |     |     | A_19_
|     |     |     |     | A_16_
|     |     |     |     | A_18_
|     |     |     |     | FPU_SENSE


Block  B
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | RST_DLY_3_
|     |     |     |     | CLK_EXP
|  *  |  S  | BS  | BR  | IPL_030_2_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_2_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_4_
|  *  |  S  | BS  | BR  | RST_DLY_2_
|  *  |  S  | BS  | BR  | IPL_030_1_
|  *  |  S  | BS  | BR  | IPL_D0_0_
|  *  |  S  | BS  | BR  | IPL_030_0_
|  *  |  S  | BS  | BR  | inst_LDS_000_INT
|  *  |  S  | BS  | BR  | RST_DLY_0_
|  *  |  S  | BS  | BR  | RST_DLY_6_
|  *  |  S  | BS  | BR  | RST_DLY_4_
|  *  |  S  | BS  | BR  | RESET
|  *  |  S  | BS  | BR  | IPL_D0_2_
|  *  |  S  | BS  | BR  | inst_CLK_000_NE_D0
|  *  |  S  | BS  | BR  | RN_IPL_030_2_
|  *  |  S  | BS  | BR  | RN_IPL_030_1_
|  *  |  S  | BS  | BR  | RN_IPL_030_0_
|  *  |  S  | BS  | BR  | RN_RESET
|     |     |     |     | A_29_
|     |     |     |     | A_30_
|     |     |     |     | A_31_


Block  C
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | AMIGA_BUS_ENABLE_LOW
|  *  |  S  | BS  | BR  | SM_AMIGA_6_
|  *  |  S  | BS  | BR  | inst_AS_030_000_SYNC
|  *  |  S  | BS  | BR  | inst_DS_000_ENABLE
|  *  |  S  | BS  | BR  | inst_AS_000_INT
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_8_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_3_
|  *  |  S  | BS  | BR  | IPL_D0_1_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_9_
|     |     |     |     | BG_030
|     |     |     |     | A_24_
|     |     |     |     | A_25_
|     |     |     |     | A_26_
|     |     |     |     | A_27_
|     |     |     |     | A_28_


Block  D
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | UDS_000
|     |     |     |     | LDS_000
|  *  |  S  | BS  | BR  | VMA
|     |     |     |     | AMIGA_BUS_ENABLE_HIGH
|  *  |  S  | BS  | BR  | BG_000
|     |     |     |     | AMIGA_ADDR_ENABLE
|  *  |  S  | BS  | BR  | inst_CLK_000_PE
|  *  |  S  | BS  | BR  | cpu_est_1_
|  *  |  S  | BS  | BR  | cpu_est_2_
|  *  |  S  | BS  | BR  | cpu_est_0_
|  *  |  S  | BS  | BR  | RN_VMA
|  *  |  S  | BS  | BR  | inst_DS_030_D0
|  *  |  S  | BS  | BR  | RN_BG_000
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_6_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_4_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_0_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_0_
|  *  |  S  | BS  | BR  | inst_DTACK_D0
|     |     |     |     | BGACK_000
|     |     |     |     | DTACK


Block  E
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|     |     |     |     | AS_000
|     |     |     |     | BERR
|     |     |     |     | AMIGA_BUS_DATA_DIR
|     |     |     |     | CIIN
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_7_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_6_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_5_


Block  F
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | SM_AMIGA_i_7_
|  *  |  S  | BS  | BR  | SM_AMIGA_5_
|  *  |  S  | BS  | BR  | inst_CLK_000_D1
|  *  |  S  | BS  | BR  | SM_AMIGA_3_
|  *  |  S  | BS  | BR  | SM_AMIGA_1_
|  *  |  S  | BS  | BR  | inst_UDS_000_INT
|  *  |  S  | BS  | BR  | SM_AMIGA_0_
|  *  |  S  | BS  | BR  | inst_VPA_D
|  *  |  S  | BS  | BR  | SM_AMIGA_2_
|     |     |     |     | N_165
|  *  |  S  | BS  | BR  | SM_AMIGA_4_
|     |     |     |     | A_17_
|     |     |     |     | FC_1_
|     |     |     |     | FC_0_
|     |     |     |     | IPL_1_
|     |     |     |     | A1


Block  G
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | A0
|  *  |  S  | BS  | BR  | RW
|     |     |     |     | SIZE_0_
|  *  |  S  | BS  | BR  | E
|     |     |     |     | CLK_DIV_OUT
|  *  |  S  | BS  | BR  | inst_nEXP_SPACE_D0reg
|  *  |  S  | BS  | BR  | inst_CLK_000_NE
|  *  |  S  | BS  | BR  | RN_E
|  *  |  S  | BS  | BR  | inst_CLK_000_D0
|  *  |  S  | BS  | BR  | SIZE_DMA_1_
|  *  |  S  | BS  | BR  | SIZE_DMA_0_
|  *  |  S  | BS  | BR  | inst_AMIGA_BUS_ENABLE_DMA_HIGH
|  *  |  S  | BS  | BR  | inst_AMIGA_BUS_ENABLE_DMA_LOW
|  *  |  S  | BS  | BR  | RN_A0
|  *  |  S  | BS  | BR  | RN_RW
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_9_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_7_
|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_1_
|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_D
|     |     |     |     | IPL_2_
|     |     |     |     | IPL_0_


Block  H
block level set pt   : GND
block level reset pt : GND
Equations :
|     |     |Block|Block| Signal
| Reg |Mode |Set  |Reset| Name
+-----+-----+-----+-----+------------------------
|  *  |  S  | BS  | BR  | RW_000
|     |     |     |     | AS_030
|     |     |     |     | SIZE_1_
|  *  |  S  | BS  | BR  | DSACK1
|  *  |  S  | BS  | BR  | BGACK_030
|     |     |     |     | FPU_CS
|  *  |  S  | BS  | BR  | RN_BGACK_030
|  *  |  S  | BS  | BR  | inst_AS_030_D0
|  *  |  S  | BS  | BR  | inst_BGACK_030_INT_D
|  *  |  S  | BS  | BR  | RN_DSACK1
|  *  |  S  | BS  | BR  | RN_RW_000
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_10_
|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_11_


<Note> (S) means the macrocell is configured in synchronous mode
       i.e. it uses the block-level set and reset pt.
       (A) means the macrocell is configured in asynchronous mode
       i.e. it can have its independant set or reset pt.
       (BS) means the block-level set pt is selected.
       (BR) means the block-level reset pt is selected.




BLOCK_A_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx A0             RST        pin 86     mx A17      RST_DLY_6_    mcell  B11
mx A1      RST_DLY_4_    mcell  B12     mx A18      RST_DLY_7_     mcell  A5
mx A2      RST_DLY_0_    mcell  B10     mx A19inst_CLK_OUT_PRE_50     mcell  A9
mx A3 inst_AS_000_DMA     mcell  A8     mx A20         UDS_000        pin 32
mx A4         CLK_030        pin 64     mx A21CLK_000_N_SYNC_0_     mcell  D7
mx A5             ...           ...     mx A22CLK_000_N_SYNC_4_     mcell  D3
mx A6          RW_000        pin 80     mx A23    RN_BGACK_030     mcell  H4
mx A7CLK_000_N_SYNC_2_    mcell  A11     mx A24         LDS_000        pin 31
mx A8CLK_000_N_SYNC_7_     mcell  E8     mx A25  inst_CLK_030_H     mcell  A2
mx A9      RST_DLY_1_     mcell  A1     mx A26      RST_DLY_3_     mcell  B0
mx A10    CYCLE_DMA_1_     mcell  A6     mx A27 inst_CLK_000_NE     mcell  G9
mx A11             ...           ...     mx A28 inst_DS_000_DMA    mcell  A13
mx A12 inst_CLK_000_PE     mcell  D9     mx A29        RN_RESET    mcell  B14
mx A13CLK_000_N_SYNC_1_    mcell  A15     mx A30             ...           ...
mx A14    CYCLE_DMA_0_    mcell  A10     mx A31      RST_DLY_2_     mcell  B5
mx A15      RST_DLY_5_    mcell  A12     mx A32inst_nEXP_SPACE_D0reg     mcell  G5
mx A16          AS_000        pin 42
----------------------------------------------------------------------------


BLOCK_B_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx B0              A0        pin 69     mx B17         SIZE_0_        pin 70
mx B1      RST_DLY_4_    mcell  B12     mx B18   RN_IPL_030_2_     mcell  B2
mx B2  inst_DS_030_D0    mcell  D10     mx B19             ...           ...
mx B3CLK_000_P_SYNC_3_     mcell  C9     mx B20         SIZE_1_        pin 79
mx B4         CLK_030        pin 64     mx B21          IPL_1_        pin 56
mx B5             ...           ...     mx B22          IPL_2_        pin 68
mx B6inst_LDS_000_INT     mcell  B9     mx B23             ...           ...
mx B7      RST_DLY_6_    mcell  B11     mx B24             RST        pin 86
mx B8   RN_IPL_030_0_     mcell  B8     mx B25             ...           ...
mx B9      RST_DLY_1_     mcell  A1     mx B26      RST_DLY_3_     mcell  B0
mx B10       IPL_D0_2_    mcell  B13     mx B27 inst_CLK_000_NE     mcell  G9
mx B11   RN_IPL_030_1_     mcell  B6     mx B28      RST_DLY_7_     mcell  A5
mx B12      RST_DLY_0_    mcell  B10     mx B29        RN_RESET    mcell  B14
mx B13CLK_000_P_SYNC_1_    mcell  G11     mx B30       IPL_D0_1_    mcell  C13
mx B14     SM_AMIGA_6_     mcell  C4     mx B31      RST_DLY_2_     mcell  B5
mx B15      RST_DLY_5_    mcell  A12     mx B32       IPL_D0_0_     mcell  B7
mx B16          IPL_0_        pin 67
----------------------------------------------------------------------------


BLOCK_C_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx C0             RST        pin 86     mx C17     SM_AMIGA_3_    mcell  F12
mx C1            BERR        pin 41     mx C18             ...           ...
mx C2 inst_CLK_000_D1     mcell  F8     mx C19inst_BGACK_030_INT_D    mcell  H13
mx C3          IPL_1_        pin 56     mx C20    RN_BGACK_030     mcell  H4
mx C4inst_DS_000_ENABLE    mcell  C12     mx C21             ...           ...
mx C5CLK_000_P_SYNC_2_     mcell  B3     mx C22 inst_AS_000_INT     mcell  C1
mx C6           A_16_        pin 96     mx C23             ...           ...
mx C7 inst_CLK_000_PE     mcell  D9     mx C24           FC_0_        pin 57
mx C8           A_17_        pin 59     mx C25   SM_AMIGA_i_7_     mcell  F0
mx C9 inst_CLK_000_D0    mcell  G13     mx C26CLK_000_P_SYNC_7_     mcell  G7
mx C10inst_AMIGA_BUS_ENABLE_DMA_LOW    mcell  G14     mx C27           A_19_        pin 97
mx C11              RW        pin 71     mx C28             ...           ...
mx C12           FC_1_        pin 58     mx C29     SM_AMIGA_6_     mcell  C4
mx C13  inst_AS_030_D0     mcell  H5     mx C30             ...           ...
mx C14     SM_AMIGA_5_     mcell  F4     mx C31           A_18_        pin 95
mx C15CLK_000_P_SYNC_8_     mcell  C5     mx C32inst_nEXP_SPACE_D0reg     mcell  G5
mx C16inst_AS_030_000_SYNC     mcell  C8
----------------------------------------------------------------------------


BLOCK_D_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx D0             RST        pin 86     mx D17       RN_BG_000     mcell  D1
mx D1CLK_000_N_SYNC_3_     mcell  A7     mx D18          RN_VMA     mcell  D0
mx D2CLK_000_P_SYNC_9_     mcell  C2     mx D19             ...           ...
mx D3      cpu_est_2_     mcell  D2     mx D20 inst_CLK_000_D1     mcell  F8
mx D4inst_DS_000_ENABLE    mcell  C12     mx D21      cpu_est_1_    mcell  D13
mx D5          DS_030        pin 98     mx D22inst_nEXP_SPACE_D0reg     mcell  G5
mx D6CLK_000_N_SYNC_5_     mcell  A3     mx D23    RN_BGACK_030     mcell  H4
mx D7 inst_CLK_000_PE     mcell  D9     mx D24             ...           ...
mx D8inst_CLK_000_NE_D0    mcell  B15     mx D25   SM_AMIGA_i_7_     mcell  F0
mx D9           DTACK        pin 30     mx D26             ...           ...
mx D10 inst_CLK_000_NE     mcell  G9     mx D27inst_UDS_000_INT     mcell  F5
mx D11            RN_E     mcell  G4     mx D28inst_AMIGA_BUS_ENABLE_DMA_HIGH    mcell  G10
mx D12 inst_CLK_000_D0    mcell  G13     mx D29        RN_RESET    mcell  B14
mx D13  inst_AS_030_D0     mcell  H5     mx D30      cpu_est_0_     mcell  D6
mx D14          BG_030        pin 21     mx D31             ...           ...
mx D15      inst_VPA_D    mcell  F13     mx D32             ...           ...
mx D16inst_LDS_000_INT     mcell  B9
----------------------------------------------------------------------------


BLOCK_E_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx E0CLK_000_P_SYNC_4_     mcell  B4     mx E17           FC_0_        pin 57
mx E1           A_31_         pin 4     mx E18       BGACK_000        pin 28
mx E2CLK_000_P_SYNC_5_     mcell  E9     mx E19           A_30_         pin 5
mx E3inst_nEXP_SPACE_D0reg     mcell  G5     mx E20           FC_1_        pin 58
mx E4  inst_AS_030_D0     mcell  H5     mx E21           A_27_        pin 16
mx E5           A_24_        pin 19     mx E22 inst_AS_000_INT     mcell  C1
mx E6           A_16_        pin 96     mx E23    RN_BGACK_030     mcell  H4
mx E7           A_28_        pin 15     mx E24             ...           ...
mx E8           A_17_        pin 59     mx E25             ...           ...
mx E9           A_26_        pin 17     mx E26             ...           ...
mx E10CLK_000_N_SYNC_6_    mcell  D14     mx E27           A_19_        pin 97
mx E11       FPU_SENSE        pin 91     mx E28          RW_000        pin 80
mx E12           A_25_        pin 18     mx E29        RN_RESET    mcell  B14
mx E13           A_29_         pin 6     mx E30             ...           ...
mx E14             ...           ...     mx E31           A_18_        pin 95
mx E15             ...           ...     mx E32          AS_030        pin 82
mx E16          AS_000        pin 42
----------------------------------------------------------------------------


BLOCK_F_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx F0             RST        pin 86     mx F17     SM_AMIGA_3_    mcell  F12
mx F1            BERR        pin 41     mx F18     SM_AMIGA_0_     mcell  F9
mx F2            RN_E     mcell  G4     mx F19     SM_AMIGA_4_    mcell  F10
mx F3      cpu_est_2_     mcell  D2     mx F20  inst_DS_030_D0    mcell  D10
mx F4      cpu_est_0_     mcell  D6     mx F21      cpu_est_1_    mcell  D13
mx F5             ...           ...     mx F22inst_nEXP_SPACE_D0reg     mcell  G5
mx F6      inst_VPA_D    mcell  F13     mx F23             ...           ...
mx F7inst_AS_030_000_SYNC     mcell  C8     mx F24             ...           ...
mx F8inst_CLK_000_NE_D0    mcell  B15     mx F25 inst_CLK_000_PE     mcell  D9
mx F9inst_UDS_000_INT     mcell  F5     mx F26          RN_VMA     mcell  D0
mx F10     SM_AMIGA_1_     mcell  F1     mx F27 inst_CLK_000_NE     mcell  G9
mx F11           N_165     mcell  F6     mx F28     SM_AMIGA_2_     mcell  F2
mx F12 inst_CLK_000_D0    mcell  G13     mx F29     SM_AMIGA_5_     mcell  F4
mx F13             VPA        pin 36     mx F30             ...           ...
mx F14     SM_AMIGA_6_     mcell  C4     mx F31   inst_DTACK_D0    mcell  D15
mx F15              A0        pin 69     mx F32 inst_CLK_000_D1     mcell  F8
mx F16             ...           ...
----------------------------------------------------------------------------


BLOCK_G_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx G0    RN_BGACK_030     mcell  H4     mx G17           RN_RW     mcell  G0
mx G1      cpu_est_1_    mcell  D13     mx G18             ...           ...
mx G2            RN_E     mcell  G4     mx G19inst_CLK_OUT_PRE_50     mcell  A9
mx G3CLK_000_P_SYNC_0_    mcell  D11     mx G20CLK_000_N_SYNC_8_    mcell  A14
mx G4      cpu_est_0_     mcell  D6     mx G21             RST        pin 86
mx G5     SIZE_DMA_0_     mcell  G6     mx G22inst_AMIGA_BUS_ENABLE_DMA_HIGH    mcell  G10
mx G6          RW_000        pin 80     mx G23     SIZE_DMA_1_     mcell  G2
mx G7CLK_000_N_SYNC_11_     mcell  H6     mx G24         LDS_000        pin 31
mx G8inst_CLK_000_NE_D0    mcell  B15     mx G25             ...           ...
mx G9        RN_RESET    mcell  B14     mx G26CLK_000_P_SYNC_6_     mcell  E5
mx G10inst_AMIGA_BUS_ENABLE_DMA_LOW    mcell  G14     mx G27             ...           ...
mx G11              A1        pin 60     mx G28inst_BGACK_030_INT_D    mcell  H13
mx G12         UDS_000        pin 32     mx G29             ...           ...
mx G13           RN_A0     mcell  G8     mx G30             ...           ...
mx G14         CLK_000        pin 11     mx G31             ...           ...
mx G15      nEXP_SPACE        pin 14     mx G32inst_nEXP_SPACE_D0reg     mcell  G5
mx G16      cpu_est_2_     mcell  D2
----------------------------------------------------------------------------


BLOCK_H_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM             Signal    Source        CSM             Signal    Source
------------------------------------    ------------------------------------
mx H0    RN_BGACK_030     mcell  H4     mx H17           FC_0_        pin 57
mx H1            BERR        pin 41     mx H18       BGACK_000        pin 28
mx H2inst_CLK_OUT_PRE_D    mcell  G15     mx H19          AS_030        pin 82
mx H3 inst_AS_000_DMA     mcell  A8     mx H20         CLK_030        pin 64
mx H4  inst_AS_030_D0     mcell  H5     mx H21             RST        pin 86
mx H5   SM_AMIGA_i_7_     mcell  F0     mx H22inst_nEXP_SPACE_D0reg     mcell  G5
mx H6           A_19_        pin 97     mx H23     SIZE_DMA_1_     mcell  G2
mx H7 inst_CLK_000_PE     mcell  D9     mx H24CLK_000_N_SYNC_9_     mcell  G3
mx H8       FPU_SENSE        pin 91     mx H25              RW        pin 71
mx H9        RN_RESET    mcell  B14     mx H26             ...           ...
mx H10     SM_AMIGA_5_     mcell  F4     mx H27       RN_DSACK1     mcell  H9
mx H11           A_16_        pin 96     mx H28             ...           ...
mx H12           FC_1_        pin 58     mx H29     SIZE_DMA_0_     mcell  G6
mx H13           A_17_        pin 59     mx H30       RN_RW_000     mcell  H0
mx H14CLK_000_N_SYNC_10_     mcell  H2     mx H31           A_18_        pin 95
mx H15     SM_AMIGA_1_     mcell  F1     mx H32     SM_AMIGA_0_     mcell  F9
mx H16          AS_000        pin 42
----------------------------------------------------------------------------

<Note> CSM indicates the mux inputs from the Central Switch Matrix.
<Note> Source indicates where the signal comes from (pin or macrocell). 




PostFit_Equations
~~~~~~~~~~~~~~~~~


 P-Terms   Fan-in  Fan-out  Type  Name (attributes)
---------  ------  -------  ----  -----------------
   1          2        1    Pin   SIZE_0_ 
   1          2        1    Pin   SIZE_0_.OE 
   1          2        1    Pin   SIZE_1_ 
   1          2        1    Pin   SIZE_1_.OE 
   1          2        1    Pin   AS_030- 
   1          3        1    Pin   AS_030.OE 
   1          2        1    Pin   AS_000- 
   1          2        1    Pin   AS_000.OE 
   1          2        1    Pin   DS_030- 
   1          3        1    Pin   DS_030.OE 
   1          3        1    Pin   UDS_000- 
   1          2        1    Pin   UDS_000.OE 
   1          3        1    Pin   LDS_000- 
   1          2        1    Pin   LDS_000.OE 
   0          0        1    Pin   BERR 
   1          9        1    Pin   BERR.OE 
   0          0        1    Pin   CLK_DIV_OUT 
   0          0        1    Pin   CLK_DIV_OUT.OE 
   1          1        1    Pin   CLK_EXP 
   1          9        1    Pin   FPU_CS- 
   1          0        1    Pin   AVEC 
   0          0        1    Pin   AMIGA_ADDR_ENABLE 
   2          4        1    Pin   AMIGA_BUS_DATA_DIR 
   1          2        1    Pin   AMIGA_BUS_ENABLE_LOW- 
   2          3        1    Pin   AMIGA_BUS_ENABLE_HIGH 
   1          0        1    Pin   CIIN 
   1         10        1    Pin   CIIN.OE 
  10          8        1    Pin   IPL_030_2_.D- 
   1          1        1    Pin   IPL_030_2_.C 
   1          2        1    Pin   RW_000.OE 
   3          7        1    Pin   RW_000.D- 
   1          1        1    Pin   RW_000.C 
   1          3        1    Pin   A0.OE 
   3          5        1    Pin   A0.D 
   1          1        1    Pin   A0.C 
   2          6        1    Pin   BG_000.D- 
   1          1        1    Pin   BG_000.C 
   2          4        1    Pin   BGACK_030.D- 
   1          1        1    Pin   BGACK_030.C 
  10          8        1    Pin   IPL_030_1_.D- 
   1          1        1    Pin   IPL_030_1_.C 
  10          8        1    Pin   IPL_030_0_.D- 
   1          1        1    Pin   IPL_030_0_.C 
   1          1        1    Pin   DSACK1.OE 
   4          9        1    Pin   DSACK1.D- 
   1          1        1    Pin   DSACK1.C 
   5          5        1    Pin   E.D 
   1          1        1    Pin   E.C 
   3          9        1    Pin   VMA.T 
   1          1        1    Pin   VMA.C 
   2         11        1    Pin   RESET.D 
   1          1        1    Pin   RESET.C 
   1          2        1    Pin   RW.OE 
   2          5        1    Pin   RW.D- 
   1          1        1    Pin   RW.C 
   4         11        1    Node  N_165 
   2          2        1    Node  cpu_est_0_.D 
   1          1        1    Node  cpu_est_0_.C 
   5          5        1    Node  cpu_est_1_.D- 
   1          1        1    Node  cpu_est_1_.C 
   2          5        1    Node  inst_AS_000_INT.D- 
   1          1        1    Node  inst_AS_000_INT.C 
   3          6        1    Node  SM_AMIGA_5_.D 
   1          1        1    Node  SM_AMIGA_5_.C 
   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 
   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.C 
   1          2        1    Node  inst_AS_030_D0.D- 
   1          1        1    Node  inst_AS_030_D0.C 
   1          2        1    Node  inst_nEXP_SPACE_D0reg.D- 
   1          1        1    Node  inst_nEXP_SPACE_D0reg.C 
   1          2        1    Node  inst_DS_030_D0.D- 
   1          1        1    Node  inst_DS_030_D0.C 
   7         14        1    Node  inst_AS_030_000_SYNC.D- 
   1          1        1    Node  inst_AS_030_000_SYNC.C 
   1          2        1    Node  inst_BGACK_030_INT_D.D- 
   1          1        1    Node  inst_BGACK_030_INT_D.C 
   7          9        1    Node  inst_AS_000_DMA.D 
   1          1        1    Node  inst_AS_000_DMA.C 
   9         12        1    Node  inst_DS_000_DMA.D 
   1          1        1    Node  inst_DS_000_DMA.C 
   2          5        1    Node  CYCLE_DMA_0_.D 
   1          1        1    Node  CYCLE_DMA_0_.C 
   3          6        1    Node  CYCLE_DMA_1_.D 
   1          1        1    Node  CYCLE_DMA_1_.C 
   3          6        1    Node  SIZE_DMA_0_.D- 
   1          1        1    Node  SIZE_DMA_0_.C 
   3          6        1    Node  SIZE_DMA_1_.D 
   1          1        1    Node  SIZE_DMA_1_.C 
   1          2        1    Node  inst_VPA_D.D- 
   1          1        1    Node  inst_VPA_D.C 
   3          5        1    Node  inst_UDS_000_INT.D- 
   1          1        1    Node  inst_UDS_000_INT.C 
   4          7        1    Node  inst_LDS_000_INT.D 
   1          1        1    Node  inst_LDS_000_INT.C 
   1          1        1    Node  inst_CLK_OUT_PRE_D.D 
   1          1        1    Node  inst_CLK_OUT_PRE_D.C 
   1          2        1    Node  inst_DTACK_D0.D- 
   1          1        1    Node  inst_DTACK_D0.C 
   1          1        1    Node  inst_CLK_OUT_PRE_50.D 
   1          1        1    Node  inst_CLK_OUT_PRE_50.C 
   1          1        1    Node  inst_CLK_000_D1.D 
   1          1        1    Node  inst_CLK_000_D1.C 
   1          1        1    Node  inst_CLK_000_D0.D 
   1          1        1    Node  inst_CLK_000_D0.C 
   1          1        1    Node  inst_CLK_000_PE.D 
   1          1        1    Node  inst_CLK_000_PE.C 
   1          1        1    Node  CLK_000_P_SYNC_9_.D 
   1          1        1    Node  CLK_000_P_SYNC_9_.C 
   1          1        1    Node  inst_CLK_000_NE.D 
   1          1        1    Node  inst_CLK_000_NE.C 
   1          1        1    Node  CLK_000_N_SYNC_11_.D 
   1          1        1    Node  CLK_000_N_SYNC_11_.C 
   4          5        1    Node  cpu_est_2_.D 
   1          1        1    Node  cpu_est_2_.C 
   1          2        1    Node  IPL_D0_0_.D- 
   1          1        1    Node  IPL_D0_0_.C 
   1          2        1    Node  IPL_D0_1_.D- 
   1          1        1    Node  IPL_D0_1_.C 
   1          2        1    Node  IPL_D0_2_.D- 
   1          1        1    Node  IPL_D0_2_.C 
   5         13        1    Node  SM_AMIGA_3_.T 
   1          1        1    Node  SM_AMIGA_3_.C 
   1          1        1    Node  inst_CLK_000_NE_D0.D 
   1          1        1    Node  inst_CLK_000_NE_D0.C 
   2          6        1    Node  SM_AMIGA_0_.D 
   1          1        1    Node  SM_AMIGA_0_.C 
   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 
   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 
   3          9        1    Node  SM_AMIGA_6_.D 
   1          1        1    Node  SM_AMIGA_6_.C 
   3         10        1    Node  RST_DLY_0_.D 
   1          1        1    Node  RST_DLY_0_.C 
   4         10        1    Node  RST_DLY_1_.D 
   1          1        1    Node  RST_DLY_1_.C 
   5         10        1    Node  RST_DLY_2_.D 
   1          1        1    Node  RST_DLY_2_.C 
   6         10        1    Node  RST_DLY_3_.D 
   1          1        1    Node  RST_DLY_3_.C 
   2          7        1    NodeX1  RST_DLY_4_.T.X1 
   1         10        1    NodeX2  RST_DLY_4_.T.X2 
   1          1        1    Node  RST_DLY_4_.C 
   4         10        1    Node  RST_DLY_5_.T 
   1          1        1    Node  RST_DLY_5_.C 
   3         10        1    Node  RST_DLY_6_.T 
   1          1        1    Node  RST_DLY_6_.C 
   2         10        1    Node  RST_DLY_7_.D 
   1          1        1    Node  RST_DLY_7_.C 
   1          2        1    Node  CLK_000_P_SYNC_0_.D 
   1          1        1    Node  CLK_000_P_SYNC_0_.C 
   1          1        1    Node  CLK_000_P_SYNC_1_.D 
   1          1        1    Node  CLK_000_P_SYNC_1_.C 
   1          1        1    Node  CLK_000_P_SYNC_2_.D 
   1          1        1    Node  CLK_000_P_SYNC_2_.C 
   1          1        1    Node  CLK_000_P_SYNC_3_.D 
   1          1        1    Node  CLK_000_P_SYNC_3_.C 
   1          1        1    Node  CLK_000_P_SYNC_4_.D 
   1          1        1    Node  CLK_000_P_SYNC_4_.C 
   1          1        1    Node  CLK_000_P_SYNC_5_.D 
   1          1        1    Node  CLK_000_P_SYNC_5_.C 
   1          1        1    Node  CLK_000_P_SYNC_6_.D 
   1          1        1    Node  CLK_000_P_SYNC_6_.C 
   1          1        1    Node  CLK_000_P_SYNC_7_.D 
   1          1        1    Node  CLK_000_P_SYNC_7_.C 
   1          1        1    Node  CLK_000_P_SYNC_8_.D 
   1          1        1    Node  CLK_000_P_SYNC_8_.C 
   1          2        1    Node  CLK_000_N_SYNC_0_.D 
   1          1        1    Node  CLK_000_N_SYNC_0_.C 
   1          1        1    Node  CLK_000_N_SYNC_1_.D 
   1          1        1    Node  CLK_000_N_SYNC_1_.C 
   1          1        1    Node  CLK_000_N_SYNC_2_.D 
   1          1        1    Node  CLK_000_N_SYNC_2_.C 
   1          1        1    Node  CLK_000_N_SYNC_3_.D 
   1          1        1    Node  CLK_000_N_SYNC_3_.C 
   1          1        1    Node  CLK_000_N_SYNC_4_.D 
   1          1        1    Node  CLK_000_N_SYNC_4_.C 
   1          1        1    Node  CLK_000_N_SYNC_5_.D 
   1          1        1    Node  CLK_000_N_SYNC_5_.C 
   1          1        1    Node  CLK_000_N_SYNC_6_.D 
   1          1        1    Node  CLK_000_N_SYNC_6_.C 
   1          1        1    Node  CLK_000_N_SYNC_7_.D 
   1          1        1    Node  CLK_000_N_SYNC_7_.C 
   1          1        1    Node  CLK_000_N_SYNC_8_.D 
   1          1        1    Node  CLK_000_N_SYNC_8_.C 
   1          1        1    Node  CLK_000_N_SYNC_9_.D 
   1          1        1    Node  CLK_000_N_SYNC_9_.C 
   1          1        1    Node  CLK_000_N_SYNC_10_.D 
   1          1        1    Node  CLK_000_N_SYNC_10_.C 
   8         10        1    Node  inst_CLK_030_H.D 
   1          1        1    Node  inst_CLK_030_H.C 
   3          6        1    Node  SM_AMIGA_1_.D 
   1          1        1    Node  SM_AMIGA_1_.C 
   3          6        1    Node  SM_AMIGA_4_.D 
   1          1        1    Node  SM_AMIGA_4_.C 
   4         13        1    Node  SM_AMIGA_2_.D 
   1          1        1    Node  SM_AMIGA_2_.C 
   3          7        1    Node  inst_DS_000_ENABLE.D 
   1          1        1    Node  inst_DS_000_ENABLE.C 
  14         20        1    Node  SM_AMIGA_i_7_.D 
   1          1        1    Node  SM_AMIGA_i_7_.C 
=========
 346                 P-Term Total: 346
                       Total Pins: 57
                      Total Nodes: 72
            Average P-Term/Output: 2


Equations:

SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);

SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);

SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);

SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);

!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);

AS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);

!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);

AS_000.OE = (BGACK_030.Q & RESET.Q);

!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);

DS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);

!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);

UDS_000.OE = (BGACK_030.Q & RESET.Q);

!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);

LDS_000.OE = (BGACK_030.Q & RESET.Q);

BERR = (0);

BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);

CLK_DIV_OUT = (0);

CLK_DIV_OUT.OE = (0);

CLK_EXP = (CLK_030);

!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);

AVEC = (1);

AMIGA_ADDR_ENABLE = (0);

AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
     # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);

!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);

AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
     # BGACK_030.Q & !SM_AMIGA_i_7_.Q);

CIIN = (1);

CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q);

!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
     # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
     # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
     # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
     # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
     # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
     # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
     # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
     # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);

IPL_030_2_.C = (CLK_OSZI);

RW_000.OE = (BGACK_030.Q & RESET.Q);

!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
     # RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
     # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);

RW_000.C = (CLK_OSZI);

A0.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);

A0.D = (!RST
     # !BGACK_030.Q & UDS_000.PIN
     # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q);

A0.C = (CLK_OSZI);

!BG_000.D = (!BG_030 & RST & !BG_000.Q
     # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);

BG_000.C = (CLK_OSZI);

!BGACK_030.D = (!BGACK_000 & RST
     # RST & !BGACK_030.Q & !inst_CLK_000_PE.Q);

BGACK_030.C = (CLK_OSZI);

!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
     # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
     # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
     # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
     # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
     # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
     # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
     # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
     # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);

IPL_030_1_.C = (CLK_OSZI);

!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
     # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
     # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
     # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
     # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
     # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
     # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
     # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
     # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);

IPL_030_0_.C = (CLK_OSZI);

DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);

!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
     # !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
     # RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
     # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);

DSACK1.C = (CLK_OSZI);

E.D = (E.Q & !cpu_est_0_.Q
     # E.Q & !cpu_est_1_.Q
     # E.Q & !inst_CLK_000_NE_D0.Q
     # cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
     # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);

E.C = (CLK_OSZI);

VMA.T = (!RST & !VMA.Q
     # !E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q
     # RST & !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q);

VMA.C = (CLK_OSZI);

RESET.D = (RST & RESET.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);

RESET.C = (CLK_OSZI);

RW.OE = (!BGACK_030.Q & RESET.Q);

!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
     # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);

RW.C = (CLK_OSZI);

N_165 = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);

cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
     # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);

cpu_est_0_.C = (CLK_OSZI);

!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
     # E.Q & cpu_est_0_.Q & !cpu_est_1_.Q
     # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q
     # E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
     # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);

cpu_est_1_.C = (CLK_OSZI);

!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q
     # RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);

inst_AS_000_INT.C = (CLK_OSZI);

SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
     # RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN
     # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);

SM_AMIGA_5_.C = (CLK_OSZI);

!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q
     # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);

inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);

!inst_AS_030_D0.D = (RST & !AS_030.PIN);

inst_AS_030_D0.C = (CLK_OSZI);

!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST);

inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);

!inst_DS_030_D0.D = (RST & !DS_030.PIN);

inst_DS_030_D0.C = (CLK_OSZI);

!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
     # !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
     # RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
     # RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
     # RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
     # RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
     # RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);

inst_AS_030_000_SYNC.C = (CLK_OSZI);

!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);

inst_BGACK_030_INT_D.C = (CLK_OSZI);

inst_AS_000_DMA.D = (!RST
     # BGACK_030.Q
     # AS_000.PIN
     # !CLK_030 & inst_AS_000_DMA.Q
     # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
     # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
     # UDS_000.PIN & LDS_000.PIN);

inst_AS_000_DMA.C = (CLK_OSZI);

inst_DS_000_DMA.D = (!RST
     # BGACK_030.Q
     # AS_000.PIN
     # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
     # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
     # UDS_000.PIN & LDS_000.PIN
     # !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
     # inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
     # CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);

inst_DS_000_DMA.C = (CLK_OSZI);

CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN
     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN);

CYCLE_DMA_0_.C = (CLK_OSZI);

CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
     # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN
     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN);

CYCLE_DMA_1_.C = (CLK_OSZI);

!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
     # RST & BGACK_030.Q & !SIZE_DMA_0_.Q
     # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);

SIZE_DMA_0_.C = (CLK_OSZI);

SIZE_DMA_1_.D = (!RST
     # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
     # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);

SIZE_DMA_1_.C = (CLK_OSZI);

!inst_VPA_D.D = (!VPA & RST);

inst_VPA_D.C = (CLK_OSZI);

!inst_UDS_000_INT.D = (RST & inst_DS_030_D0.Q & !inst_UDS_000_INT.Q
     # RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
     # RST & !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & !A0.PIN);

inst_UDS_000_INT.C = (CLK_OSZI);

inst_LDS_000_INT.D = (!RST
     # inst_DS_030_D0.Q & inst_LDS_000_INT.Q
     # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
     # !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);

inst_LDS_000_INT.C = (CLK_OSZI);

inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);

inst_CLK_OUT_PRE_D.C = (CLK_OSZI);

!inst_DTACK_D0.D = (!DTACK & RST);

inst_DTACK_D0.C = (CLK_OSZI);

inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);

inst_CLK_OUT_PRE_50.C = (CLK_OSZI);

inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);

inst_CLK_000_D1.C = (CLK_OSZI);

inst_CLK_000_D0.D = (CLK_000);

inst_CLK_000_D0.C = (CLK_OSZI);

inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);

inst_CLK_000_PE.C = (CLK_OSZI);

CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);

CLK_000_P_SYNC_9_.C = (CLK_OSZI);

inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);

inst_CLK_000_NE.C = (CLK_OSZI);

CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);

CLK_000_N_SYNC_11_.C = (CLK_OSZI);

cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q
     # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
     # E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
     # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);

cpu_est_2_.C = (CLK_OSZI);

!IPL_D0_0_.D = (RST & !IPL_0_);

IPL_D0_0_.C = (CLK_OSZI);

!IPL_D0_1_.D = (RST & !IPL_1_);

IPL_D0_1_.C = (CLK_OSZI);

!IPL_D0_2_.D = (!IPL_2_ & RST);

IPL_D0_2_.C = (CLK_OSZI);

SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
     # SM_AMIGA_3_.Q & !BERR.PIN
     # RST & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & SM_AMIGA_4_.Q
     # inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q
     # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q);

SM_AMIGA_3_.C = (CLK_OSZI);

inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);

inst_CLK_000_NE_D0.C = (CLK_OSZI);

SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);

SM_AMIGA_0_.C = (CLK_OSZI);

!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q
     # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);

inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);

SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
     # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);

SM_AMIGA_6_.C = (CLK_OSZI);

RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q
     # RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q
     # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);

RST_DLY_0_.C = (CLK_OSZI);

RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q
     # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q
     # RST & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);

RST_DLY_1_.C = (CLK_OSZI);

RST_DLY_2_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_2_.Q
     # RST & !RST_DLY_0_.Q & RST_DLY_2_.Q
     # RST & !RST_DLY_1_.Q & RST_DLY_2_.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & !RST_DLY_2_.Q
     # RST & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);

RST_DLY_2_.C = (CLK_OSZI);

RST_DLY_3_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_3_.Q
     # RST & !RST_DLY_0_.Q & RST_DLY_3_.Q
     # RST & !RST_DLY_1_.Q & RST_DLY_3_.Q
     # RST & !RST_DLY_2_.Q & RST_DLY_3_.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & !RST_DLY_3_.Q
     # RST & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);

RST_DLY_3_.C = (CLK_OSZI);

RST_DLY_4_.T.X1 = (!RST & RST_DLY_4_.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q);

RST_DLY_4_.T.X2 = (RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);

RST_DLY_4_.C = (CLK_OSZI);

RST_DLY_5_.T = (!RST & RST_DLY_5_.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & !RST_DLY_5_.Q
     # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q
     # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_7_.Q);

RST_DLY_5_.C = (CLK_OSZI);

RST_DLY_6_.T = (!RST & RST_DLY_6_.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q
     # inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & !RST_DLY_7_.Q);

RST_DLY_6_.C = (CLK_OSZI);

RST_DLY_7_.D = (RST & RST_DLY_7_.Q
     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q);

RST_DLY_7_.C = (CLK_OSZI);

CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);

CLK_000_P_SYNC_0_.C = (CLK_OSZI);

CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);

CLK_000_P_SYNC_1_.C = (CLK_OSZI);

CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);

CLK_000_P_SYNC_2_.C = (CLK_OSZI);

CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);

CLK_000_P_SYNC_3_.C = (CLK_OSZI);

CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);

CLK_000_P_SYNC_4_.C = (CLK_OSZI);

CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);

CLK_000_P_SYNC_5_.C = (CLK_OSZI);

CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);

CLK_000_P_SYNC_6_.C = (CLK_OSZI);

CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);

CLK_000_P_SYNC_7_.C = (CLK_OSZI);

CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);

CLK_000_P_SYNC_8_.C = (CLK_OSZI);

CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);

CLK_000_N_SYNC_0_.C = (CLK_OSZI);

CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);

CLK_000_N_SYNC_1_.C = (CLK_OSZI);

CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);

CLK_000_N_SYNC_2_.C = (CLK_OSZI);

CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);

CLK_000_N_SYNC_3_.C = (CLK_OSZI);

CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);

CLK_000_N_SYNC_4_.C = (CLK_OSZI);

CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);

CLK_000_N_SYNC_5_.C = (CLK_OSZI);

CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);

CLK_000_N_SYNC_6_.C = (CLK_OSZI);

CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);

CLK_000_N_SYNC_7_.C = (CLK_OSZI);

CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);

CLK_000_N_SYNC_8_.C = (CLK_OSZI);

CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);

CLK_000_N_SYNC_9_.C = (CLK_OSZI);

CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);

CLK_000_N_SYNC_10_.C = (CLK_OSZI);

inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
     # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);

inst_CLK_030_H.C = (CLK_OSZI);

SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
     # RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN
     # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN);

SM_AMIGA_1_.C = (CLK_OSZI);

SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
     # RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);

SM_AMIGA_4_.C = (CLK_OSZI);

SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
     # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q
     # RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q);

SM_AMIGA_2_.C = (CLK_OSZI);

inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q
     # RST & SM_AMIGA_5_.Q & RW.PIN
     # RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN);

inst_DS_000_ENABLE.C = (CLK_OSZI);

SM_AMIGA_i_7_.D = (RST & !N_165 & !inst_CLK_000_PE.Q & BERR.PIN
     # RST & !N_165 & !SM_AMIGA_0_.Q & BERR.PIN
     # RST & !N_165 & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q
     # RST & !N_165 & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
     # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
     # RST & !N_165 & inst_CLK_000_NE.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
     # RST & !N_165 & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # RST & !N_165 & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # RST & !N_165 & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
     # RST & E.Q & !VMA.Q & !N_165 & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);

SM_AMIGA_i_7_.C = (CLK_OSZI);


Reverse-Polarity Equations: