mirror of https://github.com/kr239/68030tk.git
MIsc. Update
This commit is contained in:
MHeinrichs
parent
fa0999c496
commit
c808e2f06a
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@ -107,11 +107,13 @@ signal DS_030_D0:STD_LOGIC := '1';
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signal AS_030_000_SYNC:STD_LOGIC := '1';
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signal BGACK_030_INT:STD_LOGIC := '1';
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signal BGACK_030_INT_D:STD_LOGIC := '1';
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signal BGACK_030_INT_PRE:STD_LOGIC := '1';
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signal AS_000_DMA:STD_LOGIC := '1';
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signal DS_000_DMA:STD_LOGIC := '1';
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signal RW_000_DMA:STD_LOGIC := '1';
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signal CYCLE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
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signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
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signal IPL_D0: STD_LOGIC_VECTOR ( 2 downto 0 ) := "111";
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signal A0_DMA: STD_LOGIC := '1';
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signal VMA_INT: STD_LOGIC := '1';
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signal VPA_D: STD_LOGIC := '1';
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@ -139,6 +141,7 @@ signal DTACK_D0: STD_LOGIC := '1';
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signal RESET_OUT: STD_LOGIC := '0';
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signal CLK_030_D0: STD_LOGIC := '0';
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--signal NO_RESET: STD_LOGIC := '0';
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signal RST_DLY: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000";
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begin
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@ -223,7 +226,9 @@ begin
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BG_000 <= '1';
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BGACK_030_INT <= '1';
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BGACK_030_INT_D <= '1';
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BGACK_030_INT_PRE<= '1';
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DSACK1_INT <= '1';
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IPL_D0 <= "111";
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IPL_030 <= "111";
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AS_000_DMA <= '1';
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DS_000_DMA <= '1';
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@ -237,10 +242,17 @@ begin
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DS_030_D0 <= '1';
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CLK_030_H <= '0';
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CYCLE_DMA <= "00";
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RST_DLY <= "00000000";
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RESET_OUT <= '0';
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else
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RESET_OUT <= '1';
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if(CLK_000_NE='1')then
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if(RST_DLY="11111111")then
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RESET_OUT <= '1';
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else
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RST_DLY <= RST_DLY+1;
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end if;
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end if;
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--now: 68000 state machine and signals
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@ -259,7 +271,8 @@ begin
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AND CLK_000_PE='1'
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--AND CLK_000_D0='1' and CLK_000_D1='0'
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) then -- BGACK_000 is high here!
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BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
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BGACK_030_INT_PRE<= '1';
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BGACK_030_INT <= BGACK_030_INT_PRE; --hold this signal high until 7m clock goes low
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end if;
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BGACK_030_INT_D <= BGACK_030_INT;
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@ -278,10 +291,13 @@ begin
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--interrupt buffering to avoid ghost interrupts
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if(CLK_000_NE='1')then
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--if(CLK_000_NE='1')then
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--if(CLK_000_D0='0' and CLK_000_D1='1')then
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IPL_030<=IPL;
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end if;
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IPL_D0<=IPL;
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if(IPL = IPL_D0)then
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IPL_030<=IPL;
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end if;
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--end if;
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-- as030-sampling and FPU-Select
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@ -476,10 +492,10 @@ begin
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end process pos_clk;
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--output clock assignment
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CLK_DIV_OUT <= CLK_OUT_INT;
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CLK_EXP <= CLK_OUT_INT;
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--CLK_DIV_OUT <= 'Z';
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--CLK_EXP <= CLK_030;
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--CLK_DIV_OUT <= CLK_OUT_INT;
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--CLK_EXP <= CLK_OUT_INT;
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CLK_DIV_OUT <= 'Z';
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CLK_EXP <= CLK_030;
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1281
Logic/68030_TK.tcl
1281
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1 @@
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-collapse all -pterms 16 -nmax 32 -clust 5 -reduce bypin choose -xorsyn -dev M4A5_clk
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,7 +1,7 @@
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// Signal Name Cross Reference File
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// ispLEVER Classic 1.8.00.04.29.14
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// Design '68030_tk' created Sat Mar 28 22:02:48 2015
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// Design '68030_tk' created Wed May 13 22:59:21 2015
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// LEGEND: '>' Functional Block Port Separator
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@ -0,0 +1 @@
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-dev mach4a_DT_NCE -clust 5
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@ -0,0 +1,773 @@
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ispLEVER Classic 1.8.00.04.29.14 Linked Equations File
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Copyright(C), 1992-2014, Lattice Semiconductor Corp.
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All Rights Reserved.
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Design bus68030 created Wed May 13 22:59:21 2015
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P-Terms Fan-in Fan-out Type Name (attributes)
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--------- ------ ------- ---- -----------------
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1 2 1 Pin SIZE_1_
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1 2 1 Pin SIZE_1_.OE
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1 2 1 Pin AS_030-
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1 3 1 Pin AS_030.OE
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1 2 1 Pin AS_000-
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1 2 1 Pin AS_000.OE
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1 2 1 Pin DS_030-
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1 3 1 Pin DS_030.OE
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1 3 1 Pin UDS_000-
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1 2 1 Pin UDS_000.OE
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1 3 1 Pin LDS_000-
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1 2 1 Pin LDS_000.OE
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0 0 1 Pin BERR
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1 9 1 Pin BERR.OE
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0 0 1 Pin CLK_DIV_OUT
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0 0 1 Pin CLK_DIV_OUT.OE
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1 1 1 Pin CLK_EXP
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1 9 1 Pin FPU_CS-
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1 0 1 Pin AVEC
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0 0 1 Pin AMIGA_ADDR_ENABLE
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2 4 1 Pin AMIGA_BUS_DATA_DIR
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1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
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2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
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1 13 1 Pin CIIN
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1 1 1 Pin CIIN.OE
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1 2 1 Pin SIZE_0_
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1 2 1 Pin SIZE_0_.OE
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10 8 1 Pin IPL_030_2_.D-
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1 1 1 Pin IPL_030_2_.C
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1 2 1 Pin RW_000.OE
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3 7 1 Pin RW_000.D-
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1 1 1 Pin RW_000.C
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1 3 1 Pin A0.OE
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3 5 1 Pin A0.D
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1 1 1 Pin A0.C
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2 6 1 Pin BG_000.D-
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1 1 1 Pin BG_000.C
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2 4 1 Pin BGACK_030.D-
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1 1 1 Pin BGACK_030.C
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10 8 1 Pin IPL_030_1_.D-
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1 1 1 Pin IPL_030_1_.C
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10 8 1 Pin IPL_030_0_.D-
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1 1 1 Pin IPL_030_0_.C
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1 1 1 Pin DSACK1.OE
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4 9 1 Pin DSACK1.D-
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1 1 1 Pin DSACK1.C
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5 5 1 Pin E.D
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1 1 1 Pin E.C
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3 9 1 Pin VMA.T
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1 1 1 Pin VMA.C
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2 11 1 Pin RESET.D
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1 1 1 Pin RESET.C
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1 2 1 Pin RW.OE
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2 5 1 Pin RW.D-
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1 1 1 Pin RW.C
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2 2 1 Node cpu_est_0_.D
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1 1 1 Node cpu_est_0_.C
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5 5 1 Node cpu_est_1_.D-
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1 1 1 Node cpu_est_1_.C
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2 5 1 Node inst_AS_000_INT.D-
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1 1 1 Node inst_AS_000_INT.C
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3 6 1 Node SM_AMIGA_5_.D
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1 1 1 Node SM_AMIGA_5_.C
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2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
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1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
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1 2 1 Node inst_AS_030_D0.D-
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1 1 1 Node inst_AS_030_D0.C
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1 2 1 Node inst_nEXP_SPACE_D0reg.D-
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1 1 1 Node inst_nEXP_SPACE_D0reg.C
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1 2 1 Node inst_DS_030_D0.D-
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1 1 1 Node inst_DS_030_D0.C
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7 14 1 Node inst_AS_030_000_SYNC.D-
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1 1 1 Node inst_AS_030_000_SYNC.C
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1 2 1 Node inst_BGACK_030_INT_D.D-
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1 1 1 Node inst_BGACK_030_INT_D.C
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7 9 1 Node inst_AS_000_DMA.D
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1 1 1 Node inst_AS_000_DMA.C
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9 12 1 Node inst_DS_000_DMA.D
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1 1 1 Node inst_DS_000_DMA.C
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2 5 1 Node CYCLE_DMA_0_.D
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1 1 1 Node CYCLE_DMA_0_.C
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3 6 1 Node CYCLE_DMA_1_.D
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1 1 1 Node CYCLE_DMA_1_.C
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3 6 1 Node SIZE_DMA_0_.D-
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1 1 1 Node SIZE_DMA_0_.C
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3 6 1 Node SIZE_DMA_1_.D
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1 1 1 Node SIZE_DMA_1_.C
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1 2 1 Node inst_VPA_D.D-
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1 1 1 Node inst_VPA_D.C
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3 5 1 Node inst_UDS_000_INT.D-
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1 1 1 Node inst_UDS_000_INT.C
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4 7 1 Node inst_LDS_000_INT.D
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1 1 1 Node inst_LDS_000_INT.C
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1 1 1 Node inst_CLK_OUT_PRE_D.D
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1 1 1 Node inst_CLK_OUT_PRE_D.C
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1 2 1 Node inst_DTACK_D0.D-
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1 1 1 Node inst_DTACK_D0.C
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1 1 1 Node inst_CLK_OUT_PRE_50.D
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1 1 1 Node inst_CLK_OUT_PRE_50.C
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1 1 1 Node inst_CLK_000_D1.D
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1 1 1 Node inst_CLK_000_D1.C
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1 1 1 Node inst_CLK_000_D0.D
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1 1 1 Node inst_CLK_000_D0.C
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1 1 1 Node inst_CLK_000_PE.D
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1 1 1 Node inst_CLK_000_PE.C
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1 1 1 Node CLK_000_P_SYNC_9_.D
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1 1 1 Node CLK_000_P_SYNC_9_.C
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1 1 1 Node inst_CLK_000_NE.D
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1 1 1 Node inst_CLK_000_NE.C
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4 11 1 Node N_96_i-
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1 1 1 Node CLK_000_N_SYNC_11_.D
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1 1 1 Node CLK_000_N_SYNC_11_.C
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4 5 1 Node cpu_est_2_.D
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1 1 1 Node cpu_est_2_.C
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1 2 1 Node IPL_D0_0_.D-
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1 1 1 Node IPL_D0_0_.C
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1 2 1 Node IPL_D0_1_.D-
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1 1 1 Node IPL_D0_1_.C
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1 2 1 Node IPL_D0_2_.D-
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1 1 1 Node IPL_D0_2_.C
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5 13 1 Node SM_AMIGA_3_.T
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1 1 1 Node SM_AMIGA_3_.C
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1 1 1 Node inst_CLK_000_NE_D0.D
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1 1 1 Node inst_CLK_000_NE_D0.C
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2 6 1 Node SM_AMIGA_0_.D
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1 1 1 Node SM_AMIGA_0_.C
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2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
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1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
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3 9 1 Node SM_AMIGA_6_.D
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1 1 1 Node SM_AMIGA_6_.C
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3 10 1 Node RST_DLY_0_.D
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1 1 1 Node RST_DLY_0_.C
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4 10 1 Node RST_DLY_1_.D
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1 1 1 Node RST_DLY_1_.C
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5 10 1 Node RST_DLY_2_.D
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1 1 1 Node RST_DLY_2_.C
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6 10 1 Node RST_DLY_3_.D
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1 1 1 Node RST_DLY_3_.C
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2 7 1 NodeX1 RST_DLY_4_.T.X1
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1 10 1 NodeX2 RST_DLY_4_.T.X2
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1 1 1 Node RST_DLY_4_.C
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4 10 1 Node RST_DLY_5_.T
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1 1 1 Node RST_DLY_5_.C
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3 10 1 Node RST_DLY_6_.T
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1 1 1 Node RST_DLY_6_.C
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2 10 1 Node RST_DLY_7_.D
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1 1 1 Node RST_DLY_7_.C
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1 2 1 Node CLK_000_P_SYNC_0_.D
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1 1 1 Node CLK_000_P_SYNC_0_.C
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1 1 1 Node CLK_000_P_SYNC_1_.D
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1 1 1 Node CLK_000_P_SYNC_1_.C
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1 1 1 Node CLK_000_P_SYNC_2_.D
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1 1 1 Node CLK_000_P_SYNC_2_.C
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1 1 1 Node CLK_000_P_SYNC_3_.D
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1 1 1 Node CLK_000_P_SYNC_3_.C
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1 1 1 Node CLK_000_P_SYNC_4_.D
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1 1 1 Node CLK_000_P_SYNC_4_.C
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1 1 1 Node CLK_000_P_SYNC_5_.D
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1 1 1 Node CLK_000_P_SYNC_5_.C
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1 1 1 Node CLK_000_P_SYNC_6_.D
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1 1 1 Node CLK_000_P_SYNC_6_.C
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1 1 1 Node CLK_000_P_SYNC_7_.D
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1 1 1 Node CLK_000_P_SYNC_7_.C
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1 1 1 Node CLK_000_P_SYNC_8_.D
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1 1 1 Node CLK_000_P_SYNC_8_.C
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1 2 1 Node CLK_000_N_SYNC_0_.D
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1 1 1 Node CLK_000_N_SYNC_0_.C
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1 1 1 Node CLK_000_N_SYNC_1_.D
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1 1 1 Node CLK_000_N_SYNC_1_.C
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1 1 1 Node CLK_000_N_SYNC_2_.D
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1 1 1 Node CLK_000_N_SYNC_2_.C
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1 1 1 Node CLK_000_N_SYNC_3_.D
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1 1 1 Node CLK_000_N_SYNC_3_.C
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1 1 1 Node CLK_000_N_SYNC_4_.D
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1 1 1 Node CLK_000_N_SYNC_4_.C
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1 1 1 Node CLK_000_N_SYNC_5_.D
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1 1 1 Node CLK_000_N_SYNC_5_.C
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1 1 1 Node CLK_000_N_SYNC_6_.D
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1 1 1 Node CLK_000_N_SYNC_6_.C
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1 1 1 Node CLK_000_N_SYNC_7_.D
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1 1 1 Node CLK_000_N_SYNC_7_.C
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1 1 1 Node CLK_000_N_SYNC_8_.D
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1 1 1 Node CLK_000_N_SYNC_8_.C
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1 1 1 Node CLK_000_N_SYNC_9_.D
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1 1 1 Node CLK_000_N_SYNC_9_.C
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1 1 1 Node CLK_000_N_SYNC_10_.D
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1 1 1 Node CLK_000_N_SYNC_10_.C
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8 10 1 Node inst_CLK_030_H.D
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1 1 1 Node inst_CLK_030_H.C
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3 6 1 Node SM_AMIGA_1_.D
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1 1 1 Node SM_AMIGA_1_.C
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3 6 1 Node SM_AMIGA_4_.D
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1 1 1 Node SM_AMIGA_4_.C
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4 13 1 Node SM_AMIGA_2_.D
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1 1 1 Node SM_AMIGA_2_.C
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3 7 1 Node inst_DS_000_ENABLE.D
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1 1 1 Node inst_DS_000_ENABLE.C
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14 20 1 Node SM_AMIGA_i_7_.D
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1 1 1 Node SM_AMIGA_i_7_.C
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2 14 1 Node CIIN_0
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=========
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348 P-Term Total: 348
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Total Pins: 61
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Total Nodes: 73
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Average P-Term/Output: 2
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Equations:
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SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
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SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
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!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
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AS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);
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!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
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AS_000.OE = (BGACK_030.Q & RESET.Q);
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!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
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DS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);
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!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);
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UDS_000.OE = (BGACK_030.Q & RESET.Q);
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!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);
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LDS_000.OE = (BGACK_030.Q & RESET.Q);
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BERR = (0);
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BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
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CLK_DIV_OUT = (0);
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CLK_DIV_OUT.OE = (0);
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CLK_EXP = (CLK_030);
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!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
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AVEC = (1);
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AMIGA_ADDR_ENABLE = (0);
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AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
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# !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
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!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
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AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
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# BGACK_030.Q & !SM_AMIGA_i_7_.Q);
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CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
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CIIN.OE = (CIIN_0);
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SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
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SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
|
||||
|
||||
!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
|
||||
# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
|
||||
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
|
||||
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
|
||||
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
|
||||
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
|
||||
# !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||||
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||||
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||||
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
||||
|
||||
IPL_030_2_.C = (CLK_OSZI);
|
||||
|
||||
RW_000.OE = (BGACK_030.Q & RESET.Q);
|
||||
|
||||
!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
|
||||
# RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);
|
||||
|
||||
RW_000.C = (CLK_OSZI);
|
||||
|
||||
A0.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);
|
||||
|
||||
A0.D = (!RST
|
||||
# !BGACK_030.Q & UDS_000.PIN
|
||||
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q);
|
||||
|
||||
A0.C = (CLK_OSZI);
|
||||
|
||||
!BG_000.D = (!BG_030 & RST & !BG_000.Q
|
||||
# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);
|
||||
|
||||
BG_000.C = (CLK_OSZI);
|
||||
|
||||
!BGACK_030.D = (!BGACK_000 & RST
|
||||
# RST & !BGACK_030.Q & !inst_CLK_000_PE.Q);
|
||||
|
||||
BGACK_030.C = (CLK_OSZI);
|
||||
|
||||
!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
|
||||
# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
|
||||
# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
|
||||
# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
|
||||
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
|
||||
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
|
||||
# IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
||||
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
||||
# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||||
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
||||
|
||||
IPL_030_1_.C = (CLK_OSZI);
|
||||
|
||||
!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
|
||||
# RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
|
||||
# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
|
||||
# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
|
||||
# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
|
||||
# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
|
||||
# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
|
||||
# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
|
||||
# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
|
||||
# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
|
||||
|
||||
IPL_030_0_.C = (CLK_OSZI);
|
||||
|
||||
DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
|
||||
|
||||
!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
|
||||
# !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
|
||||
# RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
|
||||
# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
|
||||
|
||||
DSACK1.C = (CLK_OSZI);
|
||||
|
||||
E.D = (E.Q & !cpu_est_0_.Q
|
||||
# E.Q & !cpu_est_1_.Q
|
||||
# E.Q & !inst_CLK_000_NE_D0.Q
|
||||
# cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
|
||||
# !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
E.C = (CLK_OSZI);
|
||||
|
||||
VMA.T = (!RST & !VMA.Q
|
||||
# !E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q
|
||||
# RST & !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q);
|
||||
|
||||
VMA.C = (CLK_OSZI);
|
||||
|
||||
RESET.D = (RST & RESET.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
||||
|
||||
RESET.C = (CLK_OSZI);
|
||||
|
||||
RW.OE = (!BGACK_030.Q & RESET.Q);
|
||||
|
||||
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
|
||||
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
|
||||
|
||||
RW.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
|
||||
# cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_0_.C = (CLK_OSZI);
|
||||
|
||||
!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
|
||||
# E.Q & cpu_est_0_.Q & !cpu_est_1_.Q
|
||||
# !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q
|
||||
# E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
|
||||
# !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_1_.C = (CLK_OSZI);
|
||||
|
||||
!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q
|
||||
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
|
||||
|
||||
inst_AS_000_INT.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
|
||||
# RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN
|
||||
# RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);
|
||||
|
||||
SM_AMIGA_5_.C = (CLK_OSZI);
|
||||
|
||||
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q
|
||||
# RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
|
||||
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
|
||||
|
||||
!inst_AS_030_D0.D = (RST & !AS_030.PIN);
|
||||
|
||||
inst_AS_030_D0.C = (CLK_OSZI);
|
||||
|
||||
!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST);
|
||||
|
||||
inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);
|
||||
|
||||
!inst_DS_030_D0.D = (RST & !DS_030.PIN);
|
||||
|
||||
inst_DS_030_D0.C = (CLK_OSZI);
|
||||
|
||||
!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
|
||||
# !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
||||
# RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
|
||||
|
||||
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
||||
|
||||
!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
|
||||
|
||||
inst_BGACK_030_INT_D.C = (CLK_OSZI);
|
||||
|
||||
inst_AS_000_DMA.D = (!RST
|
||||
# BGACK_030.Q
|
||||
# AS_000.PIN
|
||||
# !CLK_030 & inst_AS_000_DMA.Q
|
||||
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
||||
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
||||
# UDS_000.PIN & LDS_000.PIN);
|
||||
|
||||
inst_AS_000_DMA.C = (CLK_OSZI);
|
||||
|
||||
inst_DS_000_DMA.D = (!RST
|
||||
# BGACK_030.Q
|
||||
# AS_000.PIN
|
||||
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
||||
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
||||
# UDS_000.PIN & LDS_000.PIN
|
||||
# !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
|
||||
# inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
|
||||
# CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
|
||||
|
||||
inst_DS_000_DMA.C = (CLK_OSZI);
|
||||
|
||||
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN
|
||||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN);
|
||||
|
||||
CYCLE_DMA_0_.C = (CLK_OSZI);
|
||||
|
||||
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
|
||||
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN
|
||||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN);
|
||||
|
||||
CYCLE_DMA_1_.C = (CLK_OSZI);
|
||||
|
||||
!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
|
||||
# RST & BGACK_030.Q & !SIZE_DMA_0_.Q
|
||||
# RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
||||
|
||||
SIZE_DMA_0_.C = (CLK_OSZI);
|
||||
|
||||
SIZE_DMA_1_.D = (!RST
|
||||
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
|
||||
# !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
||||
|
||||
SIZE_DMA_1_.C = (CLK_OSZI);
|
||||
|
||||
!inst_VPA_D.D = (!VPA & RST);
|
||||
|
||||
inst_VPA_D.C = (CLK_OSZI);
|
||||
|
||||
!inst_UDS_000_INT.D = (RST & inst_DS_030_D0.Q & !inst_UDS_000_INT.Q
|
||||
# RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
|
||||
# RST & !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & !A0.PIN);
|
||||
|
||||
inst_UDS_000_INT.C = (CLK_OSZI);
|
||||
|
||||
inst_LDS_000_INT.D = (!RST
|
||||
# inst_DS_030_D0.Q & inst_LDS_000_INT.Q
|
||||
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
|
||||
# !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
|
||||
|
||||
inst_LDS_000_INT.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
|
||||
|
||||
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
|
||||
|
||||
!inst_DTACK_D0.D = (!DTACK & RST);
|
||||
|
||||
inst_DTACK_D0.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
|
||||
|
||||
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
|
||||
|
||||
inst_CLK_000_D1.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_000_D0.D = (CLK_000);
|
||||
|
||||
inst_CLK_000_D0.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
|
||||
|
||||
inst_CLK_000_PE.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
|
||||
|
||||
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
|
||||
|
||||
inst_CLK_000_NE.C = (CLK_OSZI);
|
||||
|
||||
!N_96_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);
|
||||
|
||||
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
|
||||
|
||||
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q
|
||||
# cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
|
||||
# E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
|
||||
# !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_2_.C = (CLK_OSZI);
|
||||
|
||||
!IPL_D0_0_.D = (RST & !IPL_0_);
|
||||
|
||||
IPL_D0_0_.C = (CLK_OSZI);
|
||||
|
||||
!IPL_D0_1_.D = (RST & !IPL_1_);
|
||||
|
||||
IPL_D0_1_.C = (CLK_OSZI);
|
||||
|
||||
!IPL_D0_2_.D = (!IPL_2_ & RST);
|
||||
|
||||
IPL_D0_2_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
|
||||
# SM_AMIGA_3_.Q & !BERR.PIN
|
||||
# RST & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & SM_AMIGA_4_.Q
|
||||
# inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q
|
||||
# E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q);
|
||||
|
||||
SM_AMIGA_3_.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);
|
||||
|
||||
inst_CLK_000_NE_D0.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
|
||||
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);
|
||||
|
||||
SM_AMIGA_0_.C = (CLK_OSZI);
|
||||
|
||||
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q
|
||||
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
|
||||
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
|
||||
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
|
||||
# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);
|
||||
|
||||
SM_AMIGA_6_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q
|
||||
# RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q
|
||||
# RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
||||
|
||||
RST_DLY_0_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q
|
||||
# RST & !RST_DLY_0_.Q & RST_DLY_1_.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q
|
||||
# RST & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
||||
|
||||
RST_DLY_1_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_2_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_2_.Q
|
||||
# RST & !RST_DLY_0_.Q & RST_DLY_2_.Q
|
||||
# RST & !RST_DLY_1_.Q & RST_DLY_2_.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & !RST_DLY_2_.Q
|
||||
# RST & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
||||
|
||||
RST_DLY_2_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_3_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_3_.Q
|
||||
# RST & !RST_DLY_0_.Q & RST_DLY_3_.Q
|
||||
# RST & !RST_DLY_1_.Q & RST_DLY_3_.Q
|
||||
# RST & !RST_DLY_2_.Q & RST_DLY_3_.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & !RST_DLY_3_.Q
|
||||
# RST & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
||||
|
||||
RST_DLY_3_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_4_.T.X1 = (!RST & RST_DLY_4_.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q);
|
||||
|
||||
RST_DLY_4_.T.X2 = (RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
||||
|
||||
RST_DLY_4_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_5_.T = (!RST & RST_DLY_5_.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & !RST_DLY_5_.Q
|
||||
# inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q
|
||||
# inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_7_.Q);
|
||||
|
||||
RST_DLY_5_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_6_.T = (!RST & RST_DLY_6_.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q
|
||||
# inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & !RST_DLY_7_.Q);
|
||||
|
||||
RST_DLY_6_.C = (CLK_OSZI);
|
||||
|
||||
RST_DLY_7_.D = (RST & RST_DLY_7_.Q
|
||||
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q);
|
||||
|
||||
RST_DLY_7_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
|
||||
|
||||
CLK_000_P_SYNC_0_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
|
||||
|
||||
CLK_000_P_SYNC_1_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
|
||||
|
||||
CLK_000_P_SYNC_2_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
|
||||
|
||||
CLK_000_P_SYNC_3_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
|
||||
|
||||
CLK_000_P_SYNC_4_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
|
||||
|
||||
CLK_000_P_SYNC_5_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
|
||||
|
||||
CLK_000_P_SYNC_6_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
|
||||
|
||||
CLK_000_P_SYNC_7_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
|
||||
|
||||
CLK_000_P_SYNC_8_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
|
||||
|
||||
CLK_000_N_SYNC_0_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
|
||||
|
||||
CLK_000_N_SYNC_1_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
|
||||
|
||||
CLK_000_N_SYNC_2_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
|
||||
|
||||
CLK_000_N_SYNC_3_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
|
||||
|
||||
CLK_000_N_SYNC_4_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
|
||||
|
||||
CLK_000_N_SYNC_5_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
|
||||
|
||||
CLK_000_N_SYNC_6_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
|
||||
|
||||
CLK_000_N_SYNC_7_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
|
||||
|
||||
CLK_000_N_SYNC_8_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
|
||||
|
||||
CLK_000_N_SYNC_9_.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
|
||||
|
||||
CLK_000_N_SYNC_10_.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
|
||||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
|
||||
# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
|
||||
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
|
||||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
|
||||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
|
||||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
|
||||
# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
|
||||
|
||||
inst_CLK_030_H.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
|
||||
# RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN
|
||||
# RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN);
|
||||
|
||||
SM_AMIGA_1_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
|
||||
# RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
|
||||
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);
|
||||
|
||||
SM_AMIGA_4_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
|
||||
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q
|
||||
# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
SM_AMIGA_2_.C = (CLK_OSZI);
|
||||
|
||||
inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q
|
||||
# RST & SM_AMIGA_5_.Q & RW.PIN
|
||||
# RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN);
|
||||
|
||||
inst_DS_000_ENABLE.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_i_7_.D = (RST & !inst_CLK_000_PE.Q & N_96_i & BERR.PIN
|
||||
# RST & N_96_i & !SM_AMIGA_0_.Q & BERR.PIN
|
||||
# RST & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
|
||||
# RST & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
|
||||
# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
|
||||
# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);
|
||||
|
||||
SM_AMIGA_i_7_.C = (CLK_OSZI);
|
||||
|
||||
CIIN_0 = (inst_nEXP_SPACE_D0reg.Q
|
||||
# !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
|
||||
|
||||
|
||||
Reverse-Polarity Equations:
|
||||
|
||||
|
|
@ -0,0 +1,488 @@
|
|||
#PLAFILE 68030_tk.tt4
|
||||
#DATE 03/16/2015
|
||||
#DESIGN <no design name>
|
||||
#DEVICE mach447a
|
||||
|
||||
DATA LOCATION A0:G_8_69 // IO {RN_A0}
|
||||
DATA LOCATION A1:F_*_60 // INP
|
||||
DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33 // OUT
|
||||
DATA LOCATION AMIGA_BUS_DATA_DIR:E_1_48 // OUT
|
||||
DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_4_34 // OUT
|
||||
DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_0_20 // OUT
|
||||
DATA LOCATION AS_000:E_4_42 // IO
|
||||
DATA LOCATION AS_030:H_8_82 // IO
|
||||
DATA LOCATION AVEC:A_4_92 // OUT
|
||||
DATA LOCATION A_16_:A_*_96 // INP
|
||||
DATA LOCATION A_17_:F_*_59 // INP
|
||||
DATA LOCATION A_18_:A_*_95 // INP
|
||||
DATA LOCATION A_19_:A_*_97 // INP
|
||||
DATA LOCATION A_20_:A_*_93 // INP
|
||||
DATA LOCATION A_21_:A_*_94 // INP
|
||||
DATA LOCATION A_22_:H_*_84 // INP
|
||||
DATA LOCATION A_23_:H_*_85 // INP
|
||||
DATA LOCATION A_24_:C_*_19 // INP
|
||||
DATA LOCATION A_25_:C_*_18 // INP
|
||||
DATA LOCATION A_26_:C_*_17 // INP
|
||||
DATA LOCATION A_27_:C_*_16 // INP
|
||||
DATA LOCATION A_28_:C_*_15 // INP
|
||||
DATA LOCATION A_29_:B_*_6 // INP
|
||||
DATA LOCATION A_30_:B_*_5 // INP
|
||||
DATA LOCATION A_31_:B_*_4 // INP
|
||||
DATA LOCATION BERR:E_0_41 // IO
|
||||
DATA LOCATION BGACK_000:D_*_28 // INP
|
||||
DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
|
||||
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
|
||||
DATA LOCATION BG_030:C_*_21 // INP
|
||||
DATA LOCATION CIIN:E_12_47 // OUT
|
||||
DATA LOCATION CIIN_0:E_5 // NOD
|
||||
DATA LOCATION CLK_000:*_*_11 // INP
|
||||
DATA LOCATION CLK_000_N_SYNC_0_:D_11 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_1_:B_3 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_2_:D_7 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_3_:D_3 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_4_:A_14 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_5_:C_13 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_6_:D_14 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_7_:D_10 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_8_:A_10 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_9_:G_6 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_0_:D_15 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_1_:G_7 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_2_:G_3 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_3_:B_11 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_4_:B_7 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_5_:G_14 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_6_:G_10 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_7_:A_7 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_8_:A_3 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_9_:A_11 // NOD
|
||||
DATA LOCATION CLK_030:*_*_64 // INP
|
||||
DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT
|
||||
DATA LOCATION CLK_EXP:B_1_10 // OUT
|
||||
DATA LOCATION CLK_OSZI:*_*_61 // Cin
|
||||
DATA LOCATION CYCLE_DMA_0_:A_6 // NOD
|
||||
DATA LOCATION CYCLE_DMA_1_:A_2 // NOD
|
||||
DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1}
|
||||
DATA LOCATION DS_030:A_0_98 // IO
|
||||
DATA LOCATION DTACK:D_*_30 // INP
|
||||
DATA LOCATION E:G_4_66 // IO {RN_E}
|
||||
DATA LOCATION FC_0_:F_*_57 // INP
|
||||
DATA LOCATION FC_1_:F_*_58 // INP
|
||||
DATA LOCATION FPU_CS:H_1_78 // OUT
|
||||
DATA LOCATION FPU_SENSE:A_*_91 // INP
|
||||
DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_}
|
||||
DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_}
|
||||
DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
|
||||
DATA LOCATION IPL_0_:G_*_67 // INP
|
||||
DATA LOCATION IPL_1_:F_*_56 // INP
|
||||
DATA LOCATION IPL_2_:G_*_68 // INP
|
||||
DATA LOCATION IPL_D0_0_:B_15 // NOD
|
||||
DATA LOCATION IPL_D0_1_:G_15 // NOD
|
||||
DATA LOCATION IPL_D0_2_:G_11 // NOD
|
||||
DATA LOCATION LDS_000:D_12_31 // IO
|
||||
DATA LOCATION N_96_i:F_6 // NOD
|
||||
DATA LOCATION RESET:B_0_3 // IO {RN_RESET}
|
||||
DATA LOCATION RN_A0:G_8 // NOD {A0}
|
||||
DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030}
|
||||
DATA LOCATION RN_BG_000:D_1 // NOD {BG_000}
|
||||
DATA LOCATION RN_DSACK1:H_9 // NOD {DSACK1}
|
||||
DATA LOCATION RN_E:G_4 // NOD {E}
|
||||
DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_}
|
||||
DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_}
|
||||
DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_}
|
||||
DATA LOCATION RN_RESET:B_0 // NOD {RESET}
|
||||
DATA LOCATION RN_RW:G_0 // NOD {RW}
|
||||
DATA LOCATION RN_RW_000:H_0 // NOD {RW_000}
|
||||
DATA LOCATION RN_VMA:D_0 // NOD {VMA}
|
||||
DATA LOCATION RST:*_*_86 // INP
|
||||
DATA LOCATION RST_DLY_0_:B_6 // NOD
|
||||
DATA LOCATION RST_DLY_1_:A_1 // NOD
|
||||
DATA LOCATION RST_DLY_2_:B_9 // NOD
|
||||
DATA LOCATION RST_DLY_3_:A_12 // NOD
|
||||
DATA LOCATION RST_DLY_4_:A_5 // NOD
|
||||
DATA LOCATION RST_DLY_5_:B_13 // NOD
|
||||
DATA LOCATION RST_DLY_6_:B_2 // NOD
|
||||
DATA LOCATION RST_DLY_7_:B_10 // NOD
|
||||
DATA LOCATION RW:G_0_71 // IO {RN_RW}
|
||||
DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000}
|
||||
DATA LOCATION SIZE_0_:G_12_70 // IO
|
||||
DATA LOCATION SIZE_1_:H_12_79 // IO
|
||||
DATA LOCATION SIZE_DMA_0_:G_13 // NOD
|
||||
DATA LOCATION SIZE_DMA_1_:G_9 // NOD
|
||||
DATA LOCATION SM_AMIGA_0_:B_5 // NOD
|
||||
DATA LOCATION SM_AMIGA_1_:F_8 // NOD
|
||||
DATA LOCATION SM_AMIGA_2_:F_2 // NOD
|
||||
DATA LOCATION SM_AMIGA_3_:F_13 // NOD
|
||||
DATA LOCATION SM_AMIGA_4_:F_10 // NOD
|
||||
DATA LOCATION SM_AMIGA_5_:F_12 // NOD
|
||||
DATA LOCATION SM_AMIGA_6_:F_9 // NOD
|
||||
DATA LOCATION SM_AMIGA_i_7_:F_4 // NOD
|
||||
DATA LOCATION UDS_000:D_8_32 // IO
|
||||
DATA LOCATION VMA:D_0_35 // IO {RN_VMA}
|
||||
DATA LOCATION VPA:*_*_36 // INP
|
||||
DATA LOCATION cpu_est_0_:F_1 // NOD
|
||||
DATA LOCATION cpu_est_1_:D_9 // NOD
|
||||
DATA LOCATION cpu_est_2_:D_13 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:C_1 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_9 // NOD
|
||||
DATA LOCATION inst_AS_000_DMA:A_8 // NOD
|
||||
DATA LOCATION inst_AS_000_INT:C_5 // NOD
|
||||
DATA LOCATION inst_AS_030_000_SYNC:C_4 // NOD
|
||||
DATA LOCATION inst_AS_030_D0:H_5 // NOD
|
||||
DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD
|
||||
DATA LOCATION inst_CLK_000_D0:D_6 // NOD
|
||||
DATA LOCATION inst_CLK_000_D1:G_2 // NOD
|
||||
DATA LOCATION inst_CLK_000_NE:E_8 // NOD
|
||||
DATA LOCATION inst_CLK_000_NE_D0:D_2 // NOD
|
||||
DATA LOCATION inst_CLK_000_PE:F_0 // NOD
|
||||
DATA LOCATION inst_CLK_030_H:A_13 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_50:E_9 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_D:E_13 // NOD
|
||||
DATA LOCATION inst_DS_000_DMA:A_9 // NOD
|
||||
DATA LOCATION inst_DS_000_ENABLE:F_5 // NOD
|
||||
DATA LOCATION inst_DS_030_D0:A_15 // NOD
|
||||
DATA LOCATION inst_DTACK_D0:C_2 // NOD
|
||||
DATA LOCATION inst_LDS_000_INT:C_8 // NOD
|
||||
DATA LOCATION inst_UDS_000_INT:C_12 // NOD
|
||||
DATA LOCATION inst_VPA_D:B_14 // NOD
|
||||
DATA LOCATION inst_nEXP_SPACE_D0reg:G_5 // NOD
|
||||
DATA LOCATION nEXP_SPACE:*_*_14 // INP
|
||||
DATA IO_DIR A0:BI
|
||||
DATA IO_DIR A1:IN
|
||||
DATA IO_DIR AMIGA_ADDR_ENABLE:OUT
|
||||
DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT
|
||||
DATA IO_DIR AMIGA_BUS_ENABLE_HIGH:OUT
|
||||
DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT
|
||||
DATA IO_DIR AS_000:BI
|
||||
DATA IO_DIR AS_030:BI
|
||||
DATA IO_DIR AVEC:OUT
|
||||
DATA IO_DIR A_16_:IN
|
||||
DATA IO_DIR A_17_:IN
|
||||
DATA IO_DIR A_18_:IN
|
||||
DATA IO_DIR A_19_:IN
|
||||
DATA IO_DIR A_20_:IN
|
||||
DATA IO_DIR A_21_:IN
|
||||
DATA IO_DIR A_22_:IN
|
||||
DATA IO_DIR A_23_:IN
|
||||
DATA IO_DIR A_24_:IN
|
||||
DATA IO_DIR A_25_:IN
|
||||
DATA IO_DIR A_26_:IN
|
||||
DATA IO_DIR A_27_:IN
|
||||
DATA IO_DIR A_28_:IN
|
||||
DATA IO_DIR A_29_:IN
|
||||
DATA IO_DIR A_30_:IN
|
||||
DATA IO_DIR A_31_:IN
|
||||
DATA IO_DIR BERR:BI
|
||||
DATA IO_DIR BGACK_000:IN
|
||||
DATA IO_DIR BGACK_030:OUT
|
||||
DATA IO_DIR BG_000:OUT
|
||||
DATA IO_DIR BG_030:IN
|
||||
DATA IO_DIR CIIN:OUT
|
||||
DATA IO_DIR CLK_000:IN
|
||||
DATA IO_DIR CLK_030:IN
|
||||
DATA IO_DIR CLK_DIV_OUT:OUT
|
||||
DATA IO_DIR CLK_EXP:OUT
|
||||
DATA IO_DIR CLK_OSZI:IN
|
||||
DATA IO_DIR DSACK1:OUT
|
||||
DATA IO_DIR DS_030:BI
|
||||
DATA IO_DIR DTACK:IN
|
||||
DATA IO_DIR E:OUT
|
||||
DATA IO_DIR FC_0_:IN
|
||||
DATA IO_DIR FC_1_:IN
|
||||
DATA IO_DIR FPU_CS:OUT
|
||||
DATA IO_DIR FPU_SENSE:IN
|
||||
DATA IO_DIR IPL_030_0_:OUT
|
||||
DATA IO_DIR IPL_030_1_:OUT
|
||||
DATA IO_DIR IPL_030_2_:OUT
|
||||
DATA IO_DIR IPL_0_:IN
|
||||
DATA IO_DIR IPL_1_:IN
|
||||
DATA IO_DIR IPL_2_:IN
|
||||
DATA IO_DIR LDS_000:BI
|
||||
DATA IO_DIR RESET:OUT
|
||||
DATA IO_DIR RST:IN
|
||||
DATA IO_DIR RW:BI
|
||||
DATA IO_DIR RW_000:BI
|
||||
DATA IO_DIR SIZE_0_:BI
|
||||
DATA IO_DIR SIZE_1_:BI
|
||||
DATA IO_DIR UDS_000:BI
|
||||
DATA IO_DIR VMA:OUT
|
||||
DATA IO_DIR VPA:IN
|
||||
DATA IO_DIR nEXP_SPACE:IN
|
||||
DATA GLB_CLOCK CLK_OSZI
|
||||
DATA PW_LEVEL A_28_:1
|
||||
DATA SLEW A_28_:1
|
||||
DATA PW_LEVEL A_27_:1
|
||||
DATA SLEW A_27_:1
|
||||
DATA PW_LEVEL SIZE_1_:1
|
||||
DATA SLEW SIZE_1_:1
|
||||
DATA PW_LEVEL A_26_:1
|
||||
DATA SLEW A_26_:1
|
||||
DATA PW_LEVEL A_25_:1
|
||||
DATA SLEW A_25_:1
|
||||
DATA PW_LEVEL A_31_:1
|
||||
DATA SLEW A_31_:1
|
||||
DATA PW_LEVEL A_24_:1
|
||||
DATA SLEW A_24_:1
|
||||
DATA PW_LEVEL A_23_:1
|
||||
DATA SLEW A_23_:1
|
||||
DATA PW_LEVEL A_22_:1
|
||||
DATA SLEW A_22_:1
|
||||
DATA PW_LEVEL A_21_:1
|
||||
DATA SLEW A_21_:1
|
||||
DATA PW_LEVEL IPL_2_:1
|
||||
DATA SLEW IPL_2_:1
|
||||
DATA PW_LEVEL A_20_:1
|
||||
DATA SLEW A_20_:1
|
||||
DATA PW_LEVEL A_19_:1
|
||||
DATA SLEW A_19_:1
|
||||
DATA PW_LEVEL FC_1_:1
|
||||
DATA SLEW FC_1_:1
|
||||
DATA PW_LEVEL A_18_:1
|
||||
DATA SLEW A_18_:1
|
||||
DATA PW_LEVEL AS_030:1
|
||||
DATA SLEW AS_030:1
|
||||
DATA PW_LEVEL A_17_:1
|
||||
DATA SLEW A_17_:1
|
||||
DATA PW_LEVEL AS_000:1
|
||||
DATA SLEW AS_000:1
|
||||
DATA PW_LEVEL A_16_:1
|
||||
DATA SLEW A_16_:1
|
||||
DATA PW_LEVEL DS_030:1
|
||||
DATA SLEW DS_030:1
|
||||
DATA PW_LEVEL UDS_000:1
|
||||
DATA SLEW UDS_000:1
|
||||
DATA PW_LEVEL LDS_000:1
|
||||
DATA SLEW LDS_000:1
|
||||
DATA PW_LEVEL A1:1
|
||||
DATA SLEW A1:1
|
||||
DATA SLEW nEXP_SPACE:1
|
||||
DATA PW_LEVEL BERR:1
|
||||
DATA SLEW BERR:1
|
||||
DATA PW_LEVEL BG_030:1
|
||||
DATA SLEW BG_030:1
|
||||
DATA PW_LEVEL BGACK_000:1
|
||||
DATA SLEW BGACK_000:1
|
||||
DATA SLEW CLK_030:1
|
||||
DATA SLEW CLK_000:1
|
||||
DATA SLEW CLK_OSZI:1
|
||||
DATA PW_LEVEL CLK_DIV_OUT:1
|
||||
DATA SLEW CLK_DIV_OUT:0
|
||||
DATA PW_LEVEL CLK_EXP:1
|
||||
DATA SLEW CLK_EXP:0
|
||||
DATA PW_LEVEL IPL_1_:1
|
||||
DATA SLEW IPL_1_:1
|
||||
DATA PW_LEVEL FPU_CS:1
|
||||
DATA SLEW FPU_CS:0
|
||||
DATA PW_LEVEL IPL_0_:1
|
||||
DATA SLEW IPL_0_:1
|
||||
DATA PW_LEVEL FPU_SENSE:1
|
||||
DATA SLEW FPU_SENSE:1
|
||||
DATA PW_LEVEL FC_0_:1
|
||||
DATA SLEW FC_0_:1
|
||||
DATA PW_LEVEL DTACK:1
|
||||
DATA SLEW DTACK:1
|
||||
DATA PW_LEVEL AVEC:1
|
||||
DATA SLEW AVEC:1
|
||||
DATA SLEW VPA:1
|
||||
DATA SLEW RST:1
|
||||
DATA PW_LEVEL AMIGA_ADDR_ENABLE:1
|
||||
DATA SLEW AMIGA_ADDR_ENABLE:0
|
||||
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
|
||||
DATA SLEW AMIGA_BUS_DATA_DIR:0
|
||||
DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1
|
||||
DATA SLEW AMIGA_BUS_ENABLE_LOW:0
|
||||
DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
|
||||
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
|
||||
DATA PW_LEVEL CIIN:1
|
||||
DATA SLEW CIIN:1
|
||||
DATA PW_LEVEL SIZE_0_:1
|
||||
DATA SLEW SIZE_0_:1
|
||||
DATA PW_LEVEL A_30_:1
|
||||
DATA SLEW A_30_:1
|
||||
DATA PW_LEVEL A_29_:1
|
||||
DATA SLEW A_29_:1
|
||||
DATA PW_LEVEL IPL_030_2_:1
|
||||
DATA SLEW IPL_030_2_:1
|
||||
DATA PW_LEVEL RW_000:1
|
||||
DATA SLEW RW_000:1
|
||||
DATA PW_LEVEL A0:1
|
||||
DATA SLEW A0:1
|
||||
DATA PW_LEVEL BG_000:1
|
||||
DATA SLEW BG_000:1
|
||||
DATA PW_LEVEL BGACK_030:1
|
||||
DATA SLEW BGACK_030:1
|
||||
DATA PW_LEVEL IPL_030_1_:1
|
||||
DATA SLEW IPL_030_1_:1
|
||||
DATA PW_LEVEL IPL_030_0_:1
|
||||
DATA SLEW IPL_030_0_:1
|
||||
DATA PW_LEVEL DSACK1:1
|
||||
DATA SLEW DSACK1:1
|
||||
DATA PW_LEVEL E:1
|
||||
DATA SLEW E:1
|
||||
DATA PW_LEVEL VMA:1
|
||||
DATA SLEW VMA:1
|
||||
DATA PW_LEVEL RESET:1
|
||||
DATA SLEW RESET:1
|
||||
DATA PW_LEVEL RW:1
|
||||
DATA SLEW RW:1
|
||||
DATA PW_LEVEL cpu_est_0_:1
|
||||
DATA SLEW cpu_est_0_:1
|
||||
DATA PW_LEVEL cpu_est_1_:1
|
||||
DATA SLEW cpu_est_1_:1
|
||||
DATA PW_LEVEL inst_AS_000_INT:1
|
||||
DATA SLEW inst_AS_000_INT:1
|
||||
DATA PW_LEVEL SM_AMIGA_5_:1
|
||||
DATA SLEW SM_AMIGA_5_:1
|
||||
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1
|
||||
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_LOW:1
|
||||
DATA PW_LEVEL inst_AS_030_D0:1
|
||||
DATA SLEW inst_AS_030_D0:1
|
||||
DATA PW_LEVEL inst_nEXP_SPACE_D0reg:1
|
||||
DATA SLEW inst_nEXP_SPACE_D0reg:1
|
||||
DATA PW_LEVEL inst_DS_030_D0:1
|
||||
DATA SLEW inst_DS_030_D0:1
|
||||
DATA PW_LEVEL inst_AS_030_000_SYNC:1
|
||||
DATA SLEW inst_AS_030_000_SYNC:1
|
||||
DATA PW_LEVEL inst_BGACK_030_INT_D:1
|
||||
DATA SLEW inst_BGACK_030_INT_D:1
|
||||
DATA PW_LEVEL inst_AS_000_DMA:1
|
||||
DATA SLEW inst_AS_000_DMA:1
|
||||
DATA PW_LEVEL inst_DS_000_DMA:1
|
||||
DATA SLEW inst_DS_000_DMA:1
|
||||
DATA PW_LEVEL CYCLE_DMA_0_:1
|
||||
DATA SLEW CYCLE_DMA_0_:1
|
||||
DATA PW_LEVEL CYCLE_DMA_1_:1
|
||||
DATA SLEW CYCLE_DMA_1_:1
|
||||
DATA PW_LEVEL SIZE_DMA_0_:1
|
||||
DATA SLEW SIZE_DMA_0_:1
|
||||
DATA PW_LEVEL SIZE_DMA_1_:1
|
||||
DATA SLEW SIZE_DMA_1_:1
|
||||
DATA PW_LEVEL inst_VPA_D:1
|
||||
DATA SLEW inst_VPA_D:1
|
||||
DATA PW_LEVEL inst_UDS_000_INT:1
|
||||
DATA SLEW inst_UDS_000_INT:1
|
||||
DATA PW_LEVEL inst_LDS_000_INT:1
|
||||
DATA SLEW inst_LDS_000_INT:1
|
||||
DATA PW_LEVEL inst_CLK_OUT_PRE_D:1
|
||||
DATA SLEW inst_CLK_OUT_PRE_D:1
|
||||
DATA PW_LEVEL inst_DTACK_D0:1
|
||||
DATA SLEW inst_DTACK_D0:1
|
||||
DATA PW_LEVEL inst_CLK_OUT_PRE_50:1
|
||||
DATA SLEW inst_CLK_OUT_PRE_50:1
|
||||
DATA PW_LEVEL inst_CLK_000_D1:1
|
||||
DATA SLEW inst_CLK_000_D1:1
|
||||
DATA PW_LEVEL inst_CLK_000_D0:1
|
||||
DATA SLEW inst_CLK_000_D0:1
|
||||
DATA PW_LEVEL inst_CLK_000_PE:1
|
||||
DATA SLEW inst_CLK_000_PE:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_9_:1
|
||||
DATA SLEW CLK_000_P_SYNC_9_:1
|
||||
DATA PW_LEVEL inst_CLK_000_NE:1
|
||||
DATA SLEW inst_CLK_000_NE:1
|
||||
DATA PW_LEVEL N_96_i:1
|
||||
DATA SLEW N_96_i:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_11_:1
|
||||
DATA SLEW CLK_000_N_SYNC_11_:1
|
||||
DATA PW_LEVEL cpu_est_2_:1
|
||||
DATA SLEW cpu_est_2_:1
|
||||
DATA PW_LEVEL IPL_D0_0_:1
|
||||
DATA SLEW IPL_D0_0_:1
|
||||
DATA PW_LEVEL IPL_D0_1_:1
|
||||
DATA SLEW IPL_D0_1_:1
|
||||
DATA PW_LEVEL IPL_D0_2_:1
|
||||
DATA SLEW IPL_D0_2_:1
|
||||
DATA PW_LEVEL SM_AMIGA_3_:1
|
||||
DATA SLEW SM_AMIGA_3_:1
|
||||
DATA PW_LEVEL inst_CLK_000_NE_D0:1
|
||||
DATA SLEW inst_CLK_000_NE_D0:1
|
||||
DATA PW_LEVEL SM_AMIGA_0_:1
|
||||
DATA SLEW SM_AMIGA_0_:1
|
||||
DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
|
||||
DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
|
||||
DATA PW_LEVEL SM_AMIGA_6_:1
|
||||
DATA SLEW SM_AMIGA_6_:1
|
||||
DATA PW_LEVEL RST_DLY_0_:1
|
||||
DATA SLEW RST_DLY_0_:1
|
||||
DATA PW_LEVEL RST_DLY_1_:1
|
||||
DATA SLEW RST_DLY_1_:1
|
||||
DATA PW_LEVEL RST_DLY_2_:1
|
||||
DATA SLEW RST_DLY_2_:1
|
||||
DATA PW_LEVEL RST_DLY_3_:1
|
||||
DATA SLEW RST_DLY_3_:1
|
||||
DATA PW_LEVEL RST_DLY_4_:1
|
||||
DATA SLEW RST_DLY_4_:1
|
||||
DATA PW_LEVEL RST_DLY_5_:1
|
||||
DATA SLEW RST_DLY_5_:1
|
||||
DATA PW_LEVEL RST_DLY_6_:1
|
||||
DATA SLEW RST_DLY_6_:1
|
||||
DATA PW_LEVEL RST_DLY_7_:1
|
||||
DATA SLEW RST_DLY_7_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_0_:1
|
||||
DATA SLEW CLK_000_P_SYNC_0_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_1_:1
|
||||
DATA SLEW CLK_000_P_SYNC_1_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_2_:1
|
||||
DATA SLEW CLK_000_P_SYNC_2_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_3_:1
|
||||
DATA SLEW CLK_000_P_SYNC_3_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_4_:1
|
||||
DATA SLEW CLK_000_P_SYNC_4_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_5_:1
|
||||
DATA SLEW CLK_000_P_SYNC_5_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_6_:1
|
||||
DATA SLEW CLK_000_P_SYNC_6_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_7_:1
|
||||
DATA SLEW CLK_000_P_SYNC_7_:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_8_:1
|
||||
DATA SLEW CLK_000_P_SYNC_8_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_0_:1
|
||||
DATA SLEW CLK_000_N_SYNC_0_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_1_:1
|
||||
DATA SLEW CLK_000_N_SYNC_1_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_2_:1
|
||||
DATA SLEW CLK_000_N_SYNC_2_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_3_:1
|
||||
DATA SLEW CLK_000_N_SYNC_3_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_4_:1
|
||||
DATA SLEW CLK_000_N_SYNC_4_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_5_:1
|
||||
DATA SLEW CLK_000_N_SYNC_5_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_6_:1
|
||||
DATA SLEW CLK_000_N_SYNC_6_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_7_:1
|
||||
DATA SLEW CLK_000_N_SYNC_7_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_8_:1
|
||||
DATA SLEW CLK_000_N_SYNC_8_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_9_:1
|
||||
DATA SLEW CLK_000_N_SYNC_9_:1
|
||||
DATA PW_LEVEL CLK_000_N_SYNC_10_:1
|
||||
DATA SLEW CLK_000_N_SYNC_10_:1
|
||||
DATA PW_LEVEL inst_CLK_030_H:1
|
||||
DATA SLEW inst_CLK_030_H:1
|
||||
DATA PW_LEVEL SM_AMIGA_1_:1
|
||||
DATA SLEW SM_AMIGA_1_:1
|
||||
DATA PW_LEVEL SM_AMIGA_4_:1
|
||||
DATA SLEW SM_AMIGA_4_:1
|
||||
DATA PW_LEVEL SM_AMIGA_2_:1
|
||||
DATA SLEW SM_AMIGA_2_:1
|
||||
DATA PW_LEVEL inst_DS_000_ENABLE:1
|
||||
DATA SLEW inst_DS_000_ENABLE:1
|
||||
DATA PW_LEVEL SM_AMIGA_i_7_:1
|
||||
DATA SLEW SM_AMIGA_i_7_:1
|
||||
DATA PW_LEVEL CIIN_0:1
|
||||
DATA SLEW CIIN_0:1
|
||||
DATA PW_LEVEL RN_IPL_030_2_:1
|
||||
DATA PW_LEVEL RN_RW_000:1
|
||||
DATA PW_LEVEL RN_A0:1
|
||||
DATA PW_LEVEL RN_BG_000:1
|
||||
DATA PW_LEVEL RN_BGACK_030:1
|
||||
DATA PW_LEVEL RN_IPL_030_1_:1
|
||||
DATA PW_LEVEL RN_IPL_030_0_:1
|
||||
DATA PW_LEVEL RN_DSACK1:1
|
||||
DATA PW_LEVEL RN_E:1
|
||||
DATA PW_LEVEL RN_VMA:1
|
||||
DATA PW_LEVEL RN_RESET:1
|
||||
DATA PW_LEVEL RN_RW:1
|
||||
END
|
||||
|
|
@ -0,0 +1,28 @@
|
|||
|
||||
GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H RST_DLY_3_ RST_DLY_1_ RST_DLY_4_
|
||||
inst_AS_000_DMA CYCLE_DMA_1_ CYCLE_DMA_0_ inst_DS_030_D0 CLK_000_P_SYNC_9_
|
||||
CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_8_
|
||||
DS_030 AVEC
|
||||
GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_
|
||||
IPL_030_2_ RN_IPL_030_2_ RST_DLY_0_ RST_DLY_2_ RST_DLY_5_ RST_DLY_6_
|
||||
RST_DLY_7_ SM_AMIGA_0_ inst_VPA_D IPL_D0_0_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
|
||||
CLK_000_N_SYNC_1_ CLK_EXP
|
||||
GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_LDS_000_INT inst_UDS_000_INT
|
||||
inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
inst_DTACK_D0 CLK_000_N_SYNC_5_ AMIGA_BUS_ENABLE_LOW
|
||||
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 cpu_est_1_ cpu_est_2_ CLK_000_P_SYNC_0_
|
||||
CLK_000_N_SYNC_0_ inst_CLK_000_D0 CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
|
||||
CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ inst_CLK_000_NE_D0 LDS_000 UDS_000
|
||||
AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE
|
||||
GROUP MACH_SEG_E inst_CLK_000_NE inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50
|
||||
CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
|
||||
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_6_ inst_DS_000_ENABLE
|
||||
SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_0_ inst_CLK_000_PE N_96_i
|
||||
|
||||
GROUP MACH_SEG_G A0 RN_A0 RW RN_RW E RN_E SIZE_DMA_0_ SIZE_DMA_1_ inst_nEXP_SPACE_D0reg
|
||||
IPL_D0_1_ IPL_D0_2_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_5_
|
||||
CLK_000_P_SYNC_6_ CLK_000_N_SYNC_9_ inst_CLK_000_D1 SIZE_0_ CLK_DIV_OUT
|
||||
|
||||
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030
|
||||
inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_
|
||||
FPU_CS AS_030 SIZE_1_
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
No pin assignment or valid property.
|
||||
No source constraints were imported.
|
||||
|
|
@ -1 +1 @@
|
|||
<LATTICE_ENCRYPTED_BLIF>8775301*z5Kd
|
||||
<LATTICE_ENCRYPTED_BLIF>2753107yCgL9*V
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1 @@
|
|||
-ck Min -ce On -ar On -ap On -oe On -split 16 -clust 5 -xor on -speed -ifb yes -sr no -device M4A5
|
||||
|
|
@ -0,0 +1,259 @@
|
|||
[DEVICE]
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = No;
|
||||
Pin_MC_1to1 = No;
|
||||
EN_PinReserve_IO = Yes;
|
||||
EN_PinReserve_BIDIR = Yes;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
DATE = 5/13/15;
|
||||
TIME = 22:59:29;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
Pin_Block = No;
|
||||
Pin_Macrocell_Block = No;
|
||||
Routing = No;
|
||||
|
||||
[GLOBAL CONSTRAINTS]
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_GLB_Input_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Logic_Reduction = Yes;
|
||||
XOR_Synthesis = Yes;
|
||||
DT_Synthesis = Yes;
|
||||
Node_Collapse = Yes;
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = No;
|
||||
Clock_Optimize = No;
|
||||
In_Reg_Optimize = Yes;
|
||||
Balanced_Partitioning = Yes;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode = 0;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[LOCATION ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
A_28_ = pin,15,-,C,-;
|
||||
A_27_ = pin,16,-,C,-;
|
||||
SIZE_1_ = pin,79,-,H,-;
|
||||
A_26_ = pin,17,-,C,-;
|
||||
A_25_ = pin,18,-,C,-;
|
||||
A_31_ = pin,4,-,B,-;
|
||||
A_24_ = pin,19,-,C,-;
|
||||
A_23_ = pin,85,-,H,-;
|
||||
A_22_ = pin,84,-,H,-;
|
||||
A_21_ = pin,94,-,A,-;
|
||||
IPL_2_ = pin,68,-,G,-;
|
||||
A_20_ = pin,93,-,A,-;
|
||||
A_19_ = pin,97,-,A,-;
|
||||
FC_1_ = pin,58,-,F,-;
|
||||
A_18_ = pin,95,-,A,-;
|
||||
AS_030 = pin,82,-,H,-;
|
||||
A_17_ = pin,59,-,F,-;
|
||||
AS_000 = pin,42,-,E,-;
|
||||
A_16_ = pin,96,-,A,-;
|
||||
DS_030 = pin,98,-,A,-;
|
||||
UDS_000 = pin,32,-,D,-;
|
||||
LDS_000 = pin,31,-,D,-;
|
||||
A1 = pin,60,-,F,-;
|
||||
nEXP_SPACE = pin,14,-,-,-;
|
||||
BERR = pin,41,-,E,-;
|
||||
BG_030 = pin,21,-,C,-;
|
||||
BGACK_000 = pin,28,-,D,-;
|
||||
CLK_030 = pin,64,-,-,-;
|
||||
CLK_000 = pin,11,-,-,-;
|
||||
CLK_OSZI = pin,61,-,-,-;
|
||||
CLK_DIV_OUT = pin,65,-,G,-;
|
||||
CLK_EXP = pin,10,-,B,-;
|
||||
IPL_1_ = pin,56,-,F,-;
|
||||
FPU_CS = pin,78,-,H,-;
|
||||
IPL_0_ = pin,67,-,G,-;
|
||||
FPU_SENSE = pin,91,-,A,-;
|
||||
FC_0_ = pin,57,-,F,-;
|
||||
DTACK = pin,30,-,D,-;
|
||||
AVEC = pin,92,-,A,-;
|
||||
VPA = pin,36,-,-,-;
|
||||
RST = pin,86,-,-,-;
|
||||
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
|
||||
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
|
||||
CIIN = pin,47,-,E,-;
|
||||
SIZE_0_ = pin,70,-,G,-;
|
||||
A_30_ = pin,5,-,B,-;
|
||||
A_29_ = pin,6,-,B,-;
|
||||
IPL_030_2_ = pin,9,-,B,-;
|
||||
RW_000 = pin,80,-,H,-;
|
||||
A0 = pin,69,-,G,-;
|
||||
BG_000 = pin,29,-,D,-;
|
||||
BGACK_030 = pin,83,-,H,-;
|
||||
IPL_030_1_ = pin,7,-,B,-;
|
||||
IPL_030_0_ = pin,8,-,B,-;
|
||||
DSACK1 = pin,81,-,H,-;
|
||||
E = pin,66,-,G,-;
|
||||
VMA = pin,35,-,D,-;
|
||||
RESET = pin,3,-,B,-;
|
||||
RW = pin,71,-,G,-;
|
||||
cpu_est_0_ = node,-,-,F,1;
|
||||
cpu_est_1_ = node,-,-,D,9;
|
||||
inst_AS_000_INT = node,-,-,C,5;
|
||||
SM_AMIGA_5_ = node,-,-,F,12;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,9;
|
||||
inst_AS_030_D0 = node,-,-,H,5;
|
||||
inst_nEXP_SPACE_D0reg = node,-,-,G,5;
|
||||
inst_DS_030_D0 = node,-,-,A,15;
|
||||
inst_AS_030_000_SYNC = node,-,-,C,4;
|
||||
inst_BGACK_030_INT_D = node,-,-,H,13;
|
||||
inst_AS_000_DMA = node,-,-,A,8;
|
||||
inst_DS_000_DMA = node,-,-,A,9;
|
||||
CYCLE_DMA_0_ = node,-,-,A,6;
|
||||
CYCLE_DMA_1_ = node,-,-,A,2;
|
||||
SIZE_DMA_0_ = node,-,-,G,13;
|
||||
SIZE_DMA_1_ = node,-,-,G,9;
|
||||
inst_VPA_D = node,-,-,B,14;
|
||||
inst_UDS_000_INT = node,-,-,C,12;
|
||||
inst_LDS_000_INT = node,-,-,C,8;
|
||||
inst_CLK_OUT_PRE_D = node,-,-,E,13;
|
||||
inst_DTACK_D0 = node,-,-,C,2;
|
||||
inst_CLK_OUT_PRE_50 = node,-,-,E,9;
|
||||
inst_CLK_000_D1 = node,-,-,G,2;
|
||||
inst_CLK_000_D0 = node,-,-,D,6;
|
||||
inst_CLK_000_PE = node,-,-,F,0;
|
||||
CLK_000_P_SYNC_9_ = node,-,-,A,11;
|
||||
inst_CLK_000_NE = node,-,-,E,8;
|
||||
N_96_i = node,-,-,F,6;
|
||||
CLK_000_N_SYNC_11_ = node,-,-,H,6;
|
||||
cpu_est_2_ = node,-,-,D,13;
|
||||
IPL_D0_0_ = node,-,-,B,15;
|
||||
IPL_D0_1_ = node,-,-,G,15;
|
||||
IPL_D0_2_ = node,-,-,G,11;
|
||||
SM_AMIGA_3_ = node,-,-,F,13;
|
||||
inst_CLK_000_NE_D0 = node,-,-,D,2;
|
||||
SM_AMIGA_0_ = node,-,-,B,5;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,C,1;
|
||||
SM_AMIGA_6_ = node,-,-,F,9;
|
||||
RST_DLY_0_ = node,-,-,B,6;
|
||||
RST_DLY_1_ = node,-,-,A,1;
|
||||
RST_DLY_2_ = node,-,-,B,9;
|
||||
RST_DLY_3_ = node,-,-,A,12;
|
||||
RST_DLY_4_ = node,-,-,A,5;
|
||||
RST_DLY_5_ = node,-,-,B,13;
|
||||
RST_DLY_6_ = node,-,-,B,2;
|
||||
RST_DLY_7_ = node,-,-,B,10;
|
||||
CLK_000_P_SYNC_0_ = node,-,-,D,15;
|
||||
CLK_000_P_SYNC_1_ = node,-,-,G,7;
|
||||
CLK_000_P_SYNC_2_ = node,-,-,G,3;
|
||||
CLK_000_P_SYNC_3_ = node,-,-,B,11;
|
||||
CLK_000_P_SYNC_4_ = node,-,-,B,7;
|
||||
CLK_000_P_SYNC_5_ = node,-,-,G,14;
|
||||
CLK_000_P_SYNC_6_ = node,-,-,G,10;
|
||||
CLK_000_P_SYNC_7_ = node,-,-,A,7;
|
||||
CLK_000_P_SYNC_8_ = node,-,-,A,3;
|
||||
CLK_000_N_SYNC_0_ = node,-,-,D,11;
|
||||
CLK_000_N_SYNC_1_ = node,-,-,B,3;
|
||||
CLK_000_N_SYNC_2_ = node,-,-,D,7;
|
||||
CLK_000_N_SYNC_3_ = node,-,-,D,3;
|
||||
CLK_000_N_SYNC_4_ = node,-,-,A,14;
|
||||
CLK_000_N_SYNC_5_ = node,-,-,C,13;
|
||||
CLK_000_N_SYNC_6_ = node,-,-,D,14;
|
||||
CLK_000_N_SYNC_7_ = node,-,-,D,10;
|
||||
CLK_000_N_SYNC_8_ = node,-,-,A,10;
|
||||
CLK_000_N_SYNC_9_ = node,-,-,G,6;
|
||||
CLK_000_N_SYNC_10_ = node,-,-,H,2;
|
||||
inst_CLK_030_H = node,-,-,A,13;
|
||||
SM_AMIGA_1_ = node,-,-,F,8;
|
||||
SM_AMIGA_4_ = node,-,-,F,10;
|
||||
SM_AMIGA_2_ = node,-,-,F,2;
|
||||
inst_DS_000_ENABLE = node,-,-,F,5;
|
||||
SM_AMIGA_i_7_ = node,-,-,F,4;
|
||||
CIIN_0 = node,-,-,E,5;
|
||||
|
||||
[GROUP ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
|
||||
[RESOURCE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[SLEWRATE]
|
||||
Default = SLOW;
|
||||
FAST = CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH;
|
||||
|
||||
[PULLUP]
|
||||
Default = Up;
|
||||
|
||||
[NETLIST/DELAY FORMAT]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
|
||||
[OSM BYPASS]
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Prefit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
||||
|
|
@ -0,0 +1,728 @@
|
|||
|
||||
135 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
||||
79 RW_000 5 358 7 3 0 4 6 79 -1 3 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
70 RW 5 366 6 2 2 7 70 -1 2 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 359 6 1 0 68 -1 3 0 21
|
||||
97 DS_030 5 -1 0 1 3 97 -1 1 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
||||
65 E 5 363 6 0 65 -1 5 0 21
|
||||
80 DSACK1 5 362 7 0 80 -1 4 0 21
|
||||
34 VMA 5 364 3 0 34 -1 3 0 21
|
||||
82 BGACK_030 5 361 7 0 82 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 360 3 0 28 -1 2 0 21
|
||||
8 IPL_030_2_ 5 355 1 0 8 -1 2 0 21
|
||||
7 IPL_030_0_ 5 357 1 0 7 -1 2 0 21
|
||||
6 IPL_030_1_ 5 356 1 0 6 -1 2 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
2 RESET 5 365 1 0 2 -1 1 0 21
|
||||
361 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 2 0 21
|
||||
299 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 1 3 4 5 6 7 -1 -1 1 0 21
|
||||
298 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21
|
||||
365 RN_RESET 3 2 1 5 0 3 4 6 7 2 -1 1 0 21
|
||||
319 inst_CLK_000_NE 3 -1 1 5 1 2 3 5 7 -1 -1 1 0 21
|
||||
317 inst_CLK_000_PE 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21
|
||||
352 SM_AMIGA_i_7_ 3 -1 5 4 1 3 5 7 -1 -1 15 0 21
|
||||
323 inst_CLK_000_NE_D0 3 -1 7 4 2 3 5 6 -1 -1 1 0 21
|
||||
363 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21
|
||||
294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21
|
||||
321 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
||||
348 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21
|
||||
296 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
||||
293 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21
|
||||
312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
||||
309 inst_VPA_D 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
||||
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
301 inst_AS_030_000_SYNC 3 -1 1 2 1 5 -1 -1 7 0 21
|
||||
322 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
||||
350 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
||||
311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21
|
||||
364 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
351 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
349 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
||||
326 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
||||
310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
||||
324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
||||
295 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
||||
345 CLK_000_N_SYNC_9_ 3 -1 6 2 1 7 -1 -1 1 0 21
|
||||
316 inst_CLK_000_D0 3 -1 1 2 3 5 -1 -1 1 0 21
|
||||
315 inst_CLK_000_D1 3 -1 5 2 3 5 -1 -1 1 0 21
|
||||
313 inst_DTACK_D0 3 -1 2 2 2 5 -1 -1 1 0 21
|
||||
302 inst_BGACK_030_INT_D 3 -1 7 2 1 6 -1 -1 1 0 21
|
||||
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
347 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
359 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
358 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
366 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
357 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21
|
||||
356 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21
|
||||
355 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21
|
||||
354 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
353 N_302 3 -1 2 1 5 -1 -1 1 0 21
|
||||
346 CLK_000_N_SYNC_10_ 3 -1 1 1 7 -1 -1 1 0 21
|
||||
344 CLK_000_N_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
343 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
342 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21
|
||||
341 CLK_000_N_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21
|
||||
340 CLK_000_N_SYNC_4_ 3 -1 5 1 2 -1 -1 1 0 21
|
||||
339 CLK_000_N_SYNC_3_ 3 -1 5 1 5 -1 -1 1 0 21
|
||||
338 CLK_000_N_SYNC_2_ 3 -1 1 1 5 -1 -1 1 0 21
|
||||
337 CLK_000_N_SYNC_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
336 CLK_000_N_SYNC_0_ 3 -1 3 1 5 -1 -1 1 0 21
|
||||
335 CLK_000_P_SYNC_8_ 3 -1 3 1 3 -1 -1 1 0 21
|
||||
334 CLK_000_P_SYNC_7_ 3 -1 4 1 3 -1 -1 1 0 21
|
||||
333 CLK_000_P_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21
|
||||
332 CLK_000_P_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21
|
||||
331 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21
|
||||
330 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
329 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21
|
||||
328 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
327 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
320 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21
|
||||
318 CLK_000_P_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
||||
300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 1 4 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 1 4 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 1 4 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 1 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
||||
59 A1 1 -1 -1 1 6 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 6 35 -1
|
||||
29 DTACK 1 -1 -1 1 2 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
||||
10 CLK_000 1 -1 -1 1 1 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
135 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
||||
79 RW_000 5 358 7 3 0 4 6 79 -1 3 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
70 RW 5 366 6 2 2 7 70 -1 2 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 359 6 1 0 68 -1 3 0 21
|
||||
97 DS_030 5 -1 0 1 3 97 -1 1 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
||||
65 E 5 363 6 0 65 -1 5 0 21
|
||||
80 DSACK1 5 362 7 0 80 -1 4 0 21
|
||||
34 VMA 5 364 3 0 34 -1 3 0 21
|
||||
82 BGACK_030 5 361 7 0 82 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 360 3 0 28 -1 2 0 21
|
||||
8 IPL_030_2_ 5 355 1 0 8 -1 2 0 21
|
||||
7 IPL_030_0_ 5 357 1 0 7 -1 2 0 21
|
||||
6 IPL_030_1_ 5 356 1 0 6 -1 2 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
2 RESET 5 365 1 0 2 -1 1 0 21
|
||||
361 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 2 0 21
|
||||
299 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 1 3 4 5 6 7 -1 -1 1 0 21
|
||||
298 inst_AS_030_D0 3 -1 7 6 1 2 3 4 5 7 -1 -1 1 0 21
|
||||
365 RN_RESET 3 2 1 5 0 3 4 6 7 2 -1 1 0 21
|
||||
319 inst_CLK_000_NE 3 -1 1 5 1 2 3 5 7 -1 -1 1 0 21
|
||||
317 inst_CLK_000_PE 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21
|
||||
352 SM_AMIGA_i_7_ 3 -1 5 4 1 3 5 7 -1 -1 15 0 21
|
||||
323 inst_CLK_000_NE_D0 3 -1 7 4 2 3 5 6 -1 -1 1 0 21
|
||||
363 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21
|
||||
294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21
|
||||
321 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21
|
||||
348 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21
|
||||
296 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
||||
293 cpu_est_0_ 3 -1 3 3 2 3 6 -1 -1 2 0 21
|
||||
312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
||||
309 inst_VPA_D 3 -1 6 3 2 3 5 -1 -1 1 0 21
|
||||
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
301 inst_AS_030_000_SYNC 3 -1 1 2 1 5 -1 -1 7 0 21
|
||||
322 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21
|
||||
350 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
||||
311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21
|
||||
364 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
351 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
349 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21
|
||||
326 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 3 0 21
|
||||
310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
||||
324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
||||
295 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
||||
345 CLK_000_N_SYNC_9_ 3 -1 6 2 1 7 -1 -1 1 0 21
|
||||
316 inst_CLK_000_D0 3 -1 1 2 3 5 -1 -1 1 0 21
|
||||
315 inst_CLK_000_D1 3 -1 5 2 3 5 -1 -1 1 0 21
|
||||
313 inst_DTACK_D0 3 -1 2 2 2 5 -1 -1 1 0 21
|
||||
302 inst_BGACK_030_INT_D 3 -1 7 2 1 6 -1 -1 1 0 21
|
||||
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
347 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
359 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
358 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
366 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
357 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21
|
||||
356 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21
|
||||
355 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21
|
||||
354 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
353 N_302 3 -1 2 1 5 -1 -1 1 0 21
|
||||
346 CLK_000_N_SYNC_10_ 3 -1 1 1 7 -1 -1 1 0 21
|
||||
344 CLK_000_N_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
343 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
342 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21
|
||||
341 CLK_000_N_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21
|
||||
340 CLK_000_N_SYNC_4_ 3 -1 5 1 2 -1 -1 1 0 21
|
||||
339 CLK_000_N_SYNC_3_ 3 -1 5 1 5 -1 -1 1 0 21
|
||||
338 CLK_000_N_SYNC_2_ 3 -1 1 1 5 -1 -1 1 0 21
|
||||
337 CLK_000_N_SYNC_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
336 CLK_000_N_SYNC_0_ 3 -1 3 1 5 -1 -1 1 0 21
|
||||
335 CLK_000_P_SYNC_8_ 3 -1 3 1 3 -1 -1 1 0 21
|
||||
334 CLK_000_P_SYNC_7_ 3 -1 4 1 3 -1 -1 1 0 21
|
||||
333 CLK_000_P_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21
|
||||
332 CLK_000_P_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21
|
||||
331 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21
|
||||
330 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
329 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21
|
||||
328 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
327 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
320 CLK_000_N_SYNC_11_ 3 -1 7 1 1 -1 -1 1 0 21
|
||||
318 CLK_000_P_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
||||
300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 1 4 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 1 4 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 1 4 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 1 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 1 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 1 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
||||
59 A1 1 -1 -1 1 6 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 6 35 -1
|
||||
29 DTACK 1 -1 -1 1 2 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
||||
10 CLK_000 1 -1 -1 1 1 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
135 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21
|
||||
79 RW_000 5 358 7 3 0 4 6 79 -1 3 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
68 A0 5 359 6 2 2 6 68 -1 3 0 21
|
||||
70 RW 5 366 6 2 2 7 70 -1 2 0 21
|
||||
97 DS_030 5 -1 0 2 0 3 97 -1 1 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21
|
||||
65 E 5 363 6 0 65 -1 5 0 21
|
||||
80 DSACK1 5 362 7 0 80 -1 4 0 21
|
||||
34 VMA 5 364 3 0 34 -1 3 0 21
|
||||
82 BGACK_030 5 361 7 0 82 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 360 3 0 28 -1 2 0 21
|
||||
8 IPL_030_2_ 5 357 1 0 8 -1 2 0 21
|
||||
7 IPL_030_0_ 5 356 1 0 7 -1 2 0 21
|
||||
6 IPL_030_1_ 5 355 1 0 6 -1 2 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
2 RESET 5 365 1 0 2 -1 1 0 21
|
||||
361 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 2 0 21
|
||||
299 inst_nEXP_SPACE_D0reg 3 -1 3 7 0 1 3 4 5 6 7 -1 -1 1 0 21
|
||||
365 RN_RESET 3 2 1 5 0 3 4 6 7 2 -1 1 0 21
|
||||
317 inst_CLK_000_PE 3 -1 3 5 0 1 2 3 7 -1 -1 1 0 21
|
||||
298 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
||||
353 SM_AMIGA_i_7_ 3 -1 2 4 1 3 5 7 -1 -1 8 0 21
|
||||
296 SM_AMIGA_5_ 3 -1 1 4 1 2 5 7 -1 -1 3 0 21
|
||||
319 inst_CLK_000_NE 3 -1 3 4 0 1 3 5 -1 -1 1 0 21
|
||||
363 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21
|
||||
294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21
|
||||
351 SM_AMIGA_2_ 3 -1 2 3 0 1 2 -1 -1 4 0 21
|
||||
321 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 4 0 21
|
||||
348 SM_AMIGA_1_ 3 -1 0 3 0 1 7 -1 -1 3 0 21
|
||||
326 SM_AMIGA_6_ 3 -1 1 3 1 2 6 -1 -1 3 0 21
|
||||
324 SM_AMIGA_0_ 3 -1 1 3 1 2 7 -1 -1 2 0 21
|
||||
293 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 2 0 21
|
||||
323 inst_CLK_000_NE_D0 3 -1 5 3 2 3 6 -1 -1 1 0 21
|
||||
312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21
|
||||
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
301 inst_AS_030_000_SYNC 3 -1 5 2 1 5 -1 -1 7 0 21
|
||||
322 SM_AMIGA_3_ 3 -1 2 2 1 2 -1 -1 5 0 21
|
||||
311 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 4 0 21
|
||||
364 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
352 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
349 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21
|
||||
310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
|
||||
295 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21
|
||||
316 inst_CLK_000_D0 3 -1 5 2 1 3 -1 -1 1 0 21
|
||||
309 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21
|
||||
302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
||||
300 inst_DS_030_D0 3 -1 0 2 2 6 -1 -1 1 0 21
|
||||
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
347 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
350 N_125_i_2 3 -1 1 1 2 -1 -1 6 0 21
|
||||
362 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
359 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
358 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
366 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
360 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
357 RN_IPL_030_2_ 3 8 1 1 1 8 -1 2 0 21
|
||||
356 RN_IPL_030_0_ 3 7 1 1 1 7 -1 2 0 21
|
||||
355 RN_IPL_030_1_ 3 6 1 1 1 6 -1 2 0 21
|
||||
354 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
346 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
||||
345 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
||||
344 CLK_000_N_SYNC_8_ 3 -1 1 1 0 -1 -1 1 0 21
|
||||
343 CLK_000_N_SYNC_7_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
342 CLK_000_N_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21
|
||||
341 CLK_000_N_SYNC_5_ 3 -1 5 1 5 -1 -1 1 0 21
|
||||
340 CLK_000_N_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21
|
||||
339 CLK_000_N_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21
|
||||
338 CLK_000_N_SYNC_2_ 3 -1 1 1 5 -1 -1 1 0 21
|
||||
337 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
336 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
335 CLK_000_P_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
334 CLK_000_P_SYNC_7_ 3 -1 4 1 6 -1 -1 1 0 21
|
||||
333 CLK_000_P_SYNC_6_ 3 -1 5 1 4 -1 -1 1 0 21
|
||||
332 CLK_000_P_SYNC_5_ 3 -1 3 1 5 -1 -1 1 0 21
|
||||
331 CLK_000_P_SYNC_4_ 3 -1 3 1 3 -1 -1 1 0 21
|
||||
330 CLK_000_P_SYNC_3_ 3 -1 2 1 3 -1 -1 1 0 21
|
||||
329 CLK_000_P_SYNC_2_ 3 -1 6 1 2 -1 -1 1 0 21
|
||||
328 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
327 CLK_000_P_SYNC_0_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
320 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21
|
||||
318 CLK_000_P_SYNC_9_ 3 -1 0 1 3 -1 -1 1 0 21
|
||||
315 inst_CLK_000_D1 3 -1 3 1 1 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
||||
313 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
||||
59 A1 1 -1 -1 1 5 59 -1
|
||||
55 IPL_1_ 1 -1 -1 1 1 55 -1
|
||||
35 VPA 1 -1 -1 1 0 35 -1
|
||||
29 DTACK 1 -1 -1 1 6 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 3 13 -1
|
||||
10 CLK_000 1 -1 -1 1 5 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
146 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
40 BERR 5 -1 4 6 1 2 3 5 6 7 40 -1 1 0 21
|
||||
79 RW_000 5 367 7 3 0 4 6 79 -1 3 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
70 RW 5 377 6 2 3 7 70 -1 2 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 368 6 1 0 68 -1 3 0 21
|
||||
97 DS_030 5 -1 0 1 3 97 -1 1 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
||||
8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21
|
||||
65 E 5 374 6 0 65 -1 5 0 21
|
||||
80 DSACK1 5 373 7 0 80 -1 4 0 21
|
||||
34 VMA 5 375 3 0 34 -1 3 0 21
|
||||
82 BGACK_030 5 371 7 0 82 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 369 3 0 28 -1 2 0 21
|
||||
2 RESET 5 376 1 0 2 -1 2 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
371 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 2 0 21
|
||||
376 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21
|
||||
317 inst_CLK_000_PE 3 -1 2 6 0 1 2 3 5 7 -1 -1 1 0 21
|
||||
299 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21
|
||||
296 SM_AMIGA_5_ 3 -1 1 5 1 3 5 6 7 -1 -1 3 0 21
|
||||
298 inst_AS_030_D0 3 -1 7 5 3 4 5 6 7 -1 -1 1 0 21
|
||||
319 inst_CLK_000_NE 3 -1 0 4 1 2 3 5 -1 -1 1 0 21
|
||||
364 SM_AMIGA_i_7_ 3 -1 5 3 3 5 7 -1 -1 13 0 21
|
||||
374 RN_E 3 65 6 3 2 3 6 65 -1 5 0 21
|
||||
325 SM_AMIGA_3_ 3 -1 2 3 2 3 5 -1 -1 5 0 21
|
||||
294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 5 0 21
|
||||
321 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21
|
||||
361 SM_AMIGA_4_ 3 -1 3 3 2 3 5 -1 -1 3 0 21
|
||||
329 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21
|
||||
308 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21
|
||||
293 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
||||
326 inst_CLK_000_NE_D0 3 -1 5 3 2 3 6 -1 -1 1 0 21
|
||||
316 inst_CLK_000_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21
|
||||
312 inst_CLK_OUT_PRE_D 3 -1 1 3 1 6 7 -1 -1 1 0 21
|
||||
302 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21
|
||||
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
334 RST_DLY_3_ 3 -1 1 2 1 2 -1 -1 6 0 21
|
||||
333 RST_DLY_2_ 3 -1 2 2 1 2 -1 -1 5 0 21
|
||||
362 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21
|
||||
336 RST_DLY_5_ 3 -1 2 2 1 2 -1 -1 4 0 21
|
||||
332 RST_DLY_1_ 3 -1 2 2 1 2 -1 -1 4 0 21
|
||||
311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 4 0 21
|
||||
375 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
360 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
||||
337 RST_DLY_6_ 3 -1 2 2 1 2 -1 -1 3 0 21
|
||||
331 RST_DLY_0_ 3 -1 2 2 1 2 -1 -1 3 0 21
|
||||
310 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
338 RST_DLY_7_ 3 -1 2 2 1 2 -1 -1 2 0 21
|
||||
335 RST_DLY_4_ 3 -1 1 2 1 2 -1 -1 2 1 21
|
||||
328 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21
|
||||
327 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21
|
||||
295 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21
|
||||
309 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21
|
||||
372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
359 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21
|
||||
373 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
368 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
367 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
363 inst_DS_000_ENABLE 3 -1 3 1 3 -1 -1 3 0 21
|
||||
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
377 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
369 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
365 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
330 N_180_i 3 -1 2 1 5 -1 -1 2 0 21
|
||||
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
358 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
||||
357 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21
|
||||
356 CLK_000_N_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21
|
||||
355 CLK_000_N_SYNC_7_ 3 -1 6 1 3 -1 -1 1 0 21
|
||||
354 CLK_000_N_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21
|
||||
353 CLK_000_N_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
352 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21
|
||||
351 CLK_000_N_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21
|
||||
350 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
349 CLK_000_N_SYNC_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
||||
348 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21
|
||||
347 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21
|
||||
346 CLK_000_P_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21
|
||||
345 CLK_000_P_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21
|
||||
344 CLK_000_P_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21
|
||||
343 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
342 CLK_000_P_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
341 CLK_000_P_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
340 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
339 CLK_000_P_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21
|
||||
324 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
323 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21
|
||||
322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
320 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21
|
||||
318 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21
|
||||
315 inst_CLK_000_D1 3 -1 4 1 5 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_50 3 -1 1 1 1 -1 -1 1 0 21
|
||||
313 inst_DTACK_D0 3 -1 2 1 2 -1 -1 1 0 21
|
||||
300 inst_DS_030_D0 3 -1 3 1 0 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
55 IPL_1_ 1 -1 -1 2 1 5 55 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
||||
59 A1 1 -1 -1 1 0 59 -1
|
||||
35 VPA 1 -1 -1 1 6 35 -1
|
||||
29 DTACK 1 -1 -1 1 2 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 1 13 -1
|
||||
10 CLK_000 1 -1 -1 1 4 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
146 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21
|
||||
79 RW_000 5 367 7 3 0 4 6 79 -1 3 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
70 RW 5 377 6 2 5 7 70 -1 2 0 21
|
||||
97 DS_030 5 -1 0 2 0 3 97 -1 1 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 368 6 1 2 68 -1 3 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21
|
||||
8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21
|
||||
65 E 5 374 6 0 65 -1 5 0 21
|
||||
80 DSACK1 5 373 7 0 80 -1 4 0 21
|
||||
34 VMA 5 375 3 0 34 -1 3 0 21
|
||||
82 BGACK_030 5 370 7 0 82 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 369 3 0 28 -1 2 0 21
|
||||
2 RESET 5 376 1 0 2 -1 2 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
299 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
||||
376 RN_RESET 3 2 1 6 0 1 3 4 6 7 2 -1 2 0 21
|
||||
370 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21
|
||||
317 inst_CLK_000_PE 3 -1 5 5 0 1 3 5 7 -1 -1 1 0 21
|
||||
298 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21
|
||||
364 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
||||
319 inst_CLK_000_NE 3 -1 4 4 0 1 3 5 -1 -1 1 0 21
|
||||
374 RN_E 3 65 6 3 3 5 6 65 -1 5 0 21
|
||||
294 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 5 0 21
|
||||
322 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
||||
360 SM_AMIGA_1_ 3 -1 5 3 1 5 7 -1 -1 3 0 21
|
||||
296 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
||||
328 SM_AMIGA_0_ 3 -1 1 3 1 5 7 -1 -1 2 0 21
|
||||
293 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
|
||||
327 inst_CLK_000_NE_D0 3 -1 3 3 3 5 6 -1 -1 1 0 21
|
||||
316 inst_CLK_000_D0 3 -1 3 3 3 5 6 -1 -1 1 0 21
|
||||
303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
||||
334 RST_DLY_3_ 3 -1 0 2 0 1 -1 -1 6 0 21
|
||||
333 RST_DLY_2_ 3 -1 1 2 0 1 -1 -1 5 0 21
|
||||
336 RST_DLY_5_ 3 -1 1 2 0 1 -1 -1 4 0 21
|
||||
332 RST_DLY_1_ 3 -1 0 2 0 1 -1 -1 4 0 21
|
||||
311 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 4 0 21
|
||||
375 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
||||
363 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
|
||||
337 RST_DLY_6_ 3 -1 1 2 0 1 -1 -1 3 0 21
|
||||
331 RST_DLY_0_ 3 -1 1 2 0 1 -1 -1 3 0 21
|
||||
330 SM_AMIGA_6_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
||||
310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
|
||||
308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
338 RST_DLY_7_ 3 -1 1 2 0 1 -1 -1 2 0 21
|
||||
335 RST_DLY_4_ 3 -1 0 2 0 1 -1 -1 2 1 21
|
||||
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
|
||||
295 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
||||
315 inst_CLK_000_D1 3 -1 6 2 3 5 -1 -1 1 0 21
|
||||
309 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21
|
||||
302 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21
|
||||
372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
359 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
326 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
||||
373 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
362 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
||||
320 N_96_i 3 -1 5 1 5 -1 -1 4 0 21
|
||||
368 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
367 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
361 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21
|
||||
306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
377 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
369 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
365 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
297 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21
|
||||
358 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
||||
357 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21
|
||||
356 CLK_000_N_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21
|
||||
355 CLK_000_N_SYNC_7_ 3 -1 3 1 0 -1 -1 1 0 21
|
||||
354 CLK_000_N_SYNC_6_ 3 -1 3 1 3 -1 -1 1 0 21
|
||||
353 CLK_000_N_SYNC_5_ 3 -1 2 1 3 -1 -1 1 0 21
|
||||
352 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21
|
||||
351 CLK_000_N_SYNC_3_ 3 -1 3 1 0 -1 -1 1 0 21
|
||||
350 CLK_000_N_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21
|
||||
349 CLK_000_N_SYNC_1_ 3 -1 1 1 3 -1 -1 1 0 21
|
||||
348 CLK_000_N_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
347 CLK_000_P_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
||||
346 CLK_000_P_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21
|
||||
345 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
344 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
343 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
342 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
341 CLK_000_P_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
340 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
339 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
325 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
324 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
321 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21
|
||||
318 CLK_000_P_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21
|
||||
313 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21
|
||||
312 inst_CLK_OUT_PRE_D 3 -1 4 1 7 -1 -1 1 0 21
|
||||
300 inst_DS_030_D0 3 -1 0 1 2 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
||||
63 CLK_030 1 -1 -1 3 0 1 7 63 -1
|
||||
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
67 IPL_2_ 1 -1 -1 2 1 6 67 -1
|
||||
55 IPL_1_ 1 -1 -1 2 1 6 55 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
66 IPL_0_ 1 -1 -1 1 1 66 -1
|
||||
59 A1 1 -1 -1 1 2 59 -1
|
||||
35 VPA 1 -1 -1 1 1 35 -1
|
||||
29 DTACK 1 -1 -1 1 2 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 6 13 -1
|
||||
10 CLK_000 1 -1 -1 1 3 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
|--------------------------------------------|
|
||||
|- ispLEVER Fitter Report File -|
|
||||
|- Version 1.8.00.04.29.14 -|
|
||||
|- (c)Copyright, Lattice Semiconductor 2002 -|
|
||||
|--------------------------------------------|
|
||||
|
||||
|
||||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Wed May 13 22:59:29 2015
|
||||
|
||||
|
||||
Pin 15 A_28_
|
||||
Pin 16 A_27_
|
||||
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
|
||||
Pin 17 A_26_
|
||||
Pin 18 A_25_
|
||||
Pin 4 A_31_
|
||||
Pin 19 A_24_
|
||||
Pin 85 A_23_
|
||||
Pin 84 A_22_
|
||||
Pin 94 A_21_
|
||||
Pin 68 IPL_2_
|
||||
Pin 93 A_20_
|
||||
Pin 97 A_19_
|
||||
Pin 58 FC_1_
|
||||
Pin 95 A_18_
|
||||
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
|
||||
Pin 59 A_17_
|
||||
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
|
||||
Pin 96 A_16_
|
||||
Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101
|
||||
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
|
||||
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
|
||||
Pin 60 A1
|
||||
Pin 14 nEXP_SPACE
|
||||
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
|
||||
Pin 21 BG_030
|
||||
Pin 28 BGACK_000
|
||||
Pin 64 CLK_030
|
||||
Pin 11 CLK_000
|
||||
Pin 61 CLK_OSZI
|
||||
Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247
|
||||
Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127
|
||||
Pin 56 IPL_1_
|
||||
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271
|
||||
Pin 67 IPL_0_
|
||||
Pin 91 FPU_SENSE
|
||||
Pin 57 FC_0_
|
||||
Pin 30 DTACK
|
||||
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
|
||||
Pin 36 VPA
|
||||
Pin 86 RST
|
||||
Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181
|
||||
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
|
||||
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179
|
||||
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
|
||||
Pin 5 A_30_
|
||||
Pin 6 A_29_
|
||||
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
|
||||
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
|
||||
Pin 69 A0 Reg ; S6=1 S9=1 Pair 257
|
||||
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
|
||||
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
|
||||
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143
|
||||
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137
|
||||
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283
|
||||
Pin 66 E Reg ; S6=1 S9=1 Pair 251
|
||||
Pin 35 VMA Reg ; S6=1 S9=1 Pair 173
|
||||
Pin 3 RESET Reg ; S6=1 S9=1 Pair 125
|
||||
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
|
||||
Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1
|
||||
Node 281 RN_AS_030 Comb ; S6=1 S9=1
|
||||
Node 203 RN_AS_000 Comb ; S6=1 S9=1
|
||||
Node 101 RN_DS_030 Comb ; S6=1 S9=1
|
||||
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
|
||||
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
|
||||
Node 197 RN_BERR Comb ; S6=1 S9=1
|
||||
Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1
|
||||
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
|
||||
Node 269 RN_RW_000 Reg ; S6=1 S9=1
|
||||
Node 257 RN_A0 Reg ; S6=1 S9=1
|
||||
Node 175 RN_BG_000 Reg ; S6=1 S9=1
|
||||
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
|
||||
Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1
|
||||
Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1
|
||||
Node 283 RN_DSACK1 Reg ; S6=1 S9=1
|
||||
Node 251 RN_E Reg ; S6=1 S9=1
|
||||
Node 173 RN_VMA Reg ; S6=1 S9=1
|
||||
Node 125 RN_RESET Reg ; S6=1 S9=1
|
||||
Node 245 RN_RW Reg ; S6=1 S9=1
|
||||
Node 223 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 187 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 157 inst_AS_000_INT Reg ; S6=1 S9=1
|
||||
Node 239 SM_AMIGA_5_ Reg ; S6=1 S9=1
|
||||
Node 163 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
|
||||
Node 277 inst_AS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 253 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1
|
||||
Node 124 inst_DS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 155 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
|
||||
Node 113 inst_AS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 115 inst_DS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 110 CYCLE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 104 CYCLE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 265 SIZE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 146 inst_VPA_D Reg ; S6=1 S9=1
|
||||
Node 167 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 161 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 217 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
|
||||
Node 152 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 211 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 248 inst_CLK_000_D1 Reg ; S6=1 S9=1
|
||||
Node 182 inst_CLK_000_D0 Reg ; S6=1 S9=1
|
||||
Node 221 inst_CLK_000_PE Reg ; S6=1 S9=1
|
||||
Node 118 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 209 inst_CLK_000_NE Reg ; S6=1 S9=1
|
||||
Node 230 N_96_i Comb ; S6=1 S9=1
|
||||
Node 278 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1
|
||||
Node 193 cpu_est_2_ Reg ; S6=1 S9=1
|
||||
Node 148 IPL_D0_0_ Reg ; S6=1 S9=1
|
||||
Node 268 IPL_D0_1_ Reg ; S6=1 S9=1
|
||||
Node 262 IPL_D0_2_ Reg ; S6=1 S9=1
|
||||
Node 241 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 176 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
|
||||
Node 133 SM_AMIGA_0_ Reg ; S6=1 S9=1
|
||||
Node 151 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
|
||||
Node 235 SM_AMIGA_6_ Reg ; S6=1 S9=1
|
||||
Node 134 RST_DLY_0_ Reg ; S6=1 S9=1
|
||||
Node 103 RST_DLY_1_ Reg ; S6=1 S9=1
|
||||
Node 139 RST_DLY_2_ Reg ; S6=1 S9=1
|
||||
Node 119 RST_DLY_3_ Reg ; S6=1 S9=1
|
||||
Node 109 RST_DLY_4_ Reg ; S6=1 S9=1
|
||||
Node 145 RST_DLY_5_ Reg ; S6=1 S9=1
|
||||
Node 128 RST_DLY_6_ Reg ; S6=1 S9=1
|
||||
Node 140 RST_DLY_7_ Reg ; S6=1 S9=1
|
||||
Node 196 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 256 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 250 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 142 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 136 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 266 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 260 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 112 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 106 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 190 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 130 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 184 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 178 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 122 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 169 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 194 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 188 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 116 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 254 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1
|
||||
Node 121 inst_CLK_030_H Reg ; S6=1 S9=1
|
||||
Node 233 SM_AMIGA_1_ Reg ; S6=1 S9=1
|
||||
Node 236 SM_AMIGA_4_ Reg ; S6=1 S9=1
|
||||
Node 224 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 229 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 227 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
|
||||
Node 205 CIIN_0 Comb ; S6=1 S9=1
|
||||
; Unused Pins & Nodes
|
||||
; -> None Found.
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,2 @@
|
|||
Part Number: M4A5-128/64-10VC
|
||||
Need not generate svf file according to the constraints, exit
|
||||
|
|
@ -0,0 +1,139 @@
|
|||
|
||||
|
||||
Design Name = 68030_tk.tt4
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
||||
*******************
|
||||
* TIMING ANALYSIS *
|
||||
*******************
|
||||
|
||||
Timing Analysis KEY:
|
||||
One unit of delay time is equivalent to one pass
|
||||
through the Central Switch Matrix.
|
||||
.. Delay ( in this column ) not applicable to the indicated signal.
|
||||
TSU, Set-Up Time ( 0 for input-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and a register setup before clock.
|
||||
TSU is reported on the register.
|
||||
TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and an output pin.
|
||||
TCO is reported on the register.
|
||||
TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and an output pin.
|
||||
TPD is reported on the output pin.
|
||||
TCR, Clocked Output-to-Register Time,
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and the register it drives ( before clock ).
|
||||
TCR is reported on the driving register.
|
||||
|
||||
TSU TCO TPD TCR
|
||||
#passes #passes #passes #passes
|
||||
SIGNAL NAME min max min max min max min max
|
||||
inst_AS_000_DMA 1 4 1 4 .. .. 1 5
|
||||
A0 1 4 0 0 .. .. 1 1
|
||||
RN_A0 1 4 0 0 .. .. 1 1
|
||||
inst_AS_000_INT 1 1 1 3 .. .. 2 4
|
||||
inst_DS_000_DMA 1 4 1 2 .. .. 2 3
|
||||
SIZE_DMA_0_ 1 4 1 1 .. .. 2 2
|
||||
SIZE_DMA_1_ 1 4 1 1 .. .. 2 2
|
||||
inst_CLK_030_H 1 4 .. .. .. .. 1 1
|
||||
UDS_000 .. .. .. .. 1 3 .. ..
|
||||
LDS_000 .. .. .. .. 1 3 .. ..
|
||||
inst_DS_030_D0 1 3 .. .. .. .. 1 1
|
||||
DS_030 .. .. .. .. 1 2 .. ..
|
||||
FPU_CS .. .. .. .. 1 2 .. ..
|
||||
AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. ..
|
||||
SM_AMIGA_5_ 1 1 .. .. .. .. 1 2
|
||||
inst_AS_030_D0 1 2 1 1 .. .. 1 1
|
||||
inst_nEXP_SPACE_D0reg 1 1 1 1 .. .. 1 2
|
||||
inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2
|
||||
CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1
|
||||
CYCLE_DMA_1_ 1 2 .. .. .. .. 1 1
|
||||
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_CLK_000_D1 .. .. .. .. .. .. 1 2
|
||||
inst_CLK_000_D0 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_3_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_0_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_6_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_1_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_4_ 1 1 .. .. .. .. 1 2
|
||||
SM_AMIGA_2_ 1 1 .. .. .. .. 1 2
|
||||
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
|
||||
AS_030 .. .. .. .. 1 1 .. ..
|
||||
AS_000 .. .. .. .. 1 1 .. ..
|
||||
CLK_EXP .. .. .. .. 1 1 .. ..
|
||||
CIIN .. .. .. .. 1 1 .. ..
|
||||
IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
RW_000 1 1 0 0 .. .. 1 1
|
||||
RN_RW_000 1 1 0 0 .. .. 1 1
|
||||
BG_000 1 1 0 0 .. .. 1 1
|
||||
RN_BG_000 1 1 0 0 .. .. 1 1
|
||||
BGACK_030 1 1 0 1 .. .. 1 1
|
||||
RN_BGACK_030 1 1 0 1 .. .. 1 1
|
||||
IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
DSACK1 1 1 0 0 .. .. 1 1
|
||||
RN_DSACK1 1 1 0 0 .. .. 1 1
|
||||
E .. .. 0 0 .. .. 1 1
|
||||
RN_E .. .. 0 0 .. .. 1 1
|
||||
VMA 1 1 0 0 .. .. 1 1
|
||||
RN_VMA 1 1 0 0 .. .. 1 1
|
||||
RESET 1 1 0 0 .. .. 1 1
|
||||
RN_RESET 1 1 0 0 .. .. 1 1
|
||||
RW 1 1 0 0 .. .. 1 1
|
||||
RN_RW 1 1 0 0 .. .. 1 1
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_1_ .. .. .. .. .. .. 1 1
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. ..
|
||||
inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
|
||||
inst_VPA_D 1 1 .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
|
||||
inst_DTACK_D0 1 1 .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_PE .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_NE .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_2_ .. .. .. .. .. .. 1 1
|
||||
IPL_D0_0_ 1 1 .. .. .. .. 1 1
|
||||
IPL_D0_1_ 1 1 .. .. .. .. 1 1
|
||||
IPL_D0_2_ 1 1 .. .. .. .. 1 1
|
||||
inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. ..
|
||||
RST_DLY_0_ 1 1 .. .. .. .. 1 1
|
||||
RST_DLY_1_ 1 1 .. .. .. .. 1 1
|
||||
RST_DLY_2_ 1 1 .. .. .. .. 1 1
|
||||
RST_DLY_3_ 1 1 .. .. .. .. 1 1
|
||||
RST_DLY_4_ 1 1 .. .. .. .. 1 1
|
||||
RST_DLY_5_ 1 1 .. .. .. .. 1 1
|
||||
RST_DLY_6_ 1 1 .. .. .. .. 1 1
|
||||
RST_DLY_7_ 1 1 .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1
|
||||
SM_AMIGA_i_7_ 1 1 1 1 .. .. 1 1
|
||||
CIIN_0 .. .. .. .. 1 1 .. ..
|
||||
|
|
@ -0,0 +1,633 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Wed May 13 22:59:21 2015
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW
|
||||
#$ NODES 72 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_
|
||||
.type fr
|
||||
.i 127
|
||||
.o 198
|
||||
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
|
||||
.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C inst_UDS_000_INT.C RW.C RW_000.C inst_LDS_000_INT.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C BGACK_030.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ N_96_i AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
|
||||
.p 621
|
||||
------------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-1----------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--0---------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
----1-------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----1------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
|
||||
------0------------------------------------------------------------------------------------------------------------------------ ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1----------------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------1--------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~11111111111111111111111111111111111111111111111111111111111111111111111111111111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
----------1-------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------1------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------1------------------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------0----------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~11111111~~11111~1~~~~~~~~111~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~1111
|
||||
-------------------------1----------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------1---------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------0--------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
----------------------------1-------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------------------------1------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------------------------1------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------------------------0----------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------------1---------------------------------------------------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------1-------------------------1---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---1----------------------------0---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---0----------------------------0---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------0--------------------0-------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-------------1------------------------------------------------1------------111110---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
-------------1------------------------------------------------1------------1111111--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-------------1--------------------------------------------------------------1111111-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-------------1---------------1-------------------------------------0---------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-0-----------1------------------------------------------------------1--------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-1-----------1------------------------------------------------------0--------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-------------1---------------0------------------------------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-------------1----------------0-----------------------------------1-----------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-------------1----------------1-----------------------------------0-----------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-------------1-----------------------------------------------------0----------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-0-----------1------------------------------------------------------1---------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-1-----------1------------------------------------------------------0---------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-0-----------1-----------------------------------------------------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1----------------0-----------------------------------1------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1----------------1-----------------------------------0------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1---------------0-------------------------------------1-----------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1---------------1-------------------------------------0-----------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1------------------------------------------------------0----------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
--------------------------------------------------------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------------------------------------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--1---1---0--------------0010--1------------------------------------------------------------------------------------0---------- ~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------------------0-----------------------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------------------------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||
----------------------------------------------0----------------------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------------------------------------------0---------------------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------------1-------------------------------------------------------------------------------------1-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------------------------------------1---------------------------------------------------------------------------1-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------------------------------------------------------------------------------------11-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------------0-------------------------------------------------------------------------------------0-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------------------------------------------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||
-------------1---------------------------------------------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------------------------------------------------0--------------------------------------------------------1--------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------------------------------------------------0-------------------------------------------------------1--------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------------------------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||
-------1-----1------------------0---------------01-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-01-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------001-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0---------------10-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-10-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------010-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-01--------------------------------------------------------1----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-10--------------------------------------------------------1----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------001--------------------------------------------------------0----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------010--------------------------------------------------------0----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------01-------------------------------------------------------------------01-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------10-------------------------------------------------------------------01-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0----------------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------------------------------------------------------------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||
-------1-----1------------------0---------------01-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-01-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------001-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0---------------10-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-10-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------010-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-01--------------------------------------------------------1----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-10--------------------------------------------------------1----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------001--------------------------------------------------------0----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------010--------------------------------------------------------0----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------01-------------------------------------------------------------------01--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------10-------------------------------------------------------------------01--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------------------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1-----------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1-------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1-------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------------0--0-----------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1---------------------------0--0--------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1---------------------------0-------------------------------0---------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------------------------------------------------1--------------------------------------1----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------------0------------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------1-----------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1----------------------1---------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------1--------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------------------------1---1---------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------------------------0------------0------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------------------------------------------0-------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--0----------1------------------1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------1------1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------1-----1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------0----1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------1---1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------01--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------1-------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------0-------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
|
||||
---------------------------------------1----------------------0--------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
---------------------------------0------------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
----------------------------------1-----------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------1---------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
-------------------------------------1--------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
----------------------------------------------------1---1------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
----------------------------------------------------0------------0---1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
---------------------------------------------------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||
---------------------------------------0-----------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
---------------------------------------------------------------------10------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
-----------------------------------------------------------------------1-----------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------------------------------0-------------1--------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
-----------------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
|
||||
--------------------------------------------------------------0--------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------------------------------0-----------------------------------------------1----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------------------------------0------------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
---------------------------------------------------------------------------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------------------1--------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
|
||||
---------------------------------------1-1------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
---------------------------------------1----------------------------------------------------------------------0---------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
---------------------------------------1-------------------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
.end
|
||||
|
|
@ -0,0 +1,633 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Wed May 13 22:59:21 2015
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_ A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_ A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA RESET RW
|
||||
#$ NODES 72 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_
|
||||
.type fr
|
||||
.i 127
|
||||
.o 198
|
||||
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
|
||||
.ob CLK_DIV_OUT CLK_EXP FPU_CS AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_1_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C RST_DLY_3_.C RST_DLY_4_.C RST_DLY_5_.C RST_DLY_6_.C RST_DLY_7_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C inst_CLK_030_H.C RESET.C inst_DS_000_ENABLE.C inst_UDS_000_INT.C RW.C RW_000.C inst_LDS_000_INT.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C A0.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DS_030_D0.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C BGACK_030.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_BGACK_030_INT_D.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C SIZE_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 BERR SIZE_0_ N_96_i AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE CLK_DIV_OUT.OE DSACK1.OE CIIN.OE BGACK_030.D E.D VMA.T RESET.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_DS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D cpu_est_2_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D SM_AMIGA_3_.T inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_6_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D RST_DLY_3_.D RST_DLY_4_.T RST_DLY_5_.T RST_DLY_6_.T RST_DLY_7_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_4_.D SM_AMIGA_2_.D inst_DS_000_ENABLE.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
|
||||
.p 621
|
||||
------------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-1----------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--0---------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
----1-------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----1------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
|
||||
------0------------------------------------------------------------------------------------------------------------------------ ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1----------------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------1--------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~11111111111111111111111111111111111111111111111111111111111111111111111111111111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
----------1-------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------1------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------1------------------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------0----------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~11111111~~11111~1~~~~~~~~111~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~1111
|
||||
-------------------------1----------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------1---------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------0--------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
----------------------------1-------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------------------------1------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
--------------------------------0--1------0------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-1---------------------------11-----------------------------------111---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111
|
||||
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|
||||
-1---------------------------01-----------------------------------101---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-------------1------------------------------------------------1------------111110---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
-------------1------------------------------------------------1------------1111111--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
-------------1------------------------------------------------1------------1111110--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
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|
||||
-------------1--------------------------------------------------------------1111111-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
-------------1-------------------------0-------------------------------0-------------------------------0-------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
|
||||
-----0-------1--------------------------------------------------------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
|
||||
-------------1----------------0----------------------------------------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-------------1----------------------------------------------------0----------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-------------1---------------0-------------------------------------1---------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-------------1---------------1-------------------------------------0---------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-0-----------1------------------------------------------------------1--------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-1-----------1------------------------------------------------------0--------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
|
||||
-------------1---------------0------------------------------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-------------1----------------0-----------------------------------1-----------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-------------1----------------1-----------------------------------0-----------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-------------1-----------------------------------------------------0----------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-0-----------1------------------------------------------------------1---------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-1-----------1------------------------------------------------------0---------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
|
||||
-0-----------1-----------------------------------------------------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1----------------0-----------------------------------1------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1----------------1-----------------------------------0------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1---------------0-------------------------------------1-----------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1---------------1-------------------------------------0-----------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
-------------1------------------------------------------------------0----------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
|
||||
--------------------------------------------------------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------------------------------------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--1---1---0--------------0010--1------------------------------------------------------------------------------------0---------- ~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------------------0-----------------------------------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------------------------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||
----------------------------------------------0----------------------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------------------------------------------0---------------------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------------1-------------------------------------------------------------------------------------1-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------------------------------------1---------------------------------------------------------------------------1-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------------------------------------------------------------------------------------11-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--------------------------------0-------------------------------------------------------------------------------------0-------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------------------------------------------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
|
||||
-------------1---------------------------------------------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-----------------------------------------------------0--------------------------------------------------------1--------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------------------------------------------------0-------------------------------------------------------1--------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------------------------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
|
||||
-------1-----1------------------0---------------01-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-01-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------001-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0---------------10-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-10-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------010-------------------------------------------------------------------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-01--------------------------------------------------------1----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-10--------------------------------------------------------1----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------001--------------------------------------------------------0----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------010--------------------------------------------------------0----------0--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------01-------------------------------------------------------------------01-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------10-------------------------------------------------------------------01-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0----------------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
------------------------------------------------------------------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
|
||||
-------1-----1------------------0---------------01-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-01-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------001-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0---------------10-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0-------------0-10-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------0-----1------------------0--------------010-------------------------------------------------------------------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-01--------------------------------------------------------1----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------1-----1------------------0-------------0-10--------------------------------------------------------1----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------001--------------------------------------------------------0----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0--------------010--------------------------------------------------------0----------0---0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------01-------------------------------------------------------------------01--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------10-------------------------------------------------------------------01--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------0---------------------------------------------------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1-----------------------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1-------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------------0------------------------------1-------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------------------0--0-----------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1---------------------------0--0--------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1---------------------------0-------------------------------0---------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------------------------------------------------1--------------------------------------1----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------------0------------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------1-----------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1----------------------1---------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------------1--------------0-------------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------------------------1---1---------------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------------------------0------------0------------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------------------------------------------------0-------------------------------------0----------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
--0----------1------------------1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------1------1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1------------1-----1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------0----1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1--------------1---1--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-----------------01--------01--1-----------------------------------------------------------------0-------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------1-------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
---------------------------------------0-------------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
|
||||
---------------------------------------1----------------------0--------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
---------------------------------0------------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
----------------------------------1-----------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------1---------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
-------------------------------------1--------------0----------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
----------------------------------------------------1---1------------1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
----------------------------------------------------0------------0---1-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
---------------------------------------------------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
|
||||
---------------------------------------0-----------------------------0-------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
---------------------------------------------------------------------10------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
-----------------------------------------------------------------------1-----------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------------------------------0-------------1--------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
-----------------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
|
||||
--------------------------------------------------------------0--------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------------------------------0-----------------------------------------------1----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
------------------------------------------------------------0------------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
|
||||
---------------------------------------------------------------------------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
-------------1-------------------------1--------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
|
||||
---------------------------------------1-1------------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
---------------------------------------1----------------------------------------------------------------------0---------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
---------------------------------------1-------------------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
|
||||
.end
|
||||
|
|
@ -0,0 +1,341 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Wed May 13 22:59:21 2015
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_
|
||||
A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1
|
||||
nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP
|
||||
IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE
|
||||
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_
|
||||
A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA
|
||||
RESET RW
|
||||
#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
|
||||
inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA
|
||||
inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D
|
||||
inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0
|
||||
inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE
|
||||
CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_
|
||||
IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_
|
||||
RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_
|
||||
CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
|
||||
CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
|
||||
CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
|
||||
CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
|
||||
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H
|
||||
SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0
|
||||
.type f
|
||||
.i 128
|
||||
.o 200
|
||||
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
|
||||
A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q
|
||||
RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q
|
||||
inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
|
||||
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
|
||||
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
|
||||
inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
|
||||
inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i
|
||||
CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
|
||||
SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q
|
||||
RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q
|
||||
RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q
|
||||
CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q
|
||||
CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q
|
||||
CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q
|
||||
CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q
|
||||
CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q
|
||||
SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q
|
||||
IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN
|
||||
DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN
|
||||
RW.PIN CIIN_0
|
||||
.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE
|
||||
UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE
|
||||
CLK_EXP FPU_CS% AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW%
|
||||
AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D% IPL_030_2_.C
|
||||
RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D%
|
||||
BGACK_030.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C DSACK1.D%
|
||||
DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D% RW.C RW.OE
|
||||
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D% cpu_est_1_.C inst_AS_000_INT.D%
|
||||
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C
|
||||
inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D%
|
||||
inst_DS_030_D0.C inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C
|
||||
inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D
|
||||
inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D
|
||||
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C
|
||||
SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C inst_UDS_000_INT.D%
|
||||
inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D
|
||||
inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D
|
||||
inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D
|
||||
inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D
|
||||
CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C N_96_i%
|
||||
CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D%
|
||||
IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C SM_AMIGA_3_.T
|
||||
SM_AMIGA_3_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D
|
||||
SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
||||
SM_AMIGA_6_.D SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C
|
||||
RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1
|
||||
RST_DLY_4_.T.X2 RST_DLY_4_.C RST_DLY_5_.T RST_DLY_5_.C RST_DLY_6_.T RST_DLY_6_.C
|
||||
RST_DLY_7_.D RST_DLY_7_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C
|
||||
CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C
|
||||
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C
|
||||
CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C
|
||||
CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C
|
||||
CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C
|
||||
CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C
|
||||
CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C
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||||
CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C
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||||
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C
|
||||
CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C inst_CLK_030_H.D inst_CLK_030_H.C
|
||||
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_2_.D
|
||||
SM_AMIGA_2_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C SM_AMIGA_i_7_.D
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||||
SM_AMIGA_i_7_.C CIIN_0
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.end
|
||||
|
|
@ -0,0 +1,341 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Wed May 13 22:59:21 2015
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 A_28_ A_27_ SIZE_1_ A_26_ A_25_ A_31_ A_24_ A_23_ A_22_ A_21_ IPL_2_
|
||||
A_20_ A_19_ FC_1_ A_18_ AS_030 A_17_ AS_000 A_16_ DS_030 UDS_000 LDS_000 A1
|
||||
nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP
|
||||
IPL_1_ FPU_CS IPL_0_ FPU_SENSE FC_0_ DTACK AVEC VPA RST AMIGA_ADDR_ENABLE
|
||||
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ A_30_
|
||||
A_29_ IPL_030_2_ RW_000 A0 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ DSACK1 E VMA
|
||||
RESET RW
|
||||
#$ NODES 73 cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
|
||||
inst_DS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA
|
||||
inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D
|
||||
inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0
|
||||
inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE
|
||||
CLK_000_P_SYNC_9_ inst_CLK_000_NE N_96_i CLK_000_N_SYNC_11_ cpu_est_2_ IPL_D0_0_
|
||||
IPL_D0_1_ IPL_D0_2_ SM_AMIGA_3_ inst_CLK_000_NE_D0 SM_AMIGA_0_
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_
|
||||
RST_DLY_3_ RST_DLY_4_ RST_DLY_5_ RST_DLY_6_ RST_DLY_7_ CLK_000_P_SYNC_0_
|
||||
CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_
|
||||
CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_
|
||||
CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_
|
||||
CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
|
||||
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_CLK_030_H
|
||||
SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_2_ inst_DS_000_ENABLE SM_AMIGA_i_7_ CIIN_0
|
||||
.type f
|
||||
.i 128
|
||||
.o 200
|
||||
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
|
||||
A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q E.Q VMA.Q
|
||||
RESET.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q
|
||||
inst_DS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q
|
||||
inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q
|
||||
inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q
|
||||
inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
|
||||
inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q N_96_i
|
||||
CLK_000_N_SYNC_11_.Q cpu_est_2_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
|
||||
SM_AMIGA_3_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_6_.Q RST_DLY_0_.Q
|
||||
RST_DLY_1_.Q RST_DLY_2_.Q RST_DLY_3_.Q RST_DLY_4_.Q RST_DLY_5_.Q RST_DLY_6_.Q
|
||||
RST_DLY_7_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q
|
||||
CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q
|
||||
CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q
|
||||
CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q
|
||||
CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q
|
||||
CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q
|
||||
SM_AMIGA_4_.Q SM_AMIGA_2_.Q inst_DS_000_ENABLE.Q SM_AMIGA_i_7_.Q BG_000.Q
|
||||
IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN
|
||||
DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN
|
||||
RW.PIN CIIN_0
|
||||
.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE
|
||||
UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT CLK_DIV_OUT.OE
|
||||
CLK_EXP FPU_CS- AVEC AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW-
|
||||
AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE SIZE_0_ SIZE_0_.OE IPL_030_2_.D- IPL_030_2_.C
|
||||
RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D-
|
||||
BGACK_030.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C DSACK1.D-
|
||||
DSACK1.C DSACK1.OE E.D E.C VMA.T VMA.C RESET.D RESET.C RW.D- RW.C RW.OE
|
||||
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D- cpu_est_1_.C inst_AS_000_INT.D-
|
||||
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
|
||||
inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_DS_030_D0.D-
|
||||
inst_DS_030_D0.C inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C
|
||||
inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D
|
||||
inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D
|
||||
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C
|
||||
SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C inst_UDS_000_INT.D-
|
||||
inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D
|
||||
inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_CLK_OUT_PRE_50.D
|
||||
inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D
|
||||
inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D
|
||||
CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C N_96_i-
|
||||
CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C cpu_est_2_.D cpu_est_2_.C IPL_D0_0_.D-
|
||||
IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C SM_AMIGA_3_.T
|
||||
SM_AMIGA_3_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D
|
||||
SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
|
||||
SM_AMIGA_6_.D SM_AMIGA_6_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C
|
||||
RST_DLY_2_.D RST_DLY_2_.C RST_DLY_3_.D RST_DLY_3_.C RST_DLY_4_.T.X1
|
||||
RST_DLY_4_.T.X2 RST_DLY_4_.C RST_DLY_5_.T RST_DLY_5_.C RST_DLY_6_.T RST_DLY_6_.C
|
||||
RST_DLY_7_.D RST_DLY_7_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C
|
||||
CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C
|
||||
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C
|
||||
CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C
|
||||
CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C
|
||||
CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C
|
||||
CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C
|
||||
CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C
|
||||
CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C
|
||||
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C
|
||||
CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C inst_CLK_030_H.D inst_CLK_030_H.C
|
||||
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_2_.D
|
||||
SM_AMIGA_2_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C SM_AMIGA_i_7_.D
|
||||
SM_AMIGA_i_7_.C CIIN_0
|
||||
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|
||||
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|
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||||
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|
||||
-------------1-------------------------------------------------------------0--1------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------------------------------------------0-1------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1---------------------------------------------------------------01------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------1------------1110------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1----------------------------------------------------------------11111--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------0-----------------------------------------------------------------1------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------1------------1111------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000
|
||||
-------------0------------------------------------------------------------------1----------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------1------------111110----------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------1------------1111110---------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------1------------111111-0--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
-------------0-------------------------------------------------------------------1---------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------1------------1111110---------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------1------------11111110--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------1------------1111111---------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------------------------------------------------1--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------------------01-------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------------------------------------------1-------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------------------------------------------1------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------------------------------------------1------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------------------------------1----------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000
|
||||
---------------------------------------------------------------------------------------1---------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
|
||||
----------------------------------------------------------------------------------------1--------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||
-----------------------------------------------------------------------------------------1-------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000
|
||||
------------------------------------------------------------------------------------------1------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000
|
||||
----------------------------------------------------------10-------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000
|
||||
--------------------------------------------------------------------------------------------1----------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||
---------------------------------------------------------------------------------------------1---------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
|
||||
----------------------------------------------------------------------------------------------1--------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
|
||||
-----------------------------------------------------------------------------------------------1-------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||
------------------------------------------------------------------------------------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000
|
||||
-------------------------------------------------------------------------------------------------1------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000
|
||||
--------------------------------------------------------------------------------------------------1----------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
|
||||
---------------------------------------------------------------------------------------------------1---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000
|
||||
----------------------------------------------------------------------------------------------------1--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000
|
||||
-----------------------------------------------------------------------------------------------------1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000
|
||||
-------0-----1------------------0-------------0-01-------------------------------------------------------------------0--0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------0-----1------------------0-------------0-10-------------------------------------------------------------------0--0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------------1------------------0---------------01--------------------------------------------------------1----------0--0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------------1------------------0---------------10--------------------------------------------------------1----------0--0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------0-----1------------------0-------------0-01-------------------------------------------------------------------0---0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------0-----1------------------0-------------0-10-------------------------------------------------------------------0---0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------------1------------------0---------------01--------------------------------------------------------1----------0---0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------------1------------------0---------------10--------------------------------------------------------1----------0---0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------------1----------------------------------------------1----------------------------------------------0-1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1------------------------------------------------0--------------------------------------------1-----------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1---------------------------------------------------------------------------------------------1-1---------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1-------------------------1----------------------1----------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
|
||||
-------------1-------------------------1--------------------------------------------------------------------1------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
|
||||
-------------1----------------------------------------------0-----------------------------------------------1----------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
|
||||
-------------1--------------------------------------1---0------------11--------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1-------------------10-00--------------0------------1---11--------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1-------------------------------------------------------1---------------------------------------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1----------------------------------------------0------------------------------------------------1---------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1-------------------------0-----------------------------1---------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1---------------------------0--------------------------------------------------------------------1--------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1-------------------------1--------------------------------------------------------------------------------------1- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1----------------------------------------------1-11-----0-0-------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------------------------1---0---1-11------10-------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------10-00--------------0-------1-11-1----10-------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------------0--------------------1--1-----0-0-----------------------------------0-------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------------0------------1---0---1--1------10-----------------------------------0-------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------10-00-0------------0-------1--1-1----10-----------------------------------0-------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1------------------------------------------------11-----0-0--0---------------------------------00------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------------------------1---0-----11------10--0---------------------------------00------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------10-00--------------0---------11-1----10--0---------------------------------00------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------------0-----------------------1-----0-0--0--------------------------------000------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------------0------------1---0------1------10--0--------------------------------000------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------10-00-0------------0----------1-1----10--0--------------------------------000------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1----------------------------------------------0--1-------------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------------------------------------1-------0-----------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
.end
|
||||
|
|
@ -0,0 +1,253 @@
|
|||
[DEVICE]
|
||||
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = NO;
|
||||
Pin_MC_1to1 = NO;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 5/13/15;
|
||||
TIME = 22:59:29;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
|
||||
Netlist = VHDL;
|
||||
Delay_File = SDF;
|
||||
Generic_VCC = ;
|
||||
Generic_GND = ;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignment = NO;
|
||||
Pin_Block = NO;
|
||||
Pin_Macrocell_Block = NO;
|
||||
Routing = NO;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
|
||||
Balanced_Partitioning = YES;
|
||||
Spread_Placement = YES;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Inter_Seg_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
|
||||
Fitter_Options = YES;
|
||||
Pinout_Diagram = NO;
|
||||
Pinout_Listing = YES;
|
||||
Detailed_Block_Segment_Summary = YES;
|
||||
Input_Signal_List = YES;
|
||||
Output_Signal_List = YES;
|
||||
Bidir_Signal_List = YES;
|
||||
Node_Signal_List = YES;
|
||||
Signal_Fanout_List = YES;
|
||||
Block_Segment_Fanin_List = YES;
|
||||
Prefit_Eqn = YES;
|
||||
Postfit_Eqn = YES;
|
||||
Page_Break = YES;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
|
||||
Logic_Reduction = YES;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = YES;
|
||||
Node_Collapse = Yes;
|
||||
DT_Synthesis = Yes;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = NO;
|
||||
In_Reg_Optimize = YES;
|
||||
Clock_Optimize = NO;
|
||||
Conf_Unused_IOs = OUT_LOW;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low, High;
|
||||
Default = High;
|
||||
Low = 8, H, G, F, E, D, C, B, A;
|
||||
Type = GLB;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
|
||||
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
|
||||
Layer = OFF
|
||||
BERR = OUTPUT,41,4,-;
|
||||
RW_000 = BIDIR,80,7,-;
|
||||
AS_000 = OUTPUT,42,4,-;
|
||||
RW = BIDIR,71,6,-;
|
||||
DS_030 = OUTPUT,98,0,-;
|
||||
AS_030 = OUTPUT,82,7,-;
|
||||
UDS_000 = OUTPUT,32,3,-;
|
||||
LDS_000 = OUTPUT,31,3,-;
|
||||
A0 = BIDIR,69,6,-;
|
||||
SIZE_1_ = OUTPUT,79,7,-;
|
||||
SIZE_0_ = OUTPUT,70,6,-;
|
||||
IPL_030_2_ = OUTPUT,9,1,-;
|
||||
IPL_030_0_ = OUTPUT,8,1,-;
|
||||
IPL_030_1_ = OUTPUT,7,1,-;
|
||||
E = OUTPUT,66,6,-;
|
||||
DSACK1 = OUTPUT,81,7,-;
|
||||
VMA = OUTPUT,35,3,-;
|
||||
BGACK_030 = OUTPUT,83,7,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-;
|
||||
BG_000 = OUTPUT,29,3,-;
|
||||
RESET = OUTPUT,3,1,-;
|
||||
AVEC = OUTPUT,92,0,-;
|
||||
FPU_CS = OUTPUT,78,7,-;
|
||||
CLK_DIV_OUT = OUTPUT,65,6,-;
|
||||
CIIN = OUTPUT,47,4,-;
|
||||
AMIGA_ADDR_ENABLE = OUTPUT,33,3,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
|
||||
CLK_EXP = OUTPUT,10,1,-;
|
||||
inst_nEXP_SPACE_D0reg = NODE,*,6,-;
|
||||
RN_RESET = NODE,-1,1,-;
|
||||
RN_BGACK_030 = NODE,-1,7,-;
|
||||
inst_CLK_000_PE = NODE,*,5,-;
|
||||
inst_AS_030_D0 = NODE,*,7,-;
|
||||
SM_AMIGA_i_7_ = NODE,*,5,-;
|
||||
inst_CLK_000_NE = NODE,*,4,-;
|
||||
RN_E = NODE,-1,6,-;
|
||||
cpu_est_1_ = NODE,*,3,-;
|
||||
cpu_est_2_ = NODE,*,3,-;
|
||||
SM_AMIGA_1_ = NODE,*,5,-;
|
||||
SM_AMIGA_5_ = NODE,*,5,-;
|
||||
SM_AMIGA_0_ = NODE,*,1,-;
|
||||
cpu_est_0_ = NODE,*,5,-;
|
||||
inst_CLK_000_NE_D0 = NODE,*,3,-;
|
||||
inst_CLK_000_D0 = NODE,*,3,-;
|
||||
inst_AS_000_DMA = NODE,*,0,-;
|
||||
inst_AS_030_000_SYNC = NODE,*,2,-;
|
||||
RST_DLY_3_ = NODE,*,0,-;
|
||||
RST_DLY_2_ = NODE,*,1,-;
|
||||
RST_DLY_5_ = NODE,*,1,-;
|
||||
RST_DLY_1_ = NODE,*,0,-;
|
||||
inst_LDS_000_INT = NODE,*,2,-;
|
||||
RN_VMA = NODE,-1,3,-;
|
||||
inst_DS_000_ENABLE = NODE,*,5,-;
|
||||
RST_DLY_6_ = NODE,*,1,-;
|
||||
RST_DLY_0_ = NODE,*,1,-;
|
||||
SM_AMIGA_6_ = NODE,*,5,-;
|
||||
inst_UDS_000_INT = NODE,*,2,-;
|
||||
SIZE_DMA_1_ = NODE,*,6,-;
|
||||
SIZE_DMA_0_ = NODE,*,6,-;
|
||||
RST_DLY_7_ = NODE,*,1,-;
|
||||
RST_DLY_4_ = NODE,*,0,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,2,-;
|
||||
inst_AS_000_INT = NODE,*,2,-;
|
||||
inst_CLK_000_D1 = NODE,*,6,-;
|
||||
inst_VPA_D = NODE,*,1,-;
|
||||
inst_BGACK_030_INT_D = NODE,*,7,-;
|
||||
RN_IPL_030_0_ = NODE,-1,1,-;
|
||||
RN_IPL_030_1_ = NODE,-1,1,-;
|
||||
RN_IPL_030_2_ = NODE,-1,1,-;
|
||||
inst_DS_000_DMA = NODE,*,0,-;
|
||||
inst_CLK_030_H = NODE,*,0,-;
|
||||
SM_AMIGA_3_ = NODE,*,5,-;
|
||||
RN_DSACK1 = NODE,-1,7,-;
|
||||
SM_AMIGA_2_ = NODE,*,5,-;
|
||||
N_96_i = NODE,*,5,-;
|
||||
RN_A0 = NODE,-1,6,-;
|
||||
RN_RW_000 = NODE,-1,7,-;
|
||||
SM_AMIGA_4_ = NODE,*,5,-;
|
||||
CYCLE_DMA_1_ = NODE,*,0,-;
|
||||
RN_RW = NODE,-1,6,-;
|
||||
RN_BG_000 = NODE,-1,3,-;
|
||||
CIIN_0 = NODE,*,4,-;
|
||||
CYCLE_DMA_0_ = NODE,*,0,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-;
|
||||
CLK_000_N_SYNC_10_ = NODE,*,7,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,*,6,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,*,0,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,*,2,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,*,0,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,*,1,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,*,3,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,*,0,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,*,0,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,*,1,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,*,1,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,*,3,-;
|
||||
IPL_D0_2_ = NODE,*,6,-;
|
||||
IPL_D0_1_ = NODE,*,6,-;
|
||||
IPL_D0_0_ = NODE,*,1,-;
|
||||
CLK_000_N_SYNC_11_ = NODE,*,7,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,*,0,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,*,4,-;
|
||||
inst_DTACK_D0 = NODE,*,2,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,*,4,-;
|
||||
inst_DS_030_D0 = NODE,*,0,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
|
|
@ -0,0 +1,272 @@
|
|||
[DEVICE]
|
||||
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = NO;
|
||||
Pin_MC_1to1 = NO;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 5/13/15;
|
||||
TIME = 22:59:29;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
|
||||
Netlist = VHDL;
|
||||
Delay_File = SDF;
|
||||
Generic_VCC = ;
|
||||
Generic_GND = ;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignment = NO;
|
||||
Pin_Block = NO;
|
||||
Pin_Macrocell_Block = NO;
|
||||
Routing = NO;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
|
||||
Balanced_Partitioning = YES;
|
||||
Spread_Placement = YES;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Inter_Seg_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
|
||||
Fitter_Options = YES;
|
||||
Pinout_Diagram = NO;
|
||||
Pinout_Listing = YES;
|
||||
Detailed_Block_Segment_Summary = YES;
|
||||
Input_Signal_List = YES;
|
||||
Output_Signal_List = YES;
|
||||
Bidir_Signal_List = YES;
|
||||
Node_Signal_List = YES;
|
||||
Signal_Fanout_List = YES;
|
||||
Block_Segment_Fanin_List = YES;
|
||||
Prefit_Eqn = YES;
|
||||
Postfit_Eqn = YES;
|
||||
Page_Break = YES;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
|
||||
Logic_Reduction = YES;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = YES;
|
||||
Node_Collapse = Yes;
|
||||
DT_Synthesis = Yes;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = NO;
|
||||
In_Reg_Optimize = YES;
|
||||
Clock_Optimize = NO;
|
||||
Conf_Unused_IOs = OUT_LOW;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low, High;
|
||||
Default = High;
|
||||
Low = 8, H, G, F, E, D, C, B, A;
|
||||
Type = GLB;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW,
|
||||
AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
|
||||
Layer = OFF;
|
||||
A_28_ = INPUT,15, C,-;
|
||||
A_27_ = INPUT,16, C,-;
|
||||
SIZE_1_ = BIDIR,79, H,-;
|
||||
A_26_ = INPUT,17, C,-;
|
||||
A_25_ = INPUT,18, C,-;
|
||||
A_31_ = INPUT,4, B,-;
|
||||
A_24_ = INPUT,19, C,-;
|
||||
A_23_ = INPUT,85, H,-;
|
||||
A_22_ = INPUT,84, H,-;
|
||||
A_21_ = INPUT,94, A,-;
|
||||
IPL_2_ = INPUT,68, G,-;
|
||||
A_20_ = INPUT,93, A,-;
|
||||
A_19_ = INPUT,97, A,-;
|
||||
FC_1_ = INPUT,58, F,-;
|
||||
A_18_ = INPUT,95, A,-;
|
||||
AS_030 = BIDIR,82, H,-;
|
||||
A_17_ = INPUT,59, F,-;
|
||||
AS_000 = BIDIR,42, E,-;
|
||||
A_16_ = INPUT,96, A,-;
|
||||
DS_030 = BIDIR,98, A,-;
|
||||
UDS_000 = BIDIR,32, D,-;
|
||||
LDS_000 = BIDIR,31, D,-;
|
||||
A1 = INPUT,60, F,-;
|
||||
nEXP_SPACE = INPUT,14,-,-;
|
||||
BERR = BIDIR,41, E,-;
|
||||
BG_030 = INPUT,21, C,-;
|
||||
BGACK_000 = INPUT,28, D,-;
|
||||
CLK_030 = INPUT,64,-,-;
|
||||
CLK_000 = INPUT,11,-,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||
CLK_EXP = OUTPUT,10, B,-;
|
||||
IPL_1_ = INPUT,56, F,-;
|
||||
FPU_CS = OUTPUT,78, H,-;
|
||||
IPL_0_ = INPUT,67, G,-;
|
||||
FPU_SENSE = INPUT,91, A,-;
|
||||
FC_0_ = INPUT,57, F,-;
|
||||
DTACK = INPUT,30, D,-;
|
||||
AVEC = OUTPUT,92, A,-;
|
||||
VPA = INPUT,36,-,-;
|
||||
RST = INPUT,86,-,-;
|
||||
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
|
||||
CIIN = OUTPUT,47, E,-;
|
||||
SIZE_0_ = BIDIR,70, G,-;
|
||||
A_30_ = INPUT,5, B,-;
|
||||
A_29_ = INPUT,6, B,-;
|
||||
IPL_030_2_ = OUTPUT,9, B,-;
|
||||
RW_000 = BIDIR,80, H,-;
|
||||
A0 = BIDIR,69, G,-;
|
||||
BG_000 = OUTPUT,29, D,-;
|
||||
BGACK_030 = OUTPUT,83, H,-;
|
||||
IPL_030_1_ = OUTPUT,7, B,-;
|
||||
IPL_030_0_ = OUTPUT,8, B,-;
|
||||
DSACK1 = OUTPUT,81, H,-;
|
||||
E = OUTPUT,66, G,-;
|
||||
VMA = OUTPUT,35, D,-;
|
||||
RESET = OUTPUT,3, B,-;
|
||||
RW = BIDIR,71, G,-;
|
||||
cpu_est_0_ = NODE,1, F,-;
|
||||
cpu_est_1_ = NODE,9, D,-;
|
||||
inst_AS_000_INT = NODE,5, C,-;
|
||||
SM_AMIGA_5_ = NODE,12, F,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,9, C,-;
|
||||
inst_AS_030_D0 = NODE,5, H,-;
|
||||
inst_nEXP_SPACE_D0reg = NODE,5, G,-;
|
||||
inst_DS_030_D0 = NODE,15, A,-;
|
||||
inst_AS_030_000_SYNC = NODE,4, C,-;
|
||||
inst_BGACK_030_INT_D = NODE,13, H,-;
|
||||
inst_AS_000_DMA = NODE,8, A,-;
|
||||
inst_DS_000_DMA = NODE,9, A,-;
|
||||
CYCLE_DMA_0_ = NODE,6, A,-;
|
||||
CYCLE_DMA_1_ = NODE,2, A,-;
|
||||
SIZE_DMA_0_ = NODE,13, G,-;
|
||||
SIZE_DMA_1_ = NODE,9, G,-;
|
||||
inst_VPA_D = NODE,14, B,-;
|
||||
inst_UDS_000_INT = NODE,12, C,-;
|
||||
inst_LDS_000_INT = NODE,8, C,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,13, E,-;
|
||||
inst_DTACK_D0 = NODE,2, C,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,9, E,-;
|
||||
inst_CLK_000_D1 = NODE,2, G,-;
|
||||
inst_CLK_000_D0 = NODE,6, D,-;
|
||||
inst_CLK_000_PE = NODE,0, F,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,11, A,-;
|
||||
inst_CLK_000_NE = NODE,8, E,-;
|
||||
N_96_i = NODE,6, F,-;
|
||||
CLK_000_N_SYNC_11_ = NODE,6, H,-;
|
||||
cpu_est_2_ = NODE,13, D,-;
|
||||
IPL_D0_0_ = NODE,15, B,-;
|
||||
IPL_D0_1_ = NODE,15, G,-;
|
||||
IPL_D0_2_ = NODE,11, G,-;
|
||||
SM_AMIGA_3_ = NODE,13, F,-;
|
||||
inst_CLK_000_NE_D0 = NODE,2, D,-;
|
||||
SM_AMIGA_0_ = NODE,5, B,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,1, C,-;
|
||||
SM_AMIGA_6_ = NODE,9, F,-;
|
||||
RST_DLY_0_ = NODE,6, B,-;
|
||||
RST_DLY_1_ = NODE,1, A,-;
|
||||
RST_DLY_2_ = NODE,9, B,-;
|
||||
RST_DLY_3_ = NODE,12, A,-;
|
||||
RST_DLY_4_ = NODE,5, A,-;
|
||||
RST_DLY_5_ = NODE,13, B,-;
|
||||
RST_DLY_6_ = NODE,2, B,-;
|
||||
RST_DLY_7_ = NODE,10, B,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,15, D,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,7, G,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,3, G,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,11, B,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,7, B,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,14, G,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,10, G,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,7, A,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,3, A,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,11, D,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,3, B,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,7, D,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,3, D,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,14, A,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,13, C,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,14, D,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,10, D,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,10, A,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,6, G,-;
|
||||
CLK_000_N_SYNC_10_ = NODE,2, H,-;
|
||||
inst_CLK_030_H = NODE,13, A,-;
|
||||
SM_AMIGA_1_ = NODE,8, F,-;
|
||||
SM_AMIGA_4_ = NODE,10, F,-;
|
||||
SM_AMIGA_2_ = NODE,2, F,-;
|
||||
inst_DS_000_ENABLE = NODE,5, F,-;
|
||||
SM_AMIGA_i_7_ = NODE,4, F,-;
|
||||
CIIN_0 = NODE,5, E,-;
|
||||
|
|
@ -0,0 +1,221 @@
|
|||
[DEVICE]
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = No;
|
||||
Pin_MC_1to1 = No;
|
||||
EN_PinReserve_IO = Yes;
|
||||
EN_PinReserve_BIDIR = Yes;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
DATE = 03/16/2015;
|
||||
TIME = 21:53:52;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
Pin_Block = No;
|
||||
Pin_Macrocell_Block = No;
|
||||
Routing = No;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
Balanced_Partitioning = Yes;
|
||||
Spread_Placement = Yes;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
Logic_Reduction = Yes;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = Yes;
|
||||
EN_XOR_Synthesis = Yes;
|
||||
XOR_Gate = Yes;
|
||||
Node_Collapse = Yes;
|
||||
Keep_XOR = Yes;
|
||||
DT_Synthesis = Yes;
|
||||
Clock_PTerm = Min;
|
||||
Reset_PTerm = On;
|
||||
Preset_PTerm = On;
|
||||
Clock_Enable_PTerm = On;
|
||||
Output_Enable_PTerm = On;
|
||||
EN_DT_Synthesis = Yes;
|
||||
Cluster_PTerm = 5;
|
||||
FF_inv = No;
|
||||
EN_Use_CE = No;
|
||||
Use_CE = No;
|
||||
Use_Internal_COM_FB = Yes;
|
||||
EN_use_Internal_COM_FB = Yes;
|
||||
Set_Reset_Swap = No;
|
||||
EN_Set_Reset_Swap = No;
|
||||
Density = No;
|
||||
DeMorgan = Yes;
|
||||
T_FF = Yes;
|
||||
Max_Symbols = 32;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = No;
|
||||
EN_Set_Reset_Dont_Care = Yes;
|
||||
In_Reg_Optimize = Yes;
|
||||
EN_In_Reg_Optimize = No;
|
||||
Clock_Optimize = No;
|
||||
Global_Clock_As_Pterm = No;
|
||||
Show_Iterations = No;
|
||||
Routing_Attempts = 2;
|
||||
Conf_Unused_IOs = Out_Low;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW,FAST,7,CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
AS_030 = input,82,H,-;
|
||||
A_16_ = input,96,A,-;
|
||||
A_17_ = input,59,F,-;
|
||||
A_18_ = input,95,A,-;
|
||||
A_19_ = input,97,A,-;
|
||||
BGACK_000 = input,28,D,-;
|
||||
BG_030 = input,21,C,-;
|
||||
CLK_000 = input,11,-,-;
|
||||
CLK_030 = input,64,-,-;
|
||||
CLK_OSZI = input,61,-,-;
|
||||
FC_0_ = input,57,F,-;
|
||||
FC_1_ = input,58,F,-;
|
||||
IPL_0_ = input,67,G,-;
|
||||
IPL_1_ = input,56,F,-;
|
||||
IPL_2_ = input,68,G,-;
|
||||
RST = input,86,-,-;
|
||||
RW = input,71,G,-;
|
||||
SIZE_1_ = input,79,H,-;
|
||||
SIZE_0_ = input,70,G,-;
|
||||
VPA = input,36,-,-;
|
||||
AVEC = input,92,A,-;
|
||||
BGACK_030 = input,83,H,-;
|
||||
BG_000 = input,29,D,-;
|
||||
CLK_DIV_OUT = input,65,G,-;
|
||||
CLK_EXP = input,10,B,-;
|
||||
E = input,66,G,-;
|
||||
FPU_CS = input,78,H,-;
|
||||
IPL_030_0_ = input,8,B,-;
|
||||
IPL_030_1_ = input,7,B,-;
|
||||
IPL_030_2_ = input,9,B,-;
|
||||
LDS_000 = input,31,D,-;
|
||||
UDS_000 = input,32,D,-;
|
||||
VMA = input,35,D,-;
|
||||
DTACK = input,30,D,-;
|
||||
RESET = input,3,B,-;
|
||||
AMIGA_BUS_DATA_DIR = input,48,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = input,20,C,-;
|
||||
CIIN = input,47,E,-;
|
||||
A_20_ = input,93,A,-;
|
||||
A_21_ = input,94,A,-;
|
||||
A_22_ = input,84,H,-;
|
||||
A_24_ = input,19,C,-;
|
||||
A_25_ = input,18,C,-;
|
||||
A_26_ = input,17,C,-;
|
||||
A_27_ = input,16,C,-;
|
||||
A_28_ = input,15,C,-;
|
||||
A_29_ = input,6,B,-;
|
||||
A_30_ = input,5,B,-;
|
||||
A_31_ = input,4,B,-;
|
||||
DS_030 = input,98,A,-;
|
||||
BERR = input,41,E,-;
|
||||
nEXP_SPACE = input,14,-,-;
|
||||
A0 = input,69,G,-;
|
||||
DSACK1 = input,81,H,-;
|
||||
RW_000 = input,80,H,-;
|
||||
AS_000 = input,42,E,-;
|
||||
AMIGA_ADDR_ENABLE = input,33,D,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = input,34,D,-;
|
||||
A_23_ = input,85,H,-;
|
||||
FPU_SENSE = input,91,A,-;
|
||||
A1 = input,60,F,-;
|
||||
A_3_ = input,44,E,-;
|
||||
A_2_ = input,43,E,-;
|
||||
|
||||
[GROUP ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
|
||||
[SPACE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
VCC_GND = Cell;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = 8,H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
Import_source_constraint = Yes;
|
||||
Disable_warning_message = No;
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
||||
[INPUT REGISTERS]
|
||||
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
Signal Name Cross Reference File
|
||||
|
||||
ispLEVER Classic 1.8.00.04.29.14
|
||||
|
||||
Design '68030_tk' created Wed May 13 22:59:21 2015
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
'/' Hierarchy Path Separator
|
||||
'@' Automatically Generated Node
|
||||
|
||||
|
||||
Short Name Hierarchical Name
|
||||
---------- -----------------
|
||||
|
||||
*** Shortened names not required for this design. ***
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,8 @@
|
|||
STYFILENAME: 68030_tk.sty
|
||||
PROJECT: BUS68030
|
||||
WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic"
|
||||
MODULE: BUS68030
|
||||
VHDL_FILE_LIST: 68030-68000-bus.vhd
|
||||
OUTPUT_FILE_NAME: BUS68030
|
||||
SUFFIX_NAME: edi
|
||||
PART: M4A5-128/64-10VC
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,20 +1,20 @@
|
|||
|
||||
fsm_encoding {7137371371} onehot
|
||||
fsm_encoding {7139371391} onehot
|
||||
|
||||
fsm_state_encoding {7137371371} idle_p {00000000}
|
||||
fsm_state_encoding {7139371391} idle_p {00000000}
|
||||
|
||||
fsm_state_encoding {7137371371} idle_n {00000011}
|
||||
fsm_state_encoding {7139371391} idle_n {00000011}
|
||||
|
||||
fsm_state_encoding {7137371371} as_set_p {00000101}
|
||||
fsm_state_encoding {7139371391} as_set_p {00000101}
|
||||
|
||||
fsm_state_encoding {7137371371} as_set_n {00001001}
|
||||
fsm_state_encoding {7139371391} as_set_n {00001001}
|
||||
|
||||
fsm_state_encoding {7137371371} sample_dtack_p {00010001}
|
||||
fsm_state_encoding {7139371391} sample_dtack_p {00010001}
|
||||
|
||||
fsm_state_encoding {7137371371} data_fetch_n {00100001}
|
||||
fsm_state_encoding {7139371391} data_fetch_n {00100001}
|
||||
|
||||
fsm_state_encoding {7137371371} data_fetch_p {01000001}
|
||||
fsm_state_encoding {7139371391} data_fetch_p {01000001}
|
||||
|
||||
fsm_state_encoding {7137371371} end_cycle_n {10000001}
|
||||
fsm_state_encoding {7139371391} end_cycle_n {10000001}
|
||||
|
||||
fsm_registers {7137371371} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}
|
||||
fsm_registers {7139371391} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,75 @@
|
|||
AS_030 b
|
||||
AS_000 b
|
||||
RW_000 b
|
||||
DS_030 b
|
||||
UDS_000 b
|
||||
LDS_000 b
|
||||
SIZE[1] b
|
||||
SIZE[0] b
|
||||
A[31] i
|
||||
A[30] i
|
||||
A[29] i
|
||||
A[28] i
|
||||
A[27] i
|
||||
A[26] i
|
||||
A[25] i
|
||||
A[24] i
|
||||
A[23] i
|
||||
A[22] i
|
||||
A[21] i
|
||||
A[20] i
|
||||
A[19] i
|
||||
A[18] i
|
||||
A[17] i
|
||||
A[16] i
|
||||
A[15] i
|
||||
A[14] i
|
||||
A[13] i
|
||||
A[12] i
|
||||
A[11] i
|
||||
A[10] i
|
||||
A[9] i
|
||||
A[8] i
|
||||
A[7] i
|
||||
A[6] i
|
||||
A[5] i
|
||||
A[4] i
|
||||
A[3] i
|
||||
A[2] i
|
||||
A0 b
|
||||
A1 i
|
||||
nEXP_SPACE i
|
||||
BERR b
|
||||
BG_030 i
|
||||
BG_000 o
|
||||
BGACK_030 o
|
||||
BGACK_000 i
|
||||
CLK_030 i
|
||||
CLK_000 i
|
||||
CLK_OSZI i
|
||||
CLK_DIV_OUT o
|
||||
CLK_EXP o
|
||||
FPU_CS o
|
||||
FPU_SENSE i
|
||||
IPL_030[2] o
|
||||
IPL_030[1] o
|
||||
IPL_030[0] o
|
||||
IPL[2] i
|
||||
IPL[1] i
|
||||
IPL[0] i
|
||||
DSACK1 b
|
||||
DTACK b
|
||||
AVEC o
|
||||
E o
|
||||
VPA i
|
||||
VMA o
|
||||
RST i
|
||||
RESET o
|
||||
RW b
|
||||
FC[1] i
|
||||
FC[0] i
|
||||
AMIGA_ADDR_ENABLE o
|
||||
AMIGA_BUS_DATA_DIR o
|
||||
AMIGA_BUS_ENABLE_LOW o
|
||||
AMIGA_BUS_ENABLE_HIGH o
|
||||
CIIN o
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Sat Mar 28 22:02:32 2015
|
||||
#-- Written on Wed May 13 22:59:07 2015
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,107 @@
|
|||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: C:\ispLever\synpbase
|
||||
#OS: Windows 7 6.1
|
||||
#Hostname: DEEPTHOUGHT
|
||||
|
||||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Wed May 13 22:59:14 2015
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
001
|
||||
010
|
||||
011
|
||||
100
|
||||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Wed May 13 22:59:15 2015
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Wed May 13 22:59:16 2015
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030)
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
001 -> 00000011
|
||||
010 -> 00000101
|
||||
011 -> 00001001
|
||||
100 -> 00010001
|
||||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 83 uses
|
||||
BI_DIR 11 uses
|
||||
IBUF 46 uses
|
||||
OBUF 15 uses
|
||||
BUFTH 3 uses
|
||||
AND2 303 uses
|
||||
INV 263 uses
|
||||
XOR2 15 uses
|
||||
OR2 28 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Wed May 13 22:59:16 2015
|
||||
|
||||
###########################################################]
|
||||
Binary file not shown.
|
|
@ -0,0 +1 @@
|
|||
Need not generate svf file according to the constraints, exit
|
||||
|
|
@ -0,0 +1,882 @@
|
|||
Section Type Array Num Name Real Name Base Number Increment
|
||||
// -------------------------------------------------------------------------------------------------
|
||||
Port 1 A(31:2) A 31 30 -1
|
||||
Port 2 IPL(2:0) IPL 2 3 -1
|
||||
Port 3 FC(1:0) FC 1 2 -1
|
||||
Port 4 IPL_030(2:0) IPL_030 2 3 -1
|
||||
Port 5 SIZE(1:0) SIZE 1 2 -1
|
||||
End
|
||||
Section Member Rename Array-Notation Array Number Index
|
||||
// -------------------------------------------------------------------------------------
|
||||
Port SIZE_1_ SIZE[1] 5 0
|
||||
Port SIZE_0_ SIZE[0] 5 1
|
||||
Port A_31_ A[31] 1 0
|
||||
Port A_30_ A[30] 1 1
|
||||
Port A_29_ A[29] 1 2
|
||||
Port A_28_ A[28] 1 3
|
||||
Port A_27_ A[27] 1 4
|
||||
Port A_26_ A[26] 1 5
|
||||
Port A_25_ A[25] 1 6
|
||||
Port A_24_ A[24] 1 7
|
||||
Port A_23_ A[23] 1 8
|
||||
Port A_22_ A[22] 1 9
|
||||
Port A_21_ A[21] 1 10
|
||||
Port A_20_ A[20] 1 11
|
||||
Port A_19_ A[19] 1 12
|
||||
Port A_18_ A[18] 1 13
|
||||
Port A_17_ A[17] 1 14
|
||||
Port A_16_ A[16] 1 15
|
||||
Port A_15_ A[15] 1 16
|
||||
Port A_14_ A[14] 1 17
|
||||
Port A_13_ A[13] 1 18
|
||||
Port A_12_ A[12] 1 19
|
||||
Port A_11_ A[11] 1 20
|
||||
Port A_10_ A[10] 1 21
|
||||
Port A_9_ A[9] 1 22
|
||||
Port A_8_ A[8] 1 23
|
||||
Port A_7_ A[7] 1 24
|
||||
Port A_6_ A[6] 1 25
|
||||
Port A_5_ A[5] 1 26
|
||||
Port A_4_ A[4] 1 27
|
||||
Port A_3_ A[3] 1 28
|
||||
Port A_2_ A[2] 1 29
|
||||
Port IPL_030_2_ IPL_030[2] 4 0
|
||||
Port IPL_030_1_ IPL_030[1] 4 1
|
||||
Port IPL_030_0_ IPL_030[0] 4 2
|
||||
Port IPL_2_ IPL[2] 2 0
|
||||
Port IPL_1_ IPL[1] 2 1
|
||||
Port IPL_0_ IPL[0] 2 2
|
||||
Port FC_1_ FC[1] 3 0
|
||||
Port FC_0_ FC[0] 3 1
|
||||
End
|
||||
Section Cross Reference File
|
||||
Design 'BUS68030' created Wed May 13 22:59:21 2015
|
||||
Type New Name Original Name
|
||||
// ----------------------------------------------------------------------
|
||||
Inst i_z4141 AS_030
|
||||
Inst i_z4242 AS_000
|
||||
Inst i_z4343 RW_000
|
||||
Inst i_z4444 DS_030
|
||||
Inst i_z4545 UDS_000
|
||||
Inst i_z4646 LDS_000
|
||||
Inst i_z5757 A0
|
||||
Inst i_z5A5A BERR
|
||||
Inst i_z5I5I CLK_DIV_OUT
|
||||
Inst i_z5S5S DSACK1
|
||||
Inst i_z6464 RW
|
||||
Inst i_z6B6B CIIN
|
||||
Inst pos_clk_un7_clk_000_pe_0_a2 pos_clk.un7_clk_000_pe_0_a2
|
||||
Inst DSACK1_INT_0_n DSACK1_INT_0.n
|
||||
Inst DSACK1_INT_0_p DSACK1_INT_0.p
|
||||
Inst AS_000_INT_0_r AS_000_INT_0.r
|
||||
Inst AS_000_INT_0_m AS_000_INT_0.m
|
||||
Inst BGACK_030_INT_0_r BGACK_030_INT_0.r
|
||||
Inst AS_000_INT_0_n AS_000_INT_0.n
|
||||
Inst BGACK_030_INT_0_m BGACK_030_INT_0.m
|
||||
Inst AS_000_INT_0_p AS_000_INT_0.p
|
||||
Inst BGACK_030_INT_0_n BGACK_030_INT_0.n
|
||||
Inst pos_clk_un6_bg_030_1 pos_clk.un6_bg_030_1
|
||||
Inst BGACK_030_INT_0_p BGACK_030_INT_0.p
|
||||
Inst DS_000_ENABLE_0_r DS_000_ENABLE_0.r
|
||||
Inst pos_clk_un6_bg_030 pos_clk.un6_bg_030
|
||||
Inst VMA_INT_0_r VMA_INT_0.r
|
||||
Inst DS_000_ENABLE_0_m DS_000_ENABLE_0.m
|
||||
Inst SM_AMIGA_nss_i_i_0_1_0_ SM_AMIGA_nss_i_i_0_1[0]
|
||||
Inst VMA_INT_0_m VMA_INT_0.m
|
||||
Inst DS_000_ENABLE_0_n DS_000_ENABLE_0.n
|
||||
Inst SM_AMIGA_nss_i_i_0_2_0_ SM_AMIGA_nss_i_i_0_2[0]
|
||||
Inst VMA_INT_0_n VMA_INT_0.n
|
||||
Inst DS_000_ENABLE_0_p DS_000_ENABLE_0.p
|
||||
Inst SM_AMIGA_nss_i_i_0_3_0_ SM_AMIGA_nss_i_i_0_3[0]
|
||||
Inst VMA_INT_0_p VMA_INT_0.p
|
||||
Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r
|
||||
Inst SM_AMIGA_nss_i_i_0_0_ SM_AMIGA_nss_i_i_0[0]
|
||||
Inst RW_000_INT_0_r RW_000_INT_0.r
|
||||
Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_1_1_0_ SM_AMIGA_nss_i_i_0_a2_1_1[0]
|
||||
Inst RW_000_INT_0_m RW_000_INT_0.m
|
||||
Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_1_2_0_ SM_AMIGA_nss_i_i_0_a2_1_2[0]
|
||||
Inst RW_000_INT_0_n RW_000_INT_0.n
|
||||
Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_1_3_0_ SM_AMIGA_nss_i_i_0_a2_1_3[0]
|
||||
Inst RW_000_INT_0_p RW_000_INT_0.p
|
||||
Inst LDS_000_INT_0_r LDS_000_INT_0.r
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_1_0_ SM_AMIGA_nss_i_i_0_a2_1[0]
|
||||
Inst LDS_000_INT_0_m LDS_000_INT_0.m
|
||||
Inst pos_clk_cpu_est_11_0_0_1_1_ pos_clk.cpu_est_11_0_0_1[1]
|
||||
Inst LDS_000_INT_0_n LDS_000_INT_0.n
|
||||
Inst pos_clk_cpu_est_11_0_0_2_1_ pos_clk.cpu_est_11_0_0_2[1]
|
||||
Inst pos_clk_RST_DLY_5_iv_0_x2_0_ pos_clk.RST_DLY_5_iv_0_x2[0]
|
||||
Inst LDS_000_INT_0_p LDS_000_INT_0.p
|
||||
Inst pos_clk_un37_as_030_d0_i_a2_1_4 pos_clk.un37_as_030_d0_i_a2_1_4
|
||||
Inst RW_000_DMA_0_r RW_000_DMA_0.r
|
||||
Inst pos_clk_un37_as_030_d0_i_a2_1 pos_clk.un37_as_030_d0_i_a2_1
|
||||
Inst pos_clk_RST_DLY_5_iv_0_0_ pos_clk.RST_DLY_5_iv_0[0]
|
||||
Inst RW_000_DMA_0_m RW_000_DMA_0.m
|
||||
Inst SM_AMIGA_srsts_i_i_o2_2_ SM_AMIGA_srsts_i_i_o2[2]
|
||||
Inst RW_000_DMA_0_n RW_000_DMA_0.n
|
||||
Inst SM_AMIGA_i_4_ SM_AMIGA_i[4]
|
||||
Inst RW_000_DMA_0_p RW_000_DMA_0.p
|
||||
Inst SM_AMIGA_srsts_i_0_o2_4_ SM_AMIGA_srsts_i_0_o2[4]
|
||||
Inst UDS_000_INT_0_r UDS_000_INT_0.r
|
||||
Inst cpu_est_0_0_x2_0_ cpu_est_0_0_x2[0]
|
||||
Inst UDS_000_INT_0_m UDS_000_INT_0.m
|
||||
Inst UDS_000_INT_0_n UDS_000_INT_0.n
|
||||
Inst UDS_000_INT_0_p UDS_000_INT_0.p
|
||||
Inst SM_AMIGA_srsts_i_0_m2_3__r SM_AMIGA_srsts_i_0_m2_3_.r
|
||||
Inst SM_AMIGA_srsts_i_0_m2_3__m SM_AMIGA_srsts_i_0_m2_3_.m
|
||||
Inst AMIGA_BUS_ENABLE_DMA_LOW_0_r AMIGA_BUS_ENABLE_DMA_LOW_0.r
|
||||
Inst SM_AMIGA_srsts_i_0_m2_3__n SM_AMIGA_srsts_i_0_m2_3_.n
|
||||
Inst AMIGA_BUS_ENABLE_DMA_LOW_0_m AMIGA_BUS_ENABLE_DMA_LOW_0.m
|
||||
Inst SM_AMIGA_srsts_i_0_m2_3__p SM_AMIGA_srsts_i_0_m2_3_.p
|
||||
Inst AMIGA_BUS_ENABLE_DMA_LOW_0_n AMIGA_BUS_ENABLE_DMA_LOW_0.n
|
||||
Inst pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk.CYCLE_DMA_5_1_i_x2
|
||||
Inst AMIGA_BUS_ENABLE_DMA_LOW_0_p AMIGA_BUS_ENABLE_DMA_LOW_0.p
|
||||
Inst pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk.CYCLE_DMA_5_0_i_x2
|
||||
Inst cpu_est_i_1_ cpu_est_i[1]
|
||||
Inst pos_clk_un3_ds_030_d0 pos_clk.un3_ds_030_d0
|
||||
Inst SM_AMIGA_srsts_i_0_2_5_ SM_AMIGA_srsts_i_0_2[5]
|
||||
Inst SM_AMIGA_srsts_i_0_5_ SM_AMIGA_srsts_i_0[5]
|
||||
Inst pos_clk_un24_bgack_030_int_i_0_o2_1 pos_clk.un24_bgack_030_int_i_0_o2_1
|
||||
Inst cpu_est_i_3_ cpu_est_i[3]
|
||||
Inst pos_clk_un8_bg_030 pos_clk.un8_bg_030
|
||||
Inst pos_clk_un24_bgack_030_int_i_0_o2 pos_clk.un24_bgack_030_int_i_0_o2
|
||||
Inst cpu_est_i_0_ cpu_est_i[0]
|
||||
Inst pos_clk_un37_as_030_d0_i_o4_1 pos_clk.un37_as_030_d0_i_o4_1
|
||||
Inst pos_clk_un37_as_030_d0_i_o4 pos_clk.un37_as_030_d0_i_o4
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_1_1_ pos_clk.cpu_est_11_0_0_a2_1[1]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_1_1_0_ SM_AMIGA_nss_i_i_0_o4_1_1[0]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_1_0_ SM_AMIGA_nss_i_i_0_o4_1[0]
|
||||
Inst SM_AMIGA_srsts_i_i_a2_3_2_ SM_AMIGA_srsts_i_i_a2_3[2]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_1_0_0_ SM_AMIGA_nss_i_i_0_o4_1_0[0]
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_2_1_ pos_clk.cpu_est_11_0_0_a2_2[1]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_0_ SM_AMIGA_nss_i_i_0_o4[0]
|
||||
Inst SM_AMIGA_srsts_i_i_a2_1_2_ SM_AMIGA_srsts_i_i_a2_1[2]
|
||||
Inst pos_clk_un11_ds_030_d0_1 pos_clk.un11_ds_030_d0_1
|
||||
Inst pos_clk_cpu_est_11_i_0_2_ pos_clk.cpu_est_11_i_0[2]
|
||||
Inst pos_clk_un11_ds_030_d0 pos_clk.un11_ds_030_d0
|
||||
Inst SM_AMIGA_i_5_ SM_AMIGA_i[5]
|
||||
Inst IPL_030DFF_2_ IPL_030DFF[2]
|
||||
Inst pos_clk_un37_as_030_d0_i_a2_1_1 pos_clk.un37_as_030_d0_i_a2_1_1
|
||||
Inst IPL_D0_0_ IPL_D0[0]
|
||||
Inst pos_clk_un37_as_030_d0_i_a2_1_2 pos_clk.un37_as_030_d0_i_a2_1_2
|
||||
Inst pos_clk_un7_clk_000_pe_0 pos_clk.un7_clk_000_pe_0
|
||||
Inst IPL_D0_1_ IPL_D0[1]
|
||||
Inst pos_clk_un37_as_030_d0_i_a2_1_3 pos_clk.un37_as_030_d0_i_a2_1_3
|
||||
Inst SM_AMIGA_srsts_i_i_o2_0_2_ SM_AMIGA_srsts_i_i_o2_0[2]
|
||||
Inst IPL_D0_2_ IPL_D0[2]
|
||||
Inst SM_AMIGA_srsts_i_o3_0_i_o2_0_ SM_AMIGA_srsts_i_o3_0_i_o2[0]
|
||||
Inst SM_AMIGA_i_7_ SM_AMIGA_i[7]
|
||||
Inst cpu_est_i_2_ cpu_est_i[2]
|
||||
Inst SM_AMIGA_6_ SM_AMIGA[6]
|
||||
Inst pos_clk_cpu_est_11_i_0_o2_2_ pos_clk.cpu_est_11_i_0_o2[2]
|
||||
Inst SM_AMIGA_5_ SM_AMIGA[5]
|
||||
Inst pos_clk_cpu_est_11_0_0_o2_1_ pos_clk.cpu_est_11_0_0_o2[1]
|
||||
Inst SM_AMIGA_4_ SM_AMIGA[4]
|
||||
Inst pos_clk_cpu_est_11_0_0_o2_3_ pos_clk.cpu_est_11_0_0_o2[3]
|
||||
Inst SM_AMIGA_3_ SM_AMIGA[3]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_3_ SM_AMIGA_srsts_i_0_a2[3]
|
||||
Inst SM_AMIGA_2_ SM_AMIGA[2]
|
||||
Inst SM_AMIGA_srsts_i_o3_0_o2_3_ SM_AMIGA_srsts_i_o3_0_o2[3]
|
||||
Inst SM_AMIGA_1_ SM_AMIGA[1]
|
||||
Inst SM_AMIGA_i_0_ SM_AMIGA_i[0]
|
||||
Inst SM_AMIGA_0_ SM_AMIGA[0]
|
||||
Inst SM_AMIGA_i_3_ SM_AMIGA_i[3]
|
||||
Inst cpu_est_0_ cpu_est[0]
|
||||
Inst cpu_est_1_ cpu_est[1]
|
||||
Inst cpu_est_2_ cpu_est[2]
|
||||
Inst pos_clk_un4_bgack_000_i_a2 pos_clk.un4_bgack_000_i_a2
|
||||
Inst cpu_est_3_ cpu_est[3]
|
||||
Inst pos_clk_un6_bg_030_i pos_clk.un6_bg_030_i
|
||||
Inst IPL_030DFF_0_ IPL_030DFF[0]
|
||||
Inst pos_clk_un8_bg_030_i pos_clk.un8_bg_030_i
|
||||
Inst SM_AMIGA_srsts_i_0_m2_1__r SM_AMIGA_srsts_i_0_m2_1_.r
|
||||
Inst IPL_030DFF_1_ IPL_030DFF[1]
|
||||
Inst SM_AMIGA_srsts_i_0_1_5_ SM_AMIGA_srsts_i_0_1[5]
|
||||
Inst SM_AMIGA_srsts_i_0_m2_1__m SM_AMIGA_srsts_i_0_m2_1_.m
|
||||
Inst CLK_000_N_SYNC_9_ CLK_000_N_SYNC[9]
|
||||
Inst IPL_D0_0_i_0_ IPL_D0_0_i[0]
|
||||
Inst SM_AMIGA_srsts_i_0_m2_1__n SM_AMIGA_srsts_i_0_m2_1_.n
|
||||
Inst CLK_000_N_SYNC_10_ CLK_000_N_SYNC[10]
|
||||
Inst SM_AMIGA_srsts_i_0_m2_1__p SM_AMIGA_srsts_i_0_m2_1_.p
|
||||
Inst CLK_000_N_SYNC_11_ CLK_000_N_SYNC[11]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_4_ SM_AMIGA_srsts_i_0_a2[4]
|
||||
Inst RST_DLY_0_ RST_DLY[0]
|
||||
Inst RST_DLY_1_ RST_DLY[1]
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_3_ pos_clk.cpu_est_11_0_0_a2[3]
|
||||
Inst RST_DLY_2_ RST_DLY[2]
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_0_3_ pos_clk.cpu_est_11_0_0_a2_0[3]
|
||||
Inst RST_DLY_3_ RST_DLY[3]
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_1_ pos_clk.cpu_est_11_0_0_a2[1]
|
||||
Inst RST_DLY_4_ RST_DLY[4]
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_0_1_ pos_clk.cpu_est_11_0_0_a2_0[1]
|
||||
Inst RST_DLY_5_ RST_DLY[5]
|
||||
Inst pos_clk_un9_clk_000_n_sync pos_clk.un9_clk_000_n_sync
|
||||
Inst RST_DLY_6_ RST_DLY[6]
|
||||
Inst RST_DLY_7_ RST_DLY[7]
|
||||
Inst pos_clk_un11_clk_000_n_sync pos_clk.un11_clk_000_n_sync
|
||||
Inst CYCLE_DMA_0_ CYCLE_DMA[0]
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_2_0_ SM_AMIGA_nss_i_i_0_a2_2[0]
|
||||
Inst CYCLE_DMA_1_ CYCLE_DMA[1]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_0_ SM_AMIGA_srsts_i_0_a2[0]
|
||||
Inst SIZE_DMA_0_ SIZE_DMA[0]
|
||||
Inst SM_AMIGA_nss_i_i_0_a4_0_ SM_AMIGA_nss_i_i_0_a4[0]
|
||||
Inst SIZE_DMA_1_ SIZE_DMA[1]
|
||||
Inst SM_AMIGA_srsts_i_0_0_ SM_AMIGA_srsts_i_0[0]
|
||||
Inst CLK_000_P_SYNC_5_ CLK_000_P_SYNC[5]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_0_0_ SM_AMIGA_nss_i_i_0_o4_0[0]
|
||||
Inst CLK_000_P_SYNC_6_ CLK_000_P_SYNC[6]
|
||||
Inst SM_AMIGA_nss_i_i_0_o2_0_ SM_AMIGA_nss_i_i_0_o2[0]
|
||||
Inst CLK_000_P_SYNC_7_ CLK_000_P_SYNC[7]
|
||||
Inst SM_AMIGA_i_1_ SM_AMIGA_i[1]
|
||||
Inst CLK_000_P_SYNC_8_ CLK_000_P_SYNC[8]
|
||||
Inst SIZE_c_i_1_ SIZE_c_i[1]
|
||||
Inst SM_AMIGA_srsts_i_0_o4_0_ SM_AMIGA_srsts_i_0_o4[0]
|
||||
Inst CLK_000_P_SYNC_9_ CLK_000_P_SYNC[9]
|
||||
Inst SM_AMIGA_i_6_ SM_AMIGA_i[6]
|
||||
Inst CLK_000_N_SYNC_0_ CLK_000_N_SYNC[0]
|
||||
Inst IPL_030_1_i_2_ IPL_030_1_i[2]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_0_6_ SM_AMIGA_srsts_i_0_a2_0[6]
|
||||
Inst CLK_000_N_SYNC_1_ CLK_000_N_SYNC[1]
|
||||
Inst CLK_000_N_SYNC_2_ CLK_000_N_SYNC[2]
|
||||
Inst IPL_030_1_i_1_ IPL_030_1_i[1]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_0_4_ SM_AMIGA_srsts_i_0_a2_0[4]
|
||||
Inst CLK_000_N_SYNC_3_ CLK_000_N_SYNC[3]
|
||||
Inst CLK_000_N_SYNC_4_ CLK_000_N_SYNC[4]
|
||||
Inst IPL_030_1_i_0_ IPL_030_1_i[0]
|
||||
Inst CLK_000_N_SYNC_5_ CLK_000_N_SYNC[5]
|
||||
Inst IPL_c_i_2_ IPL_c_i[2]
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_a2_0_ pos_clk.SIZE_DMA_6_0_0_a2[0]
|
||||
Inst CLK_000_N_SYNC_6_ CLK_000_N_SYNC[6]
|
||||
Inst IPL_D0_0_i_2_ IPL_D0_0_i[2]
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_a2_1_ pos_clk.SIZE_DMA_6_0_0_a2[1]
|
||||
Inst CLK_000_N_SYNC_7_ CLK_000_N_SYNC[7]
|
||||
Inst IPL_c_i_1_ IPL_c_i[1]
|
||||
Inst SM_AMIGA_i_2_ SM_AMIGA_i[2]
|
||||
Inst CLK_000_N_SYNC_8_ CLK_000_N_SYNC[8]
|
||||
Inst IPL_D0_0_i_1_ IPL_D0_0_i[1]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_1_ SM_AMIGA_srsts_i_0_a2[1]
|
||||
Inst CLK_000_P_SYNC_0_ CLK_000_P_SYNC[0]
|
||||
Inst IPL_c_i_0_ IPL_c_i[0]
|
||||
Inst CLK_000_P_SYNC_1_ CLK_000_P_SYNC[1]
|
||||
Inst pos_clk_cpu_est_11_0_0_i_3_ pos_clk.cpu_est_11_0_0_i[3]
|
||||
Inst CLK_000_P_SYNC_2_ CLK_000_P_SYNC[2]
|
||||
Inst CLK_000_P_SYNC_3_ CLK_000_P_SYNC[3]
|
||||
Inst CLK_000_P_SYNC_4_ CLK_000_P_SYNC[4]
|
||||
Inst pos_clk_DS_000_DMA_4_f0_0_i pos_clk.DS_000_DMA_4_f0_0_i
|
||||
Inst pos_clk_un22_bgack_030_int pos_clk.un22_bgack_030_int
|
||||
Inst pos_clk_un14_clk_000_n_sync pos_clk.un14_clk_000_n_sync
|
||||
Inst pos_clk_un11_clk_000_n_sync_i pos_clk.un11_clk_000_n_sync_i
|
||||
Inst pos_clk_un37_as_030_d0_i pos_clk.un37_as_030_d0_i
|
||||
Inst pos_clk_un24_bgack_030_int_i_0_o2_i pos_clk.un24_bgack_030_int_i_0_o2_i
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_0_ pos_clk.SIZE_DMA_6_0_0[0]
|
||||
Inst SM_AMIGA_srsts_i_0_o2_i_6_ SM_AMIGA_srsts_i_0_o2_i[6]
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_1_ pos_clk.SIZE_DMA_6_0_0[1]
|
||||
Inst SM_AMIGA_srsts_i_0_o2_i_5_ SM_AMIGA_srsts_i_0_o2_i[5]
|
||||
Inst pos_clk_CLK_000_P_SYNC_2_0_a2_0_ pos_clk.CLK_000_P_SYNC_2_0_a2[0]
|
||||
Inst pos_clk_un37_as_030_d0_i_a2_0 pos_clk.un37_as_030_d0_i_a2_0
|
||||
Inst pos_clk_un37_as_030_d0_i_a2 pos_clk.un37_as_030_d0_i_a2
|
||||
Inst pos_clk_A0_DMA_3_0_a2 pos_clk.A0_DMA_3_0_a2
|
||||
Inst pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2
|
||||
Inst pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2
|
||||
Inst SM_AMIGA_srsts_i_i_i_2_ SM_AMIGA_srsts_i_i_i[2]
|
||||
Inst pos_clk_DS_000_DMA_4_f0_0_a2 pos_clk.DS_000_DMA_4_f0_0_a2
|
||||
Inst SM_AMIGA_srsts_i_0_a2_1_5_ SM_AMIGA_srsts_i_0_a2_1[5]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_0_5_ SM_AMIGA_srsts_i_0_a2_0[5]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_5_ SM_AMIGA_srsts_i_0_a2[5]
|
||||
Inst SM_AMIGA_srsts_i_0_a2_6_ SM_AMIGA_srsts_i_0_a2[6]
|
||||
Inst pos_clk_un37_as_030_d0_i_i pos_clk.un37_as_030_d0_i_i
|
||||
Inst SM_AMIGA_srsts_i_0_o4_1_ SM_AMIGA_srsts_i_0_o4[1]
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_o4_0_ pos_clk.SIZE_DMA_6_0_0_o4[0]
|
||||
Inst pos_clk_un3_as_030_d0_i_i_o2 pos_clk.un3_as_030_d0_i_i_o2
|
||||
Inst pos_clk_CLK_000_N_SYNC_2_0_o4_0_ pos_clk.CLK_000_N_SYNC_2_0_o4[0]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_i_0_ SM_AMIGA_nss_i_i_0_o4_i[0]
|
||||
Inst pos_clk_un3_as_030_d0_i_i_o2_i pos_clk.un3_as_030_d0_i_i_o2_i
|
||||
Inst SM_AMIGA_srsts_i_0_o2_5_ SM_AMIGA_srsts_i_0_o2[5]
|
||||
Inst SM_AMIGA_srsts_i_0_o2_6_ SM_AMIGA_srsts_i_0_o2[6]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_1_i_0_ SM_AMIGA_nss_i_i_0_o4_1_i[0]
|
||||
Inst pos_clk_CYCLE_DMA_5_1_i_o2 pos_clk.CYCLE_DMA_5_1_i_o2
|
||||
Inst SIZE_0_ SIZE[0]
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_o4_i_0_ pos_clk.SIZE_DMA_6_0_0_o4_i[0]
|
||||
Inst pos_clk_un24_bgack_030_int_i_0_x2 pos_clk.un24_bgack_030_int_i_0_x2
|
||||
Inst SIZE_1_ SIZE[1]
|
||||
Inst SM_AMIGA_srsts_i_0_o4_i_1_ SM_AMIGA_srsts_i_0_o4_i[1]
|
||||
Inst pos_clk_un37_as_030_d0_i_o4_i pos_clk.un37_as_030_d0_i_o4_i
|
||||
Inst pos_clk_DS_000_DMA_4_f0_0 pos_clk.DS_000_DMA_4_f0_0
|
||||
Inst SM_AMIGA_i_i_7_ SM_AMIGA_i_i[7]
|
||||
Inst SM_AMIGA_nss_i_i_0_o4_0_i_0_ SM_AMIGA_nss_i_i_0_o4_0_i[0]
|
||||
Inst SM_AMIGA_srsts_i_i_2_ SM_AMIGA_srsts_i_i[2]
|
||||
Inst CLK_000_N_SYNC_i_10_ CLK_000_N_SYNC_i[10]
|
||||
Inst pos_clk_un9_clk_000_n_sync_i pos_clk.un9_clk_000_n_sync_i
|
||||
Inst pos_clk_un14_clk_000_n_sync_i pos_clk.un14_clk_000_n_sync_i
|
||||
Inst pos_clk_un22_bgack_030_int_i_0 pos_clk.un22_bgack_030_int_i_0
|
||||
Inst A_i_16_ A_i[16]
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_i_1_ pos_clk.SIZE_DMA_6_0_0_i[1]
|
||||
Inst SIZE_DMA_i_1_ SIZE_DMA_i[1]
|
||||
Inst A_16_ A[16]
|
||||
Inst pos_clk_SIZE_DMA_6_0_0_i_0_ pos_clk.SIZE_DMA_6_0_0_i[0]
|
||||
Inst SIZE_DMA_i_0_ SIZE_DMA_i[0]
|
||||
Inst A_17_ A[17]
|
||||
Inst A_18_ A[18]
|
||||
Inst A_19_ A[19]
|
||||
Inst pos_clk_un7_clk_000_pe_0_i pos_clk.un7_clk_000_pe_0_i
|
||||
Inst A_i_24_ A_i[24]
|
||||
Inst A_20_ A[20]
|
||||
Inst A_21_ A[21]
|
||||
Inst A_22_ A[22]
|
||||
Inst A_23_ A[23]
|
||||
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.r
|
||||
Inst A_24_ A[24]
|
||||
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.m
|
||||
Inst A_25_ A[25]
|
||||
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.n
|
||||
Inst A_26_ A[26]
|
||||
Inst un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.p
|
||||
Inst A_27_ A[27]
|
||||
Inst A_28_ A[28]
|
||||
Inst un1_SM_AMIGA_7_i_m2_r un1_SM_AMIGA_7_i_m2.r
|
||||
Inst A_29_ A[29]
|
||||
Inst un1_SM_AMIGA_7_i_m2_m un1_SM_AMIGA_7_i_m2.m
|
||||
Inst A_30_ A[30]
|
||||
Inst un1_SM_AMIGA_7_i_m2_n un1_SM_AMIGA_7_i_m2.n
|
||||
Inst A_31_ A[31]
|
||||
Inst un1_SM_AMIGA_7_i_m2_p un1_SM_AMIGA_7_i_m2.p
|
||||
Inst SM_AMIGA_srsts_i_o3_0_o2_i_3_ SM_AMIGA_srsts_i_o3_0_o2_i[3]
|
||||
Inst SM_AMIGA_srsts_i_0_o4_i_0_ SM_AMIGA_srsts_i_0_o4_i[0]
|
||||
Inst A_i_25_ A_i[25]
|
||||
Inst SM_AMIGA_srsts_i_0_o2_i_4_ SM_AMIGA_srsts_i_0_o2_i[4]
|
||||
Inst A_i_26_ A_i[26]
|
||||
Inst SM_AMIGA_srsts_i_i_o2_i_2_ SM_AMIGA_srsts_i_i_o2_i[2]
|
||||
Inst A_i_27_ A_i[27]
|
||||
Inst pos_clk_cpu_est_11_0_0_o2_i_3_ pos_clk.cpu_est_11_0_0_o2_i[3]
|
||||
Inst A_i_28_ A_i[28]
|
||||
Inst pos_clk_cpu_est_11_0_0_o2_i_1_ pos_clk.cpu_est_11_0_0_o2_i[1]
|
||||
Inst A_i_29_ A_i[29]
|
||||
Inst pos_clk_cpu_est_11_i_0_o2_i_2_ pos_clk.cpu_est_11_i_0_o2_i[2]
|
||||
Inst A_i_30_ A_i[30]
|
||||
Inst SM_AMIGA_srsts_i_o3_0_i_o2_i_0_ SM_AMIGA_srsts_i_o3_0_i_o2_i[0]
|
||||
Inst A_i_31_ A_i[31]
|
||||
Inst A_i_18_ A_i[18]
|
||||
Inst A_i_19_ A_i[19]
|
||||
Inst SM_AMIGA_srsts_i_i_o2_0_i_2_ SM_AMIGA_srsts_i_i_o2_0_i[2]
|
||||
Inst IPL_030_0_ IPL_030[0]
|
||||
Inst IPL_030_1_ IPL_030[1]
|
||||
Inst IPL_030_2_ IPL_030[2]
|
||||
Inst un1_RST_DLY_i_m_i_6_ un1_RST_DLY_i_m_i[6]
|
||||
Inst IPL_0_ IPL[0]
|
||||
Inst un1_RST_DLY_i_m_i_7_ un1_RST_DLY_i_m_i[7]
|
||||
Inst IPL_1_ IPL[1]
|
||||
Inst un1_RST_DLY_i_m_i_8_ un1_RST_DLY_i_m_i[8]
|
||||
Inst IPL_2_ IPL[2]
|
||||
Inst un1_RST_DLY_i_m_i_2_ un1_RST_DLY_i_m_i[2]
|
||||
Inst IPL_D0_0_0_ IPL_D0_0[0]
|
||||
Inst IPL_D0_0_1_ IPL_D0_0[1]
|
||||
Inst IPL_D0_0_2_ IPL_D0_0[2]
|
||||
Inst IPL_030_1_0_ IPL_030_1[0]
|
||||
Inst FC_0_ FC[0]
|
||||
Inst IPL_030_1_1_ IPL_030_1[1]
|
||||
Inst FC_1_ FC[1]
|
||||
Inst pos_clk_cpu_est_11_0_0_i_1_ pos_clk.cpu_est_11_0_0_i[1]
|
||||
Inst IPL_030_1_2_ IPL_030_1[2]
|
||||
Inst un1_RST_DLY_i_m_i_3_ un1_RST_DLY_i_m_i[3]
|
||||
Inst SIZE_DMA_0_0__r SIZE_DMA_0_0_.r
|
||||
Inst un1_RST_DLY_i_m_i_4_ un1_RST_DLY_i_m_i[4]
|
||||
Inst SIZE_DMA_0_0__m SIZE_DMA_0_0_.m
|
||||
Inst un1_RST_DLY_i_m_i_5_ un1_RST_DLY_i_m_i[5]
|
||||
Inst SIZE_DMA_0_0__n SIZE_DMA_0_0_.n
|
||||
Inst SIZE_DMA_0_0__p SIZE_DMA_0_0_.p
|
||||
Inst un1_RST_DLY_i_3_ un1_RST_DLY_i[3]
|
||||
Inst SIZE_DMA_0_1__r SIZE_DMA_0_1_.r
|
||||
Inst pos_clk_cpu_est_11_0_0_3_ pos_clk.cpu_est_11_0_0[3]
|
||||
Inst un1_RST_DLY_i_m_3_ un1_RST_DLY_i_m[3]
|
||||
Inst SIZE_DMA_0_1__m SIZE_DMA_0_1_.m
|
||||
Inst SIZE_DMA_0_1__n SIZE_DMA_0_1_.n
|
||||
Inst SIZE_DMA_0_1__p SIZE_DMA_0_1_.p
|
||||
Inst IPL_030_0_0__r IPL_030_0_0_.r
|
||||
Inst IPL_030_0_0__m IPL_030_0_0_.m
|
||||
Inst pos_clk_CYCLE_DMA_5_1_i_1 pos_clk.CYCLE_DMA_5_1_i_1
|
||||
Inst IPL_030_0_0__n IPL_030_0_0_.n
|
||||
Inst pos_clk_CYCLE_DMA_5_1_i pos_clk.CYCLE_DMA_5_1_i
|
||||
Inst IPL_030_0_0__p IPL_030_0_0_.p
|
||||
Inst pos_clk_CYCLE_DMA_5_0_i_1 pos_clk.CYCLE_DMA_5_0_i_1
|
||||
Inst IPL_030_0_1__r IPL_030_0_1_.r
|
||||
Inst pos_clk_CYCLE_DMA_5_0_i pos_clk.CYCLE_DMA_5_0_i
|
||||
Inst IPL_030_0_1__m IPL_030_0_1_.m
|
||||
Inst IPL_030_0_1__n IPL_030_0_1_.n
|
||||
Inst IPL_030_0_1__p IPL_030_0_1_.p
|
||||
Inst pos_clk_cpu_est_11_i_0_a2_1_2_ pos_clk.cpu_est_11_i_0_a2_1[2]
|
||||
Inst IPL_030_0_2__r IPL_030_0_2_.r
|
||||
Inst pos_clk_cpu_est_11_i_0_a2_2_ pos_clk.cpu_est_11_i_0_a2[2]
|
||||
Inst pos_clk_RST_DLY_5_iv_6_ pos_clk.RST_DLY_5_iv[6]
|
||||
Inst IPL_030_0_2__m IPL_030_0_2_.m
|
||||
Inst pos_clk_cpu_est_11_i_0_a2_0_1_2_ pos_clk.cpu_est_11_i_0_a2_0_1[2]
|
||||
Inst un1_RST_DLY_i_7_ un1_RST_DLY_i[7]
|
||||
Inst IPL_030_0_2__n IPL_030_0_2_.n
|
||||
Inst pos_clk_cpu_est_11_i_0_a2_0_2_ pos_clk.cpu_est_11_i_0_a2_0[2]
|
||||
Inst un1_RST_DLY_i_m_7_ un1_RST_DLY_i_m[7]
|
||||
Inst IPL_030_0_2__p IPL_030_0_2_.p
|
||||
Inst pos_clk_RST_DLY_5_iv_5_ pos_clk.RST_DLY_5_iv[5]
|
||||
Inst un1_RST_DLY_i_6_ un1_RST_DLY_i[6]
|
||||
Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_r AMIGA_BUS_ENABLE_DMA_HIGH_0.r
|
||||
Inst SM_AMIGA_srsts_i_0_1_6_ SM_AMIGA_srsts_i_0_1[6]
|
||||
Inst un1_RST_DLY_i_m_6_ un1_RST_DLY_i_m[6]
|
||||
Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_m AMIGA_BUS_ENABLE_DMA_HIGH_0.m
|
||||
Inst SM_AMIGA_srsts_i_0_6_ SM_AMIGA_srsts_i_0[6]
|
||||
Inst pos_clk_RST_DLY_5_iv_4_ pos_clk.RST_DLY_5_iv[4]
|
||||
Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.n
|
||||
Inst SM_AMIGA_srsts_i_0_1_4_ SM_AMIGA_srsts_i_0_1[4]
|
||||
Inst un1_RST_DLY_i_5_ un1_RST_DLY_i[5]
|
||||
Inst AMIGA_BUS_ENABLE_DMA_HIGH_0_p AMIGA_BUS_ENABLE_DMA_HIGH_0.p
|
||||
Inst SM_AMIGA_srsts_i_0_4_ SM_AMIGA_srsts_i_0[4]
|
||||
Inst un1_RST_DLY_i_m_5_ un1_RST_DLY_i_m[5]
|
||||
Inst BG_000_0_r BG_000_0.r
|
||||
Inst SM_AMIGA_srsts_i_0_1_3_ SM_AMIGA_srsts_i_0_1[3]
|
||||
Inst pos_clk_RST_DLY_5_iv_3_ pos_clk.RST_DLY_5_iv[3]
|
||||
Inst BG_000_0_m BG_000_0.m
|
||||
Inst SM_AMIGA_srsts_i_0_3_ SM_AMIGA_srsts_i_0[3]
|
||||
Inst un1_RST_DLY_i_4_ un1_RST_DLY_i[4]
|
||||
Inst BG_000_0_n BG_000_0.n
|
||||
Inst un1_RST_DLY_i_m_4_ un1_RST_DLY_i_m[4]
|
||||
Inst BG_000_0_p BG_000_0.p
|
||||
Inst pos_clk_RST_DLY_5_iv_2_ pos_clk.RST_DLY_5_iv[2]
|
||||
Inst pos_clk_cpu_est_11_0_0_1_3_ pos_clk.cpu_est_11_0_0_1[3]
|
||||
Inst pos_clk_RST_DLY_5_iv_0_a2_0_ pos_clk.RST_DLY_5_iv_0_a2[0]
|
||||
Inst un1_RST_DLY_i_2_ un1_RST_DLY_i[2]
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_1_0_0_ SM_AMIGA_nss_i_i_0_a2_1_0[0]
|
||||
Inst un1_RST_DLY_i_m_2_ un1_RST_DLY_i_m[2]
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_0_ SM_AMIGA_nss_i_i_0_a2[0]
|
||||
Inst pos_clk_RST_DLY_5_iv_1_ pos_clk.RST_DLY_5_iv[1]
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_0_1_0_ SM_AMIGA_nss_i_i_0_a2_0_1[0]
|
||||
Inst un1_RST_DLY_i_8_ un1_RST_DLY_i[8]
|
||||
Inst SM_AMIGA_nss_i_i_0_a2_0_0_ SM_AMIGA_nss_i_i_0_a2_0[0]
|
||||
Inst un1_RST_DLY_i_m_8_ un1_RST_DLY_i_m[8]
|
||||
Inst SM_AMIGA_srsts_i_0_1_1_ SM_AMIGA_srsts_i_0_1[1]
|
||||
Inst pos_clk_RST_DLY_5_iv_7_ pos_clk.RST_DLY_5_iv[7]
|
||||
Inst SM_AMIGA_srsts_i_0_1_ SM_AMIGA_srsts_i_0[1]
|
||||
Inst SM_AMIGA_srsts_i_i_a2_1_0_2_ SM_AMIGA_srsts_i_i_a2_1_0[2]
|
||||
Inst SM_AMIGA_srsts_i_i_a2_2_ SM_AMIGA_srsts_i_i_a2[2]
|
||||
Inst SM_AMIGA_srsts_i_i_a2_0_1_2_ SM_AMIGA_srsts_i_i_a2_0_1[2]
|
||||
Inst DS_000_DMA_0_r DS_000_DMA_0.r
|
||||
Inst SM_AMIGA_srsts_i_i_a2_0_2_ SM_AMIGA_srsts_i_i_a2_0[2]
|
||||
Inst DS_000_DMA_0_m DS_000_DMA_0.m
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_1_1_3_ pos_clk.cpu_est_11_0_0_a2_1_1[3]
|
||||
Inst DS_000_DMA_0_n DS_000_DMA_0.n
|
||||
Inst pos_clk_cpu_est_11_0_0_a2_1_3_ pos_clk.cpu_est_11_0_0_a2_1[3]
|
||||
Inst cpu_est_0_3__r cpu_est_0_3_.r
|
||||
Inst DS_000_DMA_0_p DS_000_DMA_0.p
|
||||
Inst pos_clk_cpu_est_11_0_0_1_ pos_clk.cpu_est_11_0_0[1]
|
||||
Inst cpu_est_0_3__m cpu_est_0_3_.m
|
||||
Inst AS_000_DMA_0_r AS_000_DMA_0.r
|
||||
Inst SM_AMIGA_srsts_i_i_a2_2_1_2_ SM_AMIGA_srsts_i_i_a2_2_1[2]
|
||||
Inst cpu_est_0_3__n cpu_est_0_3_.n
|
||||
Inst AS_000_DMA_0_m AS_000_DMA_0.m
|
||||
Inst SM_AMIGA_srsts_i_i_a2_2_2_2_ SM_AMIGA_srsts_i_i_a2_2_2[2]
|
||||
Inst cpu_est_0_3__p cpu_est_0_3_.p
|
||||
Inst AS_000_DMA_0_n AS_000_DMA_0.n
|
||||
Inst SM_AMIGA_srsts_i_i_a2_2_3_2_ SM_AMIGA_srsts_i_i_a2_2_3[2]
|
||||
Inst cpu_est_0_2__r cpu_est_0_2_.r
|
||||
Inst AS_000_DMA_0_p AS_000_DMA_0.p
|
||||
Inst SM_AMIGA_srsts_i_i_a2_2_4_2_ SM_AMIGA_srsts_i_i_a2_2_4[2]
|
||||
Inst cpu_est_0_2__m cpu_est_0_2_.m
|
||||
Inst A0_DMA_0_r A0_DMA_0.r
|
||||
Inst SM_AMIGA_srsts_i_i_a2_2_2_ SM_AMIGA_srsts_i_i_a2_2[2]
|
||||
Inst cpu_est_0_2__n cpu_est_0_2_.n
|
||||
Inst A0_DMA_0_m A0_DMA_0.m
|
||||
Inst pos_clk_un7_clk_000_pe_0_a2_0_1 pos_clk.un7_clk_000_pe_0_a2_0_1
|
||||
Inst cpu_est_0_2__p cpu_est_0_2_.p
|
||||
Inst A0_DMA_0_n A0_DMA_0.n
|
||||
Inst pos_clk_un7_clk_000_pe_0_a2_0_2 pos_clk.un7_clk_000_pe_0_a2_0_2
|
||||
Inst cpu_est_0_1__r cpu_est_0_1_.r
|
||||
Inst A0_DMA_0_p A0_DMA_0.p
|
||||
Inst pos_clk_un7_clk_000_pe_0_a2_0 pos_clk.un7_clk_000_pe_0_a2_0
|
||||
Inst cpu_est_0_1__m cpu_est_0_1_.m
|
||||
Inst pos_clk_un7_clk_000_pe_0_a2_1 pos_clk.un7_clk_000_pe_0_a2_1
|
||||
Inst cpu_est_0_1__n cpu_est_0_1_.n
|
||||
Inst DSACK1_INT_0_r DSACK1_INT_0.r
|
||||
Inst pos_clk_un7_clk_000_pe_0_a2_2 pos_clk.un7_clk_000_pe_0_a2_2
|
||||
Inst cpu_est_0_1__p cpu_est_0_1_.p
|
||||
Inst DSACK1_INT_0_m DSACK1_INT_0.m
|
||||
Net un1_rst_dly_i_m_i_5__n un1_RST_DLY_i_m_i[5]
|
||||
Net sm_amiga_srsts_i_0_m2_3__un0_n SM_AMIGA_srsts_i_0_m2_3_.un0
|
||||
Net pos_clk_rst_dly_5_iv_i_4__n pos_clk.RST_DLY_5_iv_i[4]
|
||||
Net sm_amiga_srsts_i_0_m2_1__un3_n SM_AMIGA_srsts_i_0_m2_1_.un3
|
||||
Net pos_clk_cpu_est_11_1__n pos_clk.cpu_est_11[1]
|
||||
Net un1_rst_dly_i_m_i_6__n un1_RST_DLY_i_m_i[6]
|
||||
Net sm_amiga_srsts_i_0_m2_1__un1_n SM_AMIGA_srsts_i_0_m2_1_.un1
|
||||
Net pos_clk_rst_dly_5_iv_i_5__n pos_clk.RST_DLY_5_iv_i[5]
|
||||
Net sm_amiga_srsts_i_0_m2_1__un0_n SM_AMIGA_srsts_i_0_m2_1_.un0
|
||||
Net un1_rst_dly_i_m_i_7__n un1_RST_DLY_i_m_i[7]
|
||||
Net un1_amiga_bus_enable_dma_high_0_m2_0__un3_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un3
|
||||
Net pos_clk_rst_dly_5_iv_i_6__n pos_clk.RST_DLY_5_iv_i[6]
|
||||
Net un1_amiga_bus_enable_dma_high_0_m2_0__un1_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un1
|
||||
Net un1_rst_dly_i_m_i_8__n un1_RST_DLY_i_m_i[8]
|
||||
Net un1_amiga_bus_enable_dma_high_0_m2_0__un0_n un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un0
|
||||
Net vcc_n_n VCC
|
||||
Net pos_clk_rst_dly_5_iv_i_7__n pos_clk.RST_DLY_5_iv_i[7]
|
||||
Net un1_sm_amiga_7_i_m2_un3_n un1_SM_AMIGA_7_i_m2.un3
|
||||
Net cpu_est_3__n cpu_est[3]
|
||||
Net un1_rst_dly_i_m_i_2__n un1_RST_DLY_i_m_i[2]
|
||||
Net un1_sm_amiga_7_i_m2_un1_n un1_SM_AMIGA_7_i_m2.un1
|
||||
Net pos_clk_rst_dly_5_iv_i_1__n pos_clk.RST_DLY_5_iv_i[1]
|
||||
Net un1_sm_amiga_7_i_m2_un0_n un1_SM_AMIGA_7_i_m2.un0
|
||||
Net size_dma_0_0__un3_n SIZE_DMA_0_0_.un3
|
||||
Net gnd_n_n GND
|
||||
Net pos_clk_rst_dly_5_iv_i_0__n pos_clk.RST_DLY_5_iv_i[0]
|
||||
Net size_dma_0_0__un1_n SIZE_DMA_0_0_.un1
|
||||
Net size_dma_0_0__un0_n SIZE_DMA_0_0_.un0
|
||||
Net un1_rst_dly_i_m_2__n un1_RST_DLY_i_m[2]
|
||||
Net size_dma_0_1__un3_n SIZE_DMA_0_1_.un3
|
||||
Net un1_rst_dly_2__n un1_RST_DLY[2]
|
||||
Net size_dma_0_1__un1_n SIZE_DMA_0_1_.un1
|
||||
Net un1_rst_dly_i_m_8__n un1_RST_DLY_i_m[8]
|
||||
Net size_dma_0_1__un0_n SIZE_DMA_0_1_.un0
|
||||
Net un1_rst_dly_8__n un1_RST_DLY[8]
|
||||
Net ipl_030_0_0__un3_n IPL_030_0_0_.un3
|
||||
Net ipl_030_0_0__un1_n IPL_030_0_0_.un1
|
||||
Net ipl_030_0_0__un0_n IPL_030_0_0_.un0
|
||||
Net un1_rst_dly_7__n un1_RST_DLY[7]
|
||||
Net ipl_030_0_1__un3_n IPL_030_0_1_.un3
|
||||
Net un1_rst_dly_6__n un1_RST_DLY[6]
|
||||
Net ipl_030_0_1__un1_n IPL_030_0_1_.un1
|
||||
Net ipl_030_0_1__un0_n IPL_030_0_1_.un0
|
||||
Net un1_rst_dly_5__n un1_RST_DLY[5]
|
||||
Net pos_clk_cpu_est_11_0_1__n pos_clk.cpu_est_11_0[1]
|
||||
Net ipl_030_0_2__un3_n IPL_030_0_2_.un3
|
||||
Net cpu_est_0__n cpu_est[0]
|
||||
Net ipl_030_0_2__un1_n IPL_030_0_2_.un1
|
||||
Net cpu_est_1__n cpu_est[1]
|
||||
Net un1_rst_dly_4__n un1_RST_DLY[4]
|
||||
Net ipl_030_0_2__un0_n IPL_030_0_2_.un0
|
||||
Net un1_rst_dly_3__n un1_RST_DLY[3]
|
||||
Net amiga_bus_enable_dma_high_0_un3_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un3
|
||||
Net sm_amiga_5__n SM_AMIGA[5]
|
||||
Net un1_rst_dly_i_m_7__n un1_RST_DLY_i_m[7]
|
||||
Net amiga_bus_enable_dma_high_0_un1_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un1
|
||||
Net un1_rst_dly_i_m_6__n un1_RST_DLY_i_m[6]
|
||||
Net amiga_bus_enable_dma_high_0_un0_n AMIGA_BUS_ENABLE_DMA_HIGH_0.un0
|
||||
Net un1_rst_dly_i_m_5__n un1_RST_DLY_i_m[5]
|
||||
Net bg_000_0_un3_n BG_000_0.un3
|
||||
Net un1_rst_dly_i_m_4__n un1_RST_DLY_i_m[4]
|
||||
Net bg_000_0_un1_n BG_000_0.un1
|
||||
Net un1_rst_dly_i_m_3__n un1_RST_DLY_i_m[3]
|
||||
Net bg_000_0_un0_n BG_000_0.un0
|
||||
Net ds_000_dma_0_un3_n DS_000_DMA_0.un3
|
||||
Net ds_000_dma_0_un1_n DS_000_DMA_0.un1
|
||||
Net ds_000_dma_0_un0_n DS_000_DMA_0.un0
|
||||
Net as_000_dma_0_un3_n AS_000_DMA_0.un3
|
||||
Net cycle_dma_0__n CYCLE_DMA[0]
|
||||
Net as_000_dma_0_un1_n AS_000_DMA_0.un1
|
||||
Net cycle_dma_1__n CYCLE_DMA[1]
|
||||
Net as_000_dma_0_un0_n AS_000_DMA_0.un0
|
||||
Net size_dma_0__n SIZE_DMA[0]
|
||||
Net un1_rst_dly_i_3__n un1_RST_DLY_i[3]
|
||||
Net a0_dma_0_un3_n A0_DMA_0.un3
|
||||
Net size_dma_1__n SIZE_DMA[1]
|
||||
Net un1_rst_dly_i_4__n un1_RST_DLY_i[4]
|
||||
Net pos_clk_un7_clk_000_pe_0_n pos_clk.un7_clk_000_pe_0
|
||||
Net a0_dma_0_un1_n A0_DMA_0.un1
|
||||
Net un1_rst_dly_i_5__n un1_RST_DLY_i[5]
|
||||
Net a0_dma_0_un0_n A0_DMA_0.un0
|
||||
Net un1_rst_dly_i_6__n un1_RST_DLY_i[6]
|
||||
Net dsack1_int_0_un3_n DSACK1_INT_0.un3
|
||||
Net un1_rst_dly_i_7__n un1_RST_DLY_i[7]
|
||||
Net dsack1_int_0_un1_n DSACK1_INT_0.un1
|
||||
Net un1_rst_dly_i_8__n un1_RST_DLY_i[8]
|
||||
Net dsack1_int_0_un0_n DSACK1_INT_0.un0
|
||||
Net un1_rst_dly_i_2__n un1_RST_DLY_i[2]
|
||||
Net as_000_int_0_un3_n AS_000_INT_0.un3
|
||||
Net as_000_int_0_un1_n AS_000_INT_0.un1
|
||||
Net cpu_est_i_3__n cpu_est_i[3]
|
||||
Net as_000_int_0_un0_n AS_000_INT_0.un0
|
||||
Net cpu_est_i_0__n cpu_est_i[0]
|
||||
Net ds_000_enable_0_un3_n DS_000_ENABLE_0.un3
|
||||
Net ds_000_enable_0_un1_n DS_000_ENABLE_0.un1
|
||||
Net clk_000_p_sync_9__n CLK_000_P_SYNC[9]
|
||||
Net ds_000_enable_0_un0_n DS_000_ENABLE_0.un0
|
||||
Net cpu_est_i_1__n cpu_est_i[1]
|
||||
Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3
|
||||
Net clk_000_n_sync_11__n CLK_000_N_SYNC[11]
|
||||
Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1
|
||||
Net cpu_est_2__n cpu_est[2]
|
||||
Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0
|
||||
Net ipl_d0_0__n IPL_D0[0]
|
||||
Net sm_amiga_i_4__n SM_AMIGA_i[4]
|
||||
Net lds_000_int_0_un3_n LDS_000_INT_0.un3
|
||||
Net ipl_d0_1__n IPL_D0[1]
|
||||
Net cpu_est_i_2__n cpu_est_i[2]
|
||||
Net lds_000_int_0_un1_n LDS_000_INT_0.un1
|
||||
Net ipl_d0_2__n IPL_D0[2]
|
||||
Net sm_amiga_i_5__n SM_AMIGA_i[5]
|
||||
Net lds_000_int_0_un0_n LDS_000_INT_0.un0
|
||||
Net sm_amiga_3__n SM_AMIGA[3]
|
||||
Net rw_000_dma_0_un3_n RW_000_DMA_0.un3
|
||||
Net sm_amiga_i_0__n SM_AMIGA_i[0]
|
||||
Net rw_000_dma_0_un1_n RW_000_DMA_0.un1
|
||||
Net pos_clk_un6_bg_030_n pos_clk.un6_bg_030
|
||||
Net sm_amiga_i_3__n SM_AMIGA_i[3]
|
||||
Net rw_000_dma_0_un0_n RW_000_DMA_0.un0
|
||||
Net sm_amiga_0__n SM_AMIGA[0]
|
||||
Net uds_000_int_0_un3_n UDS_000_INT_0.un3
|
||||
Net sm_amiga_i_6__n SM_AMIGA_i[6]
|
||||
Net uds_000_int_0_un1_n UDS_000_INT_0.un1
|
||||
Net sm_amiga_i_1__n SM_AMIGA_i[1]
|
||||
Net clk_000_n_sync_i_10__n CLK_000_N_SYNC_i[10]
|
||||
Net uds_000_int_0_un0_n UDS_000_INT_0.un0
|
||||
Net pos_clk_clk_000_p_sync_2_0__n pos_clk.CLK_000_P_SYNC_2[0]
|
||||
Net pos_clk_un9_clk_000_n_sync_i_n pos_clk.un9_clk_000_n_sync_i
|
||||
Net amiga_bus_enable_dma_low_0_un3_n AMIGA_BUS_ENABLE_DMA_LOW_0.un3
|
||||
Net pos_clk_ipl_n pos_clk.ipl
|
||||
Net pos_clk_un11_clk_000_n_sync_i_n pos_clk.un11_clk_000_n_sync_i
|
||||
Net pos_clk_un14_clk_000_n_sync_0_n pos_clk.un14_clk_000_n_sync_0
|
||||
Net amiga_bus_enable_dma_low_0_un1_n AMIGA_BUS_ENABLE_DMA_LOW_0.un1
|
||||
Net pos_clk_un3_ds_030_d0_n pos_clk.un3_ds_030_d0
|
||||
Net pos_clk_un22_bgack_030_int_i_n pos_clk.un22_bgack_030_int_i
|
||||
Net amiga_bus_enable_dma_low_0_un0_n AMIGA_BUS_ENABLE_DMA_LOW_0.un0
|
||||
Net sm_amiga_6__n SM_AMIGA[6]
|
||||
Net a_15__n A[15]
|
||||
Net rst_dly_0__n RST_DLY[0]
|
||||
Net sm_amiga_i_2__n SM_AMIGA_i[2]
|
||||
Net a_14__n A[14]
|
||||
Net rst_dly_1__n RST_DLY[1]
|
||||
Net rst_dly_2__n RST_DLY[2]
|
||||
Net pos_clk_size_dma_6_0_1__n pos_clk.SIZE_DMA_6_0[1]
|
||||
Net a_13__n A[13]
|
||||
Net rst_dly_3__n RST_DLY[3]
|
||||
Net rst_dly_4__n RST_DLY[4]
|
||||
Net pos_clk_size_dma_6_0_0__n pos_clk.SIZE_DMA_6_0[0]
|
||||
Net a_12__n A[12]
|
||||
Net rst_dly_5__n RST_DLY[5]
|
||||
Net rst_dly_6__n RST_DLY[6]
|
||||
Net a_11__n A[11]
|
||||
Net rst_dly_7__n RST_DLY[7]
|
||||
Net pos_clk_un8_bg_030_n pos_clk.un8_bg_030
|
||||
Net sm_amiga_i_i_7__n SM_AMIGA_i_i[7]
|
||||
Net a_10__n A[10]
|
||||
Net clk_000_p_sync_0__n CLK_000_P_SYNC[0]
|
||||
Net clk_000_p_sync_1__n CLK_000_P_SYNC[1]
|
||||
Net a_9__n A[9]
|
||||
Net clk_000_p_sync_2__n CLK_000_P_SYNC[2]
|
||||
Net clk_000_p_sync_3__n CLK_000_P_SYNC[3]
|
||||
Net a_8__n A[8]
|
||||
Net clk_000_p_sync_4__n CLK_000_P_SYNC[4]
|
||||
Net a_i_24__n A_i[24]
|
||||
Net clk_000_p_sync_5__n CLK_000_P_SYNC[5]
|
||||
Net size_dma_i_0__n SIZE_DMA_i[0]
|
||||
Net a_7__n A[7]
|
||||
Net clk_000_p_sync_6__n CLK_000_P_SYNC[6]
|
||||
Net size_dma_i_1__n SIZE_DMA_i[1]
|
||||
Net clk_000_p_sync_7__n CLK_000_P_SYNC[7]
|
||||
Net a_i_16__n A_i[16]
|
||||
Net pos_clk_un3_as_030_d0_i_n pos_clk.un3_as_030_d0_i
|
||||
Net a_6__n A[6]
|
||||
Net clk_000_p_sync_8__n CLK_000_P_SYNC[8]
|
||||
Net a_i_18__n A_i[18]
|
||||
Net pos_clk_un5_bgack_030_int_d_i_n pos_clk.un5_bgack_030_int_d_i
|
||||
Net clk_000_n_sync_0__n CLK_000_N_SYNC[0]
|
||||
Net a_i_19__n A_i[19]
|
||||
Net a_5__n A[5]
|
||||
Net clk_000_n_sync_1__n CLK_000_N_SYNC[1]
|
||||
Net a_i_31__n A_i[31]
|
||||
Net clk_000_n_sync_2__n CLK_000_N_SYNC[2]
|
||||
Net a_i_29__n A_i[29]
|
||||
Net a_4__n A[4]
|
||||
Net clk_000_n_sync_3__n CLK_000_N_SYNC[3]
|
||||
Net a_i_30__n A_i[30]
|
||||
Net clk_000_n_sync_4__n CLK_000_N_SYNC[4]
|
||||
Net a_i_27__n A_i[27]
|
||||
Net a_3__n A[3]
|
||||
Net clk_000_n_sync_5__n CLK_000_N_SYNC[5]
|
||||
Net a_i_28__n A_i[28]
|
||||
Net clk_000_n_sync_6__n CLK_000_N_SYNC[6]
|
||||
Net a_i_25__n A_i[25]
|
||||
Net a_2__n A[2]
|
||||
Net clk_000_n_sync_7__n CLK_000_N_SYNC[7]
|
||||
Net a_i_26__n A_i[26]
|
||||
Net clk_000_n_sync_8__n CLK_000_N_SYNC[8]
|
||||
Net clk_000_n_sync_9__n CLK_000_N_SYNC[9]
|
||||
Net clk_000_n_sync_10__n CLK_000_N_SYNC[10]
|
||||
Net pos_clk_un5_bgack_030_int_d_n pos_clk.un5_bgack_030_int_d
|
||||
Net sm_amiga_1__n SM_AMIGA[1]
|
||||
Net sm_amiga_4__n SM_AMIGA[4]
|
||||
Net sm_amiga_2__n SM_AMIGA[2]
|
||||
Net pos_clk_un3_as_030_d0_n pos_clk.un3_as_030_d0
|
||||
Net pos_clk_a0_dma_3_n pos_clk.A0_DMA_3
|
||||
Net pos_clk_cpu_est_11_0_3__n pos_clk.cpu_est_11_0[3]
|
||||
Net pos_clk_ds_000_dma_4_n pos_clk.DS_000_DMA_4
|
||||
Net pos_clk_ds_000_dma_4_0_n pos_clk.DS_000_DMA_4_0
|
||||
Net pos_clk_un24_bgack_030_int_i_0_i_n pos_clk.un24_bgack_030_int_i_0_i
|
||||
Net size_c_0__n SIZE_c[0]
|
||||
Net size_0__n SIZE[0]
|
||||
Net size_c_1__n SIZE_c[1]
|
||||
Net pos_clk_un11_ds_030_d0_i_n pos_clk.un11_ds_030_d0_i
|
||||
Net size_c_i_1__n SIZE_c_i[1]
|
||||
Net ipl_c_i_2__n IPL_c_i[2]
|
||||
Net ipl_c_i_1__n IPL_c_i[1]
|
||||
Net ipl_c_i_0__n IPL_c_i[0]
|
||||
Net sm_amiga_i_7__n SM_AMIGA_i[7]
|
||||
Net pos_clk_size_dma_6_0__n pos_clk.SIZE_DMA_6[0]
|
||||
Net a_c_16__n A_c[16]
|
||||
Net pos_clk_size_dma_6_1__n pos_clk.SIZE_DMA_6[1]
|
||||
Net a_16__n A[16]
|
||||
Net pos_clk_cpu_est_11_3__n pos_clk.cpu_est_11[3]
|
||||
Net a_c_17__n A_c[17]
|
||||
Net a_17__n A[17]
|
||||
Net a_c_18__n A_c[18]
|
||||
Net a_18__n A[18]
|
||||
Net a_c_19__n A_c[19]
|
||||
Net pos_clk_un24_bgack_030_int_i_0_n pos_clk.un24_bgack_030_int_i_0
|
||||
Net a_19__n A[19]
|
||||
Net a_c_20__n A_c[20]
|
||||
Net a_20__n A[20]
|
||||
Net a_c_21__n A_c[21]
|
||||
Net a_21__n A[21]
|
||||
Net a_c_22__n A_c[22]
|
||||
Net pos_clk_un6_bg_030_i_n pos_clk.un6_bg_030_i
|
||||
Net a_22__n A[22]
|
||||
Net pos_clk_un8_bg_030_0_n pos_clk.un8_bg_030_0
|
||||
Net a_c_23__n A_c[23]
|
||||
Net a_23__n A[23]
|
||||
Net a_c_24__n A_c[24]
|
||||
Net pos_clk_un24_bgack_030_int_i_0_i_1_n pos_clk.un24_bgack_030_int_i_0_i_1
|
||||
Net a_24__n A[24]
|
||||
Net a_c_25__n A_c[25]
|
||||
Net a_25__n A[25]
|
||||
Net a_c_26__n A_c[26]
|
||||
Net pos_clk_un11_ds_030_d0_i_1_n pos_clk.un11_ds_030_d0_i_1
|
||||
Net a_26__n A[26]
|
||||
Net a_c_27__n A_c[27]
|
||||
Net a_27__n A[27]
|
||||
Net a_c_28__n A_c[28]
|
||||
Net a_28__n A[28]
|
||||
Net pos_clk_un11_clk_000_n_sync_n pos_clk.un11_clk_000_n_sync
|
||||
Net a_c_29__n A_c[29]
|
||||
Net a_29__n A[29]
|
||||
Net a_c_30__n A_c[30]
|
||||
Net a_30__n A[30]
|
||||
Net a_c_31__n A_c[31]
|
||||
Net pos_clk_un22_bgack_030_int_n pos_clk.un22_bgack_030_int
|
||||
Net pos_clk_un6_bg_030_1_n pos_clk.un6_bg_030_1
|
||||
Net pos_clk_cpu_est_11_0_1_1__n pos_clk.cpu_est_11_0_1[1]
|
||||
Net pos_clk_cpu_est_11_0_2_1__n pos_clk.cpu_est_11_0_2[1]
|
||||
Net ipl_030_c_0__n IPL_030_c[0]
|
||||
Net ipl_030_0__n IPL_030[0]
|
||||
Net ipl_030_c_1__n IPL_030_c[1]
|
||||
Net ipl_030_1__n IPL_030[1]
|
||||
Net ipl_030_c_2__n IPL_030_c[2]
|
||||
Net ipl_c_0__n IPL_c[0]
|
||||
Net ipl_0__n IPL[0]
|
||||
Net ipl_c_1__n IPL_c[1]
|
||||
Net ipl_1__n IPL[1]
|
||||
Net ipl_c_2__n IPL_c[2]
|
||||
Net pos_clk_cpu_est_11_0_1_3__n pos_clk.cpu_est_11_0_1[3]
|
||||
Net pos_clk_un14_clk_000_n_sync_n pos_clk.un14_clk_000_n_sync
|
||||
Net pos_clk_un9_clk_000_n_sync_n pos_clk.un9_clk_000_n_sync
|
||||
Net pos_clk_ipl_1_n pos_clk.ipl_1
|
||||
Net cpu_est_0_3__un3_n cpu_est_0_3_.un3
|
||||
Net cpu_est_0_3__un1_n cpu_est_0_3_.un1
|
||||
Net cpu_est_0_3__un0_n cpu_est_0_3_.un0
|
||||
Net cpu_est_0_2__un3_n cpu_est_0_2_.un3
|
||||
Net cpu_est_0_2__un1_n cpu_est_0_2_.un1
|
||||
Net fc_c_0__n FC_c[0]
|
||||
Net cpu_est_0_2__un0_n cpu_est_0_2_.un0
|
||||
Net fc_0__n FC[0]
|
||||
Net cpu_est_0_1__un3_n cpu_est_0_1_.un3
|
||||
Net fc_c_1__n FC_c[1]
|
||||
Net cpu_est_0_1__un1_n cpu_est_0_1_.un1
|
||||
Net cpu_est_0_1__un0_n cpu_est_0_1_.un0
|
||||
Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3
|
||||
Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1
|
||||
Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0
|
||||
Net vma_int_0_un3_n VMA_INT_0.un3
|
||||
Net vma_int_0_un1_n VMA_INT_0.un1
|
||||
Net vma_int_0_un0_n VMA_INT_0.un0
|
||||
Net rw_000_int_0_un3_n RW_000_INT_0.un3
|
||||
Net un1_rst_dly_i_m_i_3__n un1_RST_DLY_i_m_i[3]
|
||||
Net rw_000_int_0_un1_n RW_000_INT_0.un1
|
||||
Net pos_clk_un7_clk_000_pe_n pos_clk.un7_clk_000_pe
|
||||
Net pos_clk_rst_dly_5_iv_i_2__n pos_clk.RST_DLY_5_iv_i[2]
|
||||
Net rw_000_int_0_un0_n RW_000_INT_0.un0
|
||||
Net un1_rst_dly_i_m_i_4__n un1_RST_DLY_i_m_i[4]
|
||||
Net sm_amiga_srsts_i_0_m2_3__un3_n SM_AMIGA_srsts_i_0_m2_3_.un3
|
||||
Net pos_clk_rst_dly_5_iv_i_3__n pos_clk.RST_DLY_5_iv_i[3]
|
||||
Net sm_amiga_srsts_i_0_m2_3__un1_n SM_AMIGA_srsts_i_0_m2_3_.un1
|
||||
End
|
||||
Section Type Name
|
||||
// ----------------------------------------------------------------------
|
||||
Input A_31_
|
||||
Input IPL_2_
|
||||
Input FC_1_
|
||||
Input A1
|
||||
Input nEXP_SPACE
|
||||
Input BG_030
|
||||
Input BGACK_000
|
||||
Input CLK_030
|
||||
Input CLK_000
|
||||
Input CLK_OSZI
|
||||
Input FPU_SENSE
|
||||
Input DTACK
|
||||
Input VPA
|
||||
Input RST
|
||||
Input A_30_
|
||||
Input A_29_
|
||||
Input A_28_
|
||||
Input A_27_
|
||||
Input A_26_
|
||||
Input A_25_
|
||||
Input A_24_
|
||||
Input A_23_
|
||||
Input A_22_
|
||||
Input A_21_
|
||||
Input A_20_
|
||||
Input A_19_
|
||||
Input A_18_
|
||||
Input A_17_
|
||||
Input A_16_
|
||||
Input A_15_
|
||||
Input A_14_
|
||||
Input A_13_
|
||||
Input A_12_
|
||||
Input A_11_
|
||||
Input A_10_
|
||||
Input A_9_
|
||||
Input A_8_
|
||||
Input A_7_
|
||||
Input A_6_
|
||||
Input A_5_
|
||||
Input A_4_
|
||||
Input A_3_
|
||||
Input A_2_
|
||||
Input IPL_1_
|
||||
Input IPL_0_
|
||||
Input FC_0_
|
||||
Output IPL_030_2_
|
||||
Output BG_000
|
||||
Output BGACK_030
|
||||
Output CLK_DIV_OUT
|
||||
Output CLK_EXP
|
||||
Output FPU_CS
|
||||
Output DSACK1
|
||||
Output AVEC
|
||||
Output E
|
||||
Output VMA
|
||||
Output RESET
|
||||
Output AMIGA_ADDR_ENABLE
|
||||
Output AMIGA_BUS_DATA_DIR
|
||||
Output AMIGA_BUS_ENABLE_LOW
|
||||
Output AMIGA_BUS_ENABLE_HIGH
|
||||
Output CIIN
|
||||
Output IPL_030_1_
|
||||
Output IPL_030_0_
|
||||
Bidi SIZE_1_
|
||||
Bidi AS_030
|
||||
Bidi AS_000
|
||||
Bidi RW_000
|
||||
Bidi DS_030
|
||||
Bidi UDS_000
|
||||
Bidi LDS_000
|
||||
Bidi A0
|
||||
Bidi BERR
|
||||
Bidi RW
|
||||
Bidi SIZE_0_
|
||||
End
|
||||
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Sat Mar 28 22:02:40 2015
|
||||
#Wed May 13 22:59:14 2015
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -18,17 +18,19 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
|
|||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -39,14 +41,14 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Mar 28 22:02:41 2015
|
||||
# Wed May 13 22:59:15 2015
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
|
|
@ -56,6 +58,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Mar 28 22:02:43 2015
|
||||
# Wed May 13 22:59:16 2015
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -28,9 +28,13 @@ SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
|
|||
SR<qM3="lkF8DHCVDRC"P(=""
|
||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.j"
|
||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j6jnj"
|
||||
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjjjjj/j">S
|
||||
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
|
||||
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/
|
||||
/>SqS<R"M=3MOF#M0N0C_soP"R=J"&k;F0ABtqid_jjh_Qa)_u &R4J0kF;>"/
|
||||
<SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>
|
||||
SR<qMF="s_HoH0M#_"FVR"P=&FJk0z;A1jnUdJj&k;F0"
|
||||
/>SqS<R"M=3HFsolhNCP"R=J"&k;F0Anz1Ujjd&FJk0/;">
|
||||
|
||||
|
||||
|
||||
/S<7>CV
|
||||
]</70p1s0kOk>sC
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Sat Mar 28 22:02:40 2015
|
||||
#-- Written on Wed May 13 22:59:14 2015
|
||||
|
||||
|
||||
#project files
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
ABEL5DEV=C:\ispLever\ispcpld\lib5
|
||||
DIOEDA_ABEL5DEV=C:\ispLever\ispcpld\lib5
|
||||
DIOEDA_ActiveHDL=C:\ispLever\active-hdl\BIN
|
||||
DIOEDA_ActiveHDLPath=C:\ispLever\active-hdl\BIN
|
||||
DIOEDA_AppNotes=C:\ispLever\ispcpld\bin
|
||||
DIOEDA_Bin=C:\ispLever\ispcpld\bin
|
||||
DIOEDA_Config=C:\ispLever\ispcpld\config
|
||||
DIOEDA_CONTEXT=ispLEVER CLASSIC
|
||||
DIOEDA_DSPPATH=C:\ispLever\ispLeverDSP
|
||||
DIOEDA_EPICPATH=C:\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_Examples=C:\ispLever\examples
|
||||
DIOEDA_FPGABinPath=C:\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_FPGAPath=C:\ispLever\ispfpga
|
||||
DIOEDA_HDLExplorer=C:\ispLever\hdle\win32
|
||||
DIOEDA_INI=C:\lsc_env
|
||||
DIOEDA_ispVM=C:\ispLever\ispvmsystem
|
||||
DIOEDA_ispVMSystem=C:\ispLever\ispvmsystem
|
||||
DIOEDA_License=C:\ispLever\license
|
||||
DIOEDA_MachPath=C:\ispLever\ispcpld\bin
|
||||
DIOEDA_Manuals=C:\ispLever\ispcpld\manuals
|
||||
DIOEDA_ModelSim=C:\ispLever\modelsim\win32loem
|
||||
DIOEDA_ModelsimPath=C:\ispLever\modelsim\win32loem
|
||||
DIOEDA_PDSPath=C:\ispLever\ispcomp
|
||||
DIOEDA_Precision=C:\isptools\precision
|
||||
DIOEDA_PrecisionPath=C:\isptools\precision
|
||||
DIOEDA_ProductName=ispLEVER
|
||||
DIOEDA_ProductPrefix=SYN
|
||||
DIOEDA_ProductTitle=ispLEVER
|
||||
DIOEDA_ProductType=1.8.00.04.29.14_LS_HDL_BASE_PC_N
|
||||
DIOEDA_ProductVersion=1.8.00.04
|
||||
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.8
|
||||
DIOEDA_Root=C:\ispLever\ispcpld
|
||||
DIOEDA_Spectrum=C:\isptools\spectrum
|
||||
DIOEDA_SpectrumPath=C:\isptools\spectrum
|
||||
DIOEDA_Synplify=C:\ispLever\synpbase
|
||||
DIOEDA_SynplifyPath=C:\ispLever\synpbase
|
||||
DIOEDA_Tutorial=C:\ispLever\ispcpld\tutorial
|
||||
DIOPRODUCT=ispLEVER
|
||||
PATH=C:\ispLever\ispcpld\bin
|
||||
|
|
@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Mar 28 22:02:43 2015
|
||||
# Wed May 13 22:59:16 2015
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
|
|||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030)
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -12,21 +13,21 @@ original code -> new code
|
|||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":187:4:187:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 73 uses
|
||||
DFF 83 uses
|
||||
BI_DIR 11 uses
|
||||
IBUF 46 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 2 uses
|
||||
AND2 270 uses
|
||||
INV 229 uses
|
||||
OR2 26 uses
|
||||
XOR2 4 uses
|
||||
OBUF 15 uses
|
||||
BUFTH 3 uses
|
||||
AND2 303 uses
|
||||
INV 263 uses
|
||||
XOR2 15 uses
|
||||
OR2 28 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -36,6 +37,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Mar 28 22:02:43 2015
|
||||
# Wed May 13 22:59:16 2015
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,2 @@
|
|||
@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":543:65:543:65|No identifier "a2" in scope
|
||||
@E|Parse errors encountered - exiting
|
||||
@E: CD395 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:53:144:62|Constant width 8 does not match context width 9
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,6 @@
|
|||
@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>10</data>
|
||||
<data>12</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
|
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1427576561</data>
|
||||
<data type="timestamp">1431550755</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -1,11 +1,13 @@
|
|||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":187:4:187:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":190:4:190:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
|
|||
|
|
@ -19,7 +19,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
</report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>1</data>
|
||||
<data>2</data>
|
||||
<report_link name="more">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
|
||||
</report_link>
|
||||
|
|
@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>105MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1427576563</data>
|
||||
<data type="timestamp">1431550756</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":497:16:497:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030)
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<html><body><samp><pre>
|
||||
<!@TC:1427576560>
|
||||
<!@TC:1431550754>
|
||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: C:\ispLever\synpbase
|
||||
#OS: Windows 7 6.1
|
||||
|
|
@ -8,29 +8,31 @@
|
|||
#Implementation: logic
|
||||
|
||||
<a name=compilerReport1>$ Start of Compile</a>
|
||||
#Sat Mar 28 22:02:40 2015
|
||||
#Wed May 13 22:59:14 2015
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1427576561> | Running in 64-bit mode
|
||||
@N: : <!@TM:1431550755> | Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1427576561> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1427576561> | Top entity is set to BUS68030.
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1431550755> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1431550755> | Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1427576561> | Synthesizing work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1427576561> | Signal clk_out_pre is undriven </font>
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1431550755> | Synthesizing work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:7:126:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1431550755> | Signal clk_out_pre is undriven </font>
|
||||
Post processing for work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1427576561> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1427576561> | Pruning register CLK_000_D4_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1427576561> | Pruning register CLK_000_D3_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:34:129:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1427576561> | Pruning register CLK_000_D2_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1427576561> | Pruning register CLK_OUT_PRE_50_D_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:152:2:152:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(152)</a><!@TM:1427576561> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:61:133:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1427576561> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1427576561> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1427576561> | Trying to extract state machine for register SM_AMIGA
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1431550755> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1431550755> | Pruning register CLK_000_D4_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1431550755> | Pruning register CLK_000_D3_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1431550755> | Pruning register CLK_000_D2_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:35:127:38:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1431550755> | Pruning register CLK_OUT_INT_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:36:124:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1431550755> | Pruning register CLK_OUT_PRE_50_D_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1431550755> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:135:61:135:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(135)</a><!@TM:1431550755> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1431550755> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1431550755> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1431550755> | Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -41,24 +43,24 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1427576561> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1427576561> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1431550755> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1431550755> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Mar 28 22:02:41 2015
|
||||
# Wed May 13 22:59:15 2015
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1427576563> | Running in 64-bit mode
|
||||
@N: : <!@TM:1431550756> | Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Mar 28 22:02:43 2015
|
||||
# Wed May 13 22:59:16 2015
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -66,7 +68,8 @@ Map & Optimize Report
|
|||
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1427576563> | Running in 64-bit mode.
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1431550756> | Running in 64-bit mode.
|
||||
<font color=#A52A2A>@W:<a href="@W:MO111:@XP_HELP">MO111</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:497:16:497:19:@W:MO111:@XP_MSG">68030-68000-bus.vhd(497)</a><!@TM:1431550756> | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) </font>
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -77,31 +80,31 @@ original code -> new code
|
|||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:187:4:187:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(187)</a><!@TM:1427576563> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1427576563> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:190:4:190:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(190)</a><!@TM:1431550756> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1431550756> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||
---------------------------------------
|
||||
<a name=resourceUsage3>Resource Usage Report</a>
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 73 uses
|
||||
DFF 83 uses
|
||||
BI_DIR 11 uses
|
||||
IBUF 46 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 2 uses
|
||||
AND2 270 uses
|
||||
INV 229 uses
|
||||
OR2 26 uses
|
||||
XOR2 4 uses
|
||||
OBUF 15 uses
|
||||
BUFTH 3 uses
|
||||
AND2 303 uses
|
||||
INV 263 uses
|
||||
XOR2 15 uses
|
||||
OR2 28 uses
|
||||
|
||||
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1427576563> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1431550756> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sat Mar 28 22:02:43 2015
|
||||
# Wed May 13 22:59:16 2015
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (22:02 28-Mar)</a>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (22:59 13-May)</a>
|
||||
<ul ></ul></li> </ul>
|
||||
</li>
|
||||
</ul>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
Synopsys, Inc.
|
||||
Version I-2014.03LC
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Sat Mar 28 22:02:40 2015
|
||||
Written on Wed May 13 22:59:14 2015
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -33,28 +33,28 @@
|
|||
<tr>
|
||||
<td class="optionTitle">Compile Input</td><td>Complete</td>
|
||||
<td>6</td>
|
||||
<td>10</td>
|
||||
<td>12</td>
|
||||
<td>0</td>
|
||||
<td>-</td>
|
||||
<td>0m:01s</td>
|
||||
<td>-</td>
|
||||
<td><font size="-1">28.03.2015</font><br/><font size="-2">22:02:41</font></td>
|
||||
<td><font size="-1">13.05.2015</font><br/><font size="-2">22:59:15</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Map & Optimize</td><td>Complete</td>
|
||||
<td>3</td>
|
||||
<td>1</td>
|
||||
<td>2</td>
|
||||
<td>0</td>
|
||||
<td>0m:00s</td>
|
||||
<td>0m:00s</td>
|
||||
<td>105MB</td>
|
||||
<td><font size="-1">28.03.2015</font><br/><font size="-2">22:02:43</font></td>
|
||||
<td><font size="-1">13.05.2015</font><br/><font size="-2">22:59:16</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Multi-srs Generator</td>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">28.03.2015</font><br/><font size="-2">22:02:43</font></td> </tbody>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">13.05.2015</font><br/><font size="-2">22:59:16</font></td> </tbody>
|
||||
</table>
|
||||
</td></tr></table></body>
|
||||
</html>
|
||||
|
|
@ -1,15 +1,15 @@
|
|||
#defaultlanguage:vhdl
|
||||
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
|
||||
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1427576546
|
||||
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401227704
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1431550739
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
|
|
@ -1,15 +1,15 @@
|
|||
#defaultlanguage:vhdl
|
||||
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
|
||||
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1427576546
|
||||
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401227704
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1431550739
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -1,15 +1,17 @@
|
|||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -20,5 +22,5 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
|
||||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue