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Stuck at 25MHz

This commit is contained in:
MHeinrichs 2014-08-12 21:24:42 +02:00
parent 1a7a72f376
commit 1f269e383c
23 changed files with 5512 additions and 254 deletions
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168
Logic/68030-68000-bus.vhd
View File

@ -121,6 +121,7 @@ signal CLK_OUT_PRE_50: STD_LOGIC := '1';
signal CLK_OUT_PRE_50_D: STD_LOGIC := '1';
signal CLK_OUT_PRE_25: STD_LOGIC := '1';
signal CLK_OUT_PRE_33: STD_LOGIC := '1';
signal CLK_OUT_PRE_33_D: STD_LOGIC := '1';
signal CLK_PRE_66:STD_LOGIC := '0';
signal CLK_OUT_PRE: STD_LOGIC := '1';
signal CLK_OUT_PRE_D: STD_LOGIC := '1';
@ -143,87 +144,31 @@ begin
--the clocks
neg_clk: process(RST, CLK_OSZI)
neg_clk: process(CLK_OSZI)
begin
if(RST = '0' ) then
CLK_CNT_N <= "10";
elsif(falling_edge(CLK_OSZI)) then
if(CLK_CNT_N = "10") then
if(falling_edge(CLK_OSZI)) then
if(CLK_CNT_N = "10" or RST = '0') then
CLK_CNT_N <= "00";
else
CLK_CNT_N <= CLK_CNT_N+1;
end if;
end if;
end process neg_clk;
--the state machine
state_machine: process(RST, CLK_OSZI)
begin
if(RST = '0' ) then
CLK_CNT_P <= "00";
RESET <= '0';
CLK_OUT_PRE_50 <= '0';
CLK_OUT_PRE_50_D <= '0';
--CLK_OUT_PRE_33 <= '0';
CLK_OUT_PRE_25 <= '0';
CLK_OUT_PRE <= '0';
CLK_OUT_PRE_D <= '0';
CLK_OUT_NE <= '0';
CLK_OUT_INT <= '0';
cpu_est <= E20;
CLK_000_D0 <= '1';
CLK_000_D1 <= '1';
CLK_000_D2 <= '1';
CLK_000_D3 <= '1';
CLK_000_D4 <= '1';
VPA_D <= '1';
DTACK_D0 <= '1';
SM_AMIGA <= IDLE_P;
AS_000_INT <= '1';
RW_000_INT <= '1';
RW_000_DMA <= '1';
AS_030_000_SYNC <= '1';
UDS_000_INT <= '1';
LDS_000_INT <= '1';
DS_000_ENABLE <= '0';
CLK_REF <= "00";
VMA_INT <= '1';
BG_000 <= '1';
BGACK_030_INT <= '1';
BGACK_030_INT_D <= '1';
DSACK1_INT <= '1';
IPL_030 <= "111";
CLK_000_P_SYNC <= "0000000000000";
CLK_000_N_SYNC <= "0000000000000";
CLK_000_PE <= '0';
CLK_000_NE <= '0';
CLK_000_NE_D0 <= '0';
AS_000_DMA <= '1';
DS_000_DMA <= '1';
SIZE_DMA <= "11";
A0_DMA <= '1';
AMIGA_BUS_ENABLE_INT <= '1';
AS_030_D0 <= '1';
DS_030_D0 <= '1';
elsif(rising_edge(CLK_OSZI)) then
--reset buffer
RESET <= '1';
--pos edge clock
pos_clk: process(CLK_OSZI)
begin
if(rising_edge(CLK_OSZI)) then
--clk generation :
CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
CLK_OUT_PRE_50_D<= CLK_OUT_PRE_50;
if(CLK_CNT_P = "10") then
if(CLK_CNT_P = "10" or RST = '0') then
CLK_CNT_P <= "00";
else
CLK_CNT_P <= CLK_CNT_P+1;
end if;
--if(CLK_CNT_P ="00" or CLK_CNT_N ="00")then --33MHz Clock
-- CLK_OUT_PRE_33 <= '0';
--else
-- CLK_OUT_PRE_33 <= '1';
--end if;
if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25;
end if;
@ -258,10 +203,6 @@ begin
CLK_000_PE <= CLK_000_P_SYNC(9);
CLK_000_NE <= CLK_000_N_SYNC(11);
CLK_000_NE_D0 <= CLK_000_NE;
DTACK_D0 <= DTACK;
VPA_D <= VPA;
--now: 68000 state machine and signals
-- e-clock is changed on the FALLING edge!
@ -289,9 +230,66 @@ begin
null;
end case;
end if;
end if;
end process pos_clk;
CLK_PRE_66 <= (not CLK_CNT_N(0) and CLK_CNT_P(0)) or
(CLK_CNT_N(1) and CLK_CNT_P(1));
process_33_clk:process(CLK_PRE_66)
begin
if(rising_edge(CLK_PRE_66)) then
CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
CLK_OUT_PRE_33_D <= CLK_OUT_PRE_33;
end if;
end process process_33_clk;
--output clock assignment
CLK_DIV_OUT <= CLK_OUT_PRE_D;
CLK_EXP <= CLK_OUT_PRE_D;
--the state machine
state_machine: process(RST, CLK_OSZI)
begin
if(RST = '0' ) then
RESET <= '0';
VPA_D <= '1';
DTACK_D0 <= '1';
SM_AMIGA <= IDLE_P;
AS_000_INT <= '1';
RW_000_INT <= '1';
RW_000_DMA <= '1';
AS_030_000_SYNC <= '1';
UDS_000_INT <= '1';
LDS_000_INT <= '1';
DS_000_ENABLE <= '0';
CLK_REF <= "00";
VMA_INT <= '1';
BG_000 <= '1';
BGACK_030_INT <= '1';
BGACK_030_INT_D <= '1';
DSACK1_INT <= '1';
IPL_030 <= "111";
AS_000_DMA <= '1';
DS_000_DMA <= '1';
SIZE_DMA <= "11";
A0_DMA <= '1';
AMIGA_BUS_ENABLE_INT <= '1';
AS_030_D0 <= '1';
DS_030_D0 <= '1';
CLK_030_H <= '0';
elsif(rising_edge(CLK_OSZI)) then
--reset buffer
RESET <= '1';
--now: 68000 state machine and signals
--buffering signals
AS_030_D0 <= AS_030;
DS_030_D0 <= DS_030;
DTACK_D0 <= DTACK;
VPA_D <= VPA;
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
@ -333,7 +331,7 @@ begin
DSACK1_INT <= '1';
AS_000_INT <= '1';
DS_000_ENABLE <= '0';
AMIGA_BUS_ENABLE_INT <= '1';
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
AS_030_D0 = '0' AND --as set
BGACK_000='1' AND --no dma -cycle
@ -377,11 +375,11 @@ begin
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
RW_000_INT <= '1';
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0')then
if(nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
SM_AMIGA<=IDLE_N; --go to s1
end if;
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
SM_AMIGA<=IDLE_N; --go to s1
else
AMIGA_BUS_ENABLE_INT <= '1';
end if;
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
if(CLK_000_PE='1')then --go to s2
@ -420,8 +418,8 @@ begin
SM_AMIGA<=DATA_FETCH_P;
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
if( (CLK_000_N_SYNC( 4)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_N_SYNC( 5)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
if( (CLK_000_N_SYNC( 5)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_N_SYNC( 6)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
DSACK1_INT <='0';
end if;
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
@ -490,23 +488,9 @@ begin
end if;
end process state_machine;
CLK_PRE_66 <= (not CLK_CNT_N(0) and CLK_CNT_P(0)) or
(CLK_CNT_N(1) and CLK_CNT_P(1));
process_33_clk:process(RST, CLK_PRE_66)
begin
if(RST = '0' ) then
CLK_OUT_PRE_33 <= '0';
elsif(rising_edge(CLK_PRE_66)) then
CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
end if;
end process process_33_clk;
--output clock assignment
CLK_DIV_OUT <= CLK_OUT_INT;
CLK_EXP <= CLK_OUT_INT;
-- bus drivers
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;

2
Logic/68030_TK.cmi
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@ -9,7 +9,7 @@ Remember_Setting=1
Open_PV_Opt=2
Open_PV=0
PV_IS_ACTIVE=0
ACTIVE_SHEET=Pin Attributes
ACTIVE_SHEET=Global Constraints
Show_Def_Opt=2
Show_Def_Val=1
Expand_All_Column=0

4235
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.crf
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@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Sun Aug 10 19:50:14 2014
// Design '68030_tk' created Tue Aug 12 21:21:14 2014
// LEGEND: '>' Functional Block Port Separator

2
Logic/68030_tk.ipr
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@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>4020=31 , ZM5
<LATTICE_ENCRYPTED_BLIF>46023=1P<d{ #

1110
Logic/68030_tk.jed Normal file
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File diff suppressed because it is too large Load Diff

46
Logic/BUS68030.fse
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@ -1,46 +1,20 @@
fsm_encoding {7140321401} onehot
fsm_encoding {7141321411} onehot
fsm_state_encoding {7140321401} idle_p {00000001}
fsm_state_encoding {7141321411} idle_p {00000001}
fsm_state_encoding {7140321401} idle_n {00000010}
fsm_state_encoding {7141321411} idle_n {00000010}
fsm_state_encoding {7140321401} as_set_p {00000100}
fsm_state_encoding {7141321411} as_set_p {00000100}
fsm_state_encoding {7140321401} as_set_n {00001000}
fsm_state_encoding {7141321411} as_set_n {00001000}
fsm_state_encoding {7140321401} sample_dtack_p {00010000}
fsm_state_encoding {7141321411} sample_dtack_p {00010000}
fsm_state_encoding {7140321401} data_fetch_n {00100000}
fsm_state_encoding {7141321411} data_fetch_n {00100000}
fsm_state_encoding {7140321401} data_fetch_p {01000000}
fsm_state_encoding {7141321411} data_fetch_p {01000000}
fsm_state_encoding {7140321401} end_cycle_n {10000000}
fsm_state_encoding {7141321411} end_cycle_n {10000000}
fsm_registers {7140321401} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]}
fsm_encoding {7128341282} original
fsm_state_encoding {7128341282} e20 {0000}
fsm_state_encoding {7128341282} e5 {0010}
fsm_state_encoding {7128341282} e6 {0011}
fsm_state_encoding {7128341282} e3 {0100}
fsm_state_encoding {7128341282} e4 {0101}
fsm_state_encoding {7128341282} e1 {0110}
fsm_state_encoding {7128341282} e2 {0111}
fsm_state_encoding {7128341282} e7 {1010}
fsm_state_encoding {7128341282} e8 {1011}
fsm_state_encoding {7128341282} e9 {1100}
fsm_state_encoding {7128341282} e10 {1111}
fsm_registers {7128341282} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]}
fsm_registers {7141321411} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]}

2
Logic/BUS68030.prj
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@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Sun Aug 10 19:50:07 2014
#-- Written on Tue Aug 12 21:21:07 2014
#device options

4
Logic/Programming.xcf
View File

@ -19,8 +19,8 @@
<BScanVal>0</BScanVal>
</Bypass>
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
<FileTime>08/09/14 13:04:48</FileTime>
<JedecChecksum>0xF4B9</JedecChecksum>
<FileTime>08/12/14 21:21:19</FileTime>
<JedecChecksum>0xC574</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>

76
Logic/bus68030.srf
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Sun Aug 10 19:50:07 2014
#Tue Aug 12 21:21:07 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -19,18 +19,20 @@ VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:2:498:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:35:126:37|Pruning register CLK_OUT_NE
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":161:2:161:3|Pruning register CLK_CNT_P(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_CNT_N(1 downto 0)
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:36:105:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:32:102:34|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_33_D
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":241:1:241:2|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_CNT_P(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:37:140:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -41,23 +43,9 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:34:128:36|Trying to extract state machine for register cpu_est
Extracted state machine for register cpu_est
State machine has 11 reachable states with original encodings of:
0000
0010
0011
0100
0101
0110
0111
1010
1011
1100
1111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Aug 10 19:50:07 2014
# Tue Aug 12 21:21:07 2014
###########################################################]
Map & Optimize Report
@ -76,43 +64,31 @@ original code -> new code
101 -> 00100000
110 -> 01000000
111 -> 10000000
Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral))
original code -> new code
0000 -> 0000
0010 -> 0010
0011 -> 0011
0100 -> 0100
0101 -> 0101
0110 -> 0110
0111 -> 0111
1010 -> 1010
1011 -> 1011
1100 -> 1100
1111 -> 1111
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":211:4:211:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
---------------------------------------
Resource Usage Report
Simple gate primitives:
DFFRH 44 uses
DFFSH 27 uses
DFF 1 use
DFFSH 25 uses
DFFRH 10 uses
DFF 36 uses
BI_DIR 13 uses
IBUF 30 uses
OBUF 16 uses
BUFTH 1 use
AND2 193 uses
INV 167 uses
XOR2 3 uses
OR2 23 uses
AND2 214 uses
INV 165 uses
OR2 21 uses
XOR2 2 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
G-2012.09LC-SP1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Aug 10 19:50:09 2014
# Tue Aug 12 21:21:09 2014
###########################################################]

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Sun Aug 10 19:50:07 2014
#-- Written on Tue Aug 12 21:21:07 2014
#project files

32
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -12,43 +12,31 @@ original code -> new code
101 -> 00100000
110 -> 01000000
111 -> 10000000
Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral))
original code -> new code
0000 -> 0000
0010 -> 0010
0011 -> 0011
0100 -> 0100
0101 -> 0101
0110 -> 0110
0111 -> 0111
1010 -> 1010
1011 -> 1011
1100 -> 1100
1111 -> 1111
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":211:4:211:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
---------------------------------------
Resource Usage Report
Simple gate primitives:
DFFRH 44 uses
DFFSH 27 uses
DFF 1 use
DFFSH 25 uses
DFFRH 10 uses
DFF 36 uses
BI_DIR 13 uses
IBUF 30 uses
OBUF 16 uses
BUFTH 1 use
AND2 193 uses
INV 167 uses
XOR2 3 uses
OR2 23 uses
AND2 214 uses
INV 165 uses
OR2 21 uses
XOR2 2 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
G-2012.09LC-SP1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Aug 10 19:50:09 2014
# Tue Aug 12 21:21:09 2014
###########################################################]

2
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,3 +1,3 @@
@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":488:5:488:11|Expecting keyword if
@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":248:32:248:32|No identifier "clk_out_pre_25_d" in scope
@E|Parse errors encountered - exiting

4
Logic/synlog/report/BUS68030_compiler_notes.txt
View File

@ -2,6 +2,6 @@
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Trying to extract state machine for register SM_AMIGA
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:34:128:36|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:37:140:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Trying to extract state machine for register SM_AMIGA

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>10</data>
<data>12</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1407693007</data>
<data type="timestamp">1407871267</data>
</info>
</job_info>
</job_run_status>

22
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,11 +1,13 @@
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:2:498:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:35:126:37|Pruning register CLK_OUT_NE
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":161:2:161:3|Pruning register CLK_CNT_P(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_CNT_N(1 downto 0)
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:36:105:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_33_D
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":241:1:241:2|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_CNT_P(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...

1
Logic/synlog/report/BUS68030_fpga_mapper_notes.txt
View File

@ -1,2 +1,3 @@
@N: MF248 |Running in 64-bit mode.
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":211:4:211:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.

6
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -12,7 +12,7 @@ The file contains the job information from mapper to be displayed as part of the
</job_status>
<job_info>
<info name="Notes">
<data>2</data>
<data>3</data>
<report_link name="more">
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_notes.txt</data>
</report_link>
@ -36,10 +36,10 @@ The file contains the job information from mapper to be displayed as part of the
<data>0h:00m:00s</data>
</info>
<info name="Peak Memory">
<data>95MB</data>
<data>96MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1407693009</data>
<data type="timestamp">1407871269</data>
</info>
</job_info>
</job_run_status>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Sun Aug 10 19:50:07 2014
Written on Tue Aug 12 21:21:07 2014
-->

2
Logic/synwork/BUS68030_compiler.fdep
View File

@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407693003
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407871262
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_compiler.fdeporig
View File

@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407693003
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407871262
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_compiler.srs
View File

Binary file not shown.

40
Logic/synwork/BUS68030_compiler.tlg
View File

@ -1,17 +1,19 @@
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:2:498:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:35:126:37|Pruning register CLK_OUT_NE
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":161:2:161:3|Pruning register CLK_CNT_P(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_CNT_N(1 downto 0)
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:36:105:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:32:102:34|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Trying to extract state machine for register SM_AMIGA
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_33_D
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":241:1:241:2|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_CNT_P(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:37:140:39|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":141:32:141:34|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -22,17 +24,3 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:34:128:36|Trying to extract state machine for register cpu_est
Extracted state machine for register cpu_est
State machine has 11 reachable states with original encodings of:
0000
0010
0011
0100
0101
0110
0111
1010
1011
1100
1111