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68030tk
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Update - minor changes

This commit is contained in:
MHeinrichs 2014-08-12 20:28:14 +02:00
parent d39a0451d5
commit 1a7a72f376
17 changed files with 1512 additions and 50 deletions
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32
Logic/68030-68000-bus.vhd
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@ -136,7 +136,7 @@ signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
signal CLK_000_PE: STD_LOGIC := '0';
signal CLK_000_NE: STD_LOGIC := '0';
signal CLK_000_E_ADVANCE: STD_LOGIC := '0';
signal CLK_000_NE_D0: STD_LOGIC := '0';
signal DTACK_D0: STD_LOGIC := '1';
begin
@ -196,7 +196,7 @@ begin
CLK_000_N_SYNC <= "0000000000000";
CLK_000_PE <= '0';
CLK_000_NE <= '0';
CLK_000_E_ADVANCE <= '0';
CLK_000_NE_D0 <= '0';
AS_000_DMA <= '1';
DS_000_DMA <= '1';
SIZE_DMA <= "11";
@ -257,7 +257,7 @@ begin
-- since the clock is not symmetrically these values differ!
CLK_000_PE <= CLK_000_P_SYNC(9);
CLK_000_NE <= CLK_000_N_SYNC(11);
CLK_000_E_ADVANCE <= CLK_000_NE;
CLK_000_NE_D0 <= CLK_000_NE;
DTACK_D0 <= DTACK;
VPA_D <= VPA;
@ -265,7 +265,8 @@ begin
-- e-clock is changed on the FALLING edge!
if(CLK_000_E_ADVANCE = '1' ) then
if(CLK_000_NE_D0 = '1' ) then
--if(CLK_000_D0='0' AND CLK_000_D1='1') then
case (cpu_est) is
when E1 => cpu_est <= E2 ;
when E2 => cpu_est <= E3 ;
@ -298,7 +299,7 @@ begin
BGACK_030_INT <= '0';
elsif ( BGACK_000='1'
AND CLK_000_PE='1'
--AND CLK_000_D1='0' and CLK_000_D0='1'
--AND CLK_000_D0='1' and CLK_000_D1='0'
) then -- BGACK_000 is high here!
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
end if;
@ -319,8 +320,8 @@ begin
--interrupt buffering to avoid ghost interrupts
--if(CLK_000_NE='1')then
if(CLK_000_D0='0' and CLK_000_D1='1')then
if(CLK_000_NE='1')then
--if(CLK_000_D0='0' and CLK_000_D1='1')then
IPL_030<=IPL;
end if;
@ -346,9 +347,10 @@ begin
-- VMA generation
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
--if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert
VMA_INT <= '0';
--elsif(CLK_000_PE='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
VMA_INT <= '1';
end if;
--uds/lds precalculation
@ -374,7 +376,7 @@ begin
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
RW_000_INT <= '1';
RW_000_INT <= '1';
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0')then
if(nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
@ -407,8 +409,8 @@ begin
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
if( CLK_000_NE='1' and --falling edge
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
((VPA = '1' AND DTACK='0') OR --DTACK end cycle
(VPA='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
)then --go to s5
SM_AMIGA<=DATA_FETCH_N;
end if;
@ -418,8 +420,8 @@ begin
SM_AMIGA<=DATA_FETCH_P;
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
if( (CLK_000_N_SYNC( 5)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_N_SYNC( 6)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
if( (CLK_000_N_SYNC( 4)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
(CLK_000_N_SYNC( 5)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
DSACK1_INT <='0';
end if;
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
@ -434,7 +436,7 @@ begin
if(CLK_000_PE='1')then --go to s0
--if(CLK_000_D0='1')then --go to s0
SM_AMIGA<=IDLE_P;
VMA_INT <= '1';
RW_000_INT <= '1';
end if;
end case;

1464
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.crf
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@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Sat Aug 09 23:50:26 2014
// Design '68030_tk' created Sun Aug 10 19:50:14 2014
// LEGEND: '>' Functional Block Port Separator

3
Logic/68030_tk.ipr
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@ -1,2 +1 @@
<LATTICE_ENCRYPTED_BLIF>6322631O
GG?K
<LATTICE_ENCRYPTED_BLIF>4020=31 , ZM5

2
Logic/BUS68030.prj
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@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Sat Aug 09 23:50:19 2014
#-- Written on Sun Aug 10 19:50:07 2014
#device options

21
Logic/bus68030.srf
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Sat Aug 09 23:50:20 2014
#Sun Aug 10 19:50:07 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -19,9 +19,8 @@ VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:2:496:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:2:498:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:29:112:31|Pruning register DTACK_D0
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2
@ -58,7 +57,7 @@ State machine has 11 reachable states with original encodings of:
1111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Aug 09 23:50:20 2014
# Sun Aug 10 19:50:07 2014
###########################################################]
Map & Optimize Report
@ -95,25 +94,25 @@ Resource Usage Report
Simple gate primitives:
DFFRH 44 uses
DFFSH 26 uses
DFFSH 27 uses
DFF 1 use
BI_DIR 13 uses
IBUF 30 uses
OBUF 16 uses
BUFTH 1 use
AND2 201 uses
INV 164 uses
OR2 21 uses
XOR2 2 uses
AND2 193 uses
INV 167 uses
XOR2 3 uses
OR2 23 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
G-2012.09LC-SP1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Aug 09 23:50:21 2014
# Sun Aug 10 19:50:09 2014
###########################################################]

2
Logic/run_options.txt
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@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Sat Aug 09 23:50:20 2014
#-- Written on Sun Aug 10 19:50:07 2014
#project files

14
Logic/synlog/bus68030_fpga_mapper.srr
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@ -30,25 +30,25 @@ Resource Usage Report
Simple gate primitives:
DFFRH 44 uses
DFFSH 26 uses
DFFSH 27 uses
DFF 1 use
BI_DIR 13 uses
IBUF 30 uses
OBUF 16 uses
BUFTH 1 use
AND2 201 uses
INV 164 uses
OR2 21 uses
XOR2 2 uses
AND2 193 uses
INV 167 uses
XOR2 3 uses
OR2 23 uses
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
G-2012.09LC-SP1
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Aug 09 23:50:21 2014
# Sun Aug 10 19:50:09 2014
###########################################################]

2
Logic/synlog/report/BUS68030_compiler_errors.txt
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@ -1,3 +1,3 @@
@E: CG119 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":294:48:294:49|Expecting closing )
@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":488:5:488:11|Expecting keyword if
@E|Parse errors encountered - exiting

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>11</data>
<data>10</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1407621020</data>
<data type="timestamp">1407693007</data>
</info>
</job_info>
</job_run_status>

3
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,6 +1,5 @@
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:2:496:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:2:498:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:29:112:31|Pruning register DTACK_D0
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2

4
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -36,10 +36,10 @@ The file contains the job information from mapper to be displayed as part of the
<data>0h:00m:00s</data>
</info>
<info name="Peak Memory">
<data>96MB</data>
<data>95MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1407621021</data>
<data type="timestamp">1407693009</data>
</info>
</job_info>
</job_run_status>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Sat Aug 09 23:50:20 2014
Written on Sun Aug 10 19:50:07 2014
-->

2
Logic/synwork/BUS68030_compiler.fdep
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@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407621014
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407693003
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_compiler.fdeporig
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@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407621014
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407693003
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_compiler.srs
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Binary file not shown.

3
Logic/synwork/BUS68030_compiler.tlg
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@ -1,8 +1,7 @@
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:2:496:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:2:498:3|Pruning register CLK_OUT_PRE_33
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":140:32:140:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:29:112:31|Pruning register DTACK_D0
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2