mirror of https://github.com/kr239/68030tk.git
50Mhz version
This commit is contained in:
MHeinrichs
parent
5eee23fe31
commit
63002d2099
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@ -162,7 +162,8 @@ begin
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--here the clock is selected
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CLK_OUT_PRE_D <= CLK_OUT_PRE_25;
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--CLK_OUT_PRE_D <= CLK_OUT_PRE_25;
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CLK_OUT_PRE_D <= CLK_OUT_PRE_50;
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-- the external clock to the processor is generated here
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CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
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@ -505,7 +506,7 @@ begin
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--output clock assignment
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CLK_DIV_OUT <= CLK_OUT_INT;
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CLK_EXP <= not CLK_OUT_EXP_INT;
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CLK_EXP <= CLK_OUT_INT;--not CLK_OUT_EXP_INT;
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--CLK_DIV_OUT <= 'Z';
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--CLK_EXP <= CLK_030;
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@ -351181,3 +351181,186 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
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########## Tcl recorder end at 01/24/16 16:20:40 ###########
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########## Tcl recorder starts at 01/25/16 07:24:04 ##########
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# Commands to make the Process:
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# Hierarchy
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if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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########## Tcl recorder end at 01/25/16 07:24:04 ###########
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########## Tcl recorder starts at 01/25/16 07:24:04 ##########
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# Commands to make the Process:
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# JEDEC File
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if [catch {open BUS68030.cmd w} rspFile] {
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puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
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} else {
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puts $rspFile "STYFILENAME: 68030_tk.sty
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PROJECT: BUS68030
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WORKING_PATH: \"$proj_dir\"
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MODULE: BUS68030
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VHDL_FILE_LIST: 68030-68000-bus.vhd
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OUTPUT_FILE_NAME: BUS68030
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SUFFIX_NAME: edi
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PART: M4A5-128/64-10VC
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"
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close $rspFile
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}
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if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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file delete BUS68030.cmd
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if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [catch {open 68030_tk.rsp w} rspFile] {
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puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
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} else {
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puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
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"
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close $rspFile
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}
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if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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file delete 68030_tk.rsp
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if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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########## Tcl recorder end at 01/25/16 07:24:04 ###########
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2940
Logic/68030_tk.bl2
2940
Logic/68030_tk.bl2
File diff suppressed because it is too large
Load Diff
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@ -1,164 +1,110 @@
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#$ TOOL ispLEVER Classic 1.8.00.04.29.14
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#$ DATE Sun Jan 24 16:20:54 2016
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#$ DATE Mon Jan 25 07:24:19 2016
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#$ MODULE 68030_tk
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#$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ IPL_030_1_ IPL_030_0_ FC_1_ IPL_1_ AS_030 \
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# IPL_0_ AS_000 FC_0_ RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \
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#$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ \
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# AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \
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# BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE \
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# DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ \
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# AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH A_29_ CIIN A_28_ A_27_ A_26_ A_25_ \
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# DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR \
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# A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ \
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# A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_
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#$ NODES 81 inst_BGACK_030_INTreg inst_CLK_OUT_INTreg inst_VMA_INTreg cpu_est_0_ \
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# cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT SM_AMIGA_5_ \
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# inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg \
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# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \
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# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \
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# inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT \
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# inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0 \
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# inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE \
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# CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ \
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# inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg SM_AMIGA_4_ inst_DS_000_ENABLE \
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# RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ \
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# CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ \
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# CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ \
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# CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ \
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# CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ \
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# CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA \
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# SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ \
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# BG_000DFFreg IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg
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#$ NODES 79 inst_BGACK_030_INTreg inst_VMA_INTreg N_317_i cpu_est_2_ cpu_est_3_ \
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# cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW \
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# inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D \
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# inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ \
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# inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 \
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# inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE \
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# CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \
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# inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \
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# SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \
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# CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ \
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# CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \
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# CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ \
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# CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ \
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# CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_RW_000_INT \
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# inst_RW_000_DMA inst_A0_DMA SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ \
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# SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg \
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# IPL_030DFF_1_reg IPL_030DFF_2_reg
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.model bus68030
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.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
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BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
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DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
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A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
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A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
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inst_BGACK_030_INTreg.BLIF inst_CLK_OUT_INTreg.BLIF inst_VMA_INTreg.BLIF \
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cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
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inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \
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inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
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inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \
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CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \
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inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \
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inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \
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inst_CLK_OUT_PRE_50.BLIF N_210_i.BLIF inst_CLK_OUT_PRE_25.BLIF \
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inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
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inst_CLK_OUT_EXP_INT.BLIF CLK_000_P_SYNC_9_.BLIF inst_CLK_000_NE.BLIF \
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CLK_000_N_SYNC_11_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \
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inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
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inst_DSACK1_INTreg.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF \
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RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF CLK_000_P_SYNC_0_.BLIF \
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CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF \
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CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF \
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CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_N_SYNC_0_.BLIF \
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CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \
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CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.BLIF \
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CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \
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CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF \
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inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \
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SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF \
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IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF \
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AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \
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LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF \
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RW.PIN.BLIF
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inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF N_317_i.BLIF cpu_est_2_.BLIF \
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cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \
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SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \
|
||||
inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
|
||||
inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
|
||||
SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF \
|
||||
inst_LDS_000_INT.BLIF inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF \
|
||||
inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_000_D1.BLIF \
|
||||
inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF CLK_000_P_SYNC_9_.BLIF \
|
||||
inst_CLK_000_NE.BLIF CLK_000_N_SYNC_11_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \
|
||||
IPL_D0_2_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF \
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_4_.BLIF \
|
||||
inst_DS_000_ENABLE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF \
|
||||
CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF \
|
||||
CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF \
|
||||
CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF \
|
||||
CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF \
|
||||
CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF \
|
||||
CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF \
|
||||
CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF \
|
||||
inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF inst_CLK_030_H.BLIF \
|
||||
SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \
|
||||
BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \
|
||||
IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \
|
||||
RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \
|
||||
SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF
|
||||
.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
|
||||
AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
|
||||
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \
|
||||
SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \
|
||||
AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \
|
||||
SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \
|
||||
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D \
|
||||
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \
|
||||
IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \
|
||||
IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \
|
||||
CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
|
||||
CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
|
||||
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
|
||||
CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
|
||||
CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
|
||||
CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
|
||||
SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \
|
||||
CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \
|
||||
CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \
|
||||
CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D \
|
||||
CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C \
|
||||
CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D \
|
||||
CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C \
|
||||
CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \
|
||||
CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \
|
||||
CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \
|
||||
CLK_000_N_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \
|
||||
RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \
|
||||
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
|
||||
inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
|
||||
inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \
|
||||
SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \
|
||||
IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \
|
||||
IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
|
||||
IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \
|
||||
CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \
|
||||
CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D \
|
||||
CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \
|
||||
SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \
|
||||
cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \
|
||||
CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
|
||||
CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \
|
||||
CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \
|
||||
CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \
|
||||
CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \
|
||||
CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \
|
||||
CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \
|
||||
CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \
|
||||
CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \
|
||||
CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \
|
||||
CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \
|
||||
CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \
|
||||
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \
|
||||
CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D \
|
||||
inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
|
||||
inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
|
||||
inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \
|
||||
inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \
|
||||
inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \
|
||||
inst_RESET_OUT.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D \
|
||||
inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \
|
||||
BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
|
||||
inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
|
||||
inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE.D \
|
||||
inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
|
||||
inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C inst_CLK_000_D1.D \
|
||||
inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \
|
||||
inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \
|
||||
inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \
|
||||
inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D \
|
||||
inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
|
||||
inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C inst_CLK_OUT_PRE_D.D \
|
||||
inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D \
|
||||
inst_CLK_000_PE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \
|
||||
SIZE_0_ N_210_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
|
||||
SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE \
|
||||
inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
cpu_est_2_.BLIF cpu_est_3_.BLIF SM_AMIGA_5_.BLIF inst_VPA_D.BLIF \
|
||||
inst_DTACK_D0.BLIF N_210_i.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
|
||||
inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \
|
||||
SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
|
||||
SM_AMIGA_i_7_.D
|
||||
10000100-1--10000-0- 1
|
||||
100001-0-1-11000--0- 1
|
||||
10000100-11-10--0--- 1
|
||||
100001-0-11110------ 1
|
||||
1-----0101--10000-0- 1
|
||||
1------101-11000--0- 1
|
||||
1-----0--1---000000- 1
|
||||
1-----01011-10--0--- 1
|
||||
1--------1-1-000-00- 1
|
||||
1------1011110------ 1
|
||||
1-----0--11--0--00-- 1
|
||||
1--------111-0---0-- 1
|
||||
1--------10--------1 1
|
||||
1--------1---0-----1 1
|
||||
-------11--------1-0 0
|
||||
----------1--1------ 0
|
||||
-----0-0---------1-0 0
|
||||
----1--0---------1-0 0
|
||||
---1---0---------1-0 0
|
||||
--1----0---------1-0 0
|
||||
-1-----0---------1-0 0
|
||||
-----------0----1--0 0
|
||||
------1----0-------0 0
|
||||
----------0-------10 0
|
||||
----------0----1---0 0
|
||||
----------0---1----0 0
|
||||
------------0----1-0 0
|
||||
---------0---------- 0
|
||||
0------------------- 0
|
||||
-------------1-----0 0
|
||||
.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
|
||||
inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
|
||||
SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
|
||||
11010--0- 1
|
||||
1----01-1 1
|
||||
1-----10- 1
|
||||
-----1-1- 0
|
||||
----1-0-- 0
|
||||
---0--0-- 0
|
||||
--1---0-- 0
|
||||
-0----0-- 0
|
||||
------01- 0
|
||||
0-------- 0
|
||||
-------10 0
|
||||
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \
|
||||
inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C \
|
||||
inst_CLK_000_NE.D inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 \
|
||||
LDS_000 A0 BERR RW SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \
|
||||
LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE \
|
||||
RESET.OE CIIN.OE inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 \
|
||||
SM_AMIGA_3_.D.X2
|
||||
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
|
||||
SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
|
||||
101-1- 1
|
||||
|
|
@ -179,19 +125,19 @@ SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
|
|||
-0--0- 0
|
||||
0----- 0
|
||||
-0---0 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
|
||||
inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
|
||||
BERR.PIN.BLIF SM_AMIGA_2_.D
|
||||
1000010--11-- 1
|
||||
1001000--11-- 1
|
||||
1-----10-11-- 1
|
||||
1-------0--11 1
|
||||
1---------11- 1
|
||||
------11---0- 0
|
||||
--------1-0-- 0
|
||||
-----00----0- 0
|
||||
-----10----0- 0
|
||||
----1-0----0- 0
|
||||
---1--0----0- 0
|
||||
---0--0----0- 0
|
||||
--1---0----0- 0
|
||||
-1----0----0- 0
|
||||
---------0-0- 0
|
||||
|
|
@ -217,25 +163,6 @@ SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
|
|||
--00-- 0
|
||||
---1-0 0
|
||||
0----- 0
|
||||
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF inst_CLK_000_NE_D0.BLIF \
|
||||
cpu_est_2_.D
|
||||
1101 1
|
||||
-01- 1
|
||||
0-1- 1
|
||||
--10 1
|
||||
1111 0
|
||||
-00- 0
|
||||
0-0- 0
|
||||
--00 0
|
||||
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
inst_CLK_000_NE_D0.BLIF cpu_est_3_.D
|
||||
111-1 1
|
||||
0--1- 1
|
||||
---10 1
|
||||
0--0- 0
|
||||
1-0-1 0
|
||||
10--1 0
|
||||
---00 0
|
||||
.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
|
||||
IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D
|
||||
0-01100- 1
|
||||
|
|
@ -317,6 +244,56 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
|
|||
1- 1
|
||||
-0 1
|
||||
01 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF N_317_i.BLIF cpu_est_2_.BLIF \
|
||||
cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF SM_AMIGA_5_.BLIF \
|
||||
inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
|
||||
inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \
|
||||
SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
|
||||
SM_AMIGA_i_7_.D
|
||||
101010000---10000-0- 1
|
||||
1010100-0--11000--0- 1
|
||||
101010000-1-10--0--- 1
|
||||
1010100-0-1110------ 1
|
||||
1-1----010--10000-0- 1
|
||||
1-1-----10-11000--0- 1
|
||||
1-1----0-----000000- 1
|
||||
1-1----0101-10--0--- 1
|
||||
1-1--------1-000-00- 1
|
||||
1-1-----101110------ 1
|
||||
1-1----0--1--0--00-- 1
|
||||
1-1-------11-0---0-- 1
|
||||
1-1-------0--------1 1
|
||||
1-1----------0-----1 1
|
||||
--------11-------1-0 0
|
||||
----------1--1------ 0
|
||||
------1-0--------1-0 0
|
||||
-----1--0--------1-0 0
|
||||
----0---0--------1-0 0
|
||||
---1----0--------1-0 0
|
||||
-1------0--------1-0 0
|
||||
-----------0----1--0 0
|
||||
-------1---0-------0 0
|
||||
----------0-------10 0
|
||||
----------0----1---0 0
|
||||
----------0---1----0 0
|
||||
------------0----1-0 0
|
||||
--0----------------- 0
|
||||
0------------------- 0
|
||||
-------------1-----0 0
|
||||
.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
|
||||
inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
|
||||
SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
|
||||
11010--0- 1
|
||||
1----01-1 1
|
||||
1-----10- 1
|
||||
-----1-1- 0
|
||||
----1-0-- 0
|
||||
---0--0-- 0
|
||||
--1---0-- 0
|
||||
-0----0-- 0
|
||||
------01- 0
|
||||
0-------- 0
|
||||
-------10 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \
|
||||
inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
|
||||
10100 1
|
||||
|
|
@ -355,24 +332,35 @@ SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
|
|||
11-0-- 0
|
||||
110--- 0
|
||||
10---1 0
|
||||
.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_3_.BLIF inst_CLK_000_NE_D0.BLIF \
|
||||
.names cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \
|
||||
cpu_est_1_.D
|
||||
1001 1
|
||||
01-- 1
|
||||
-1-0 1
|
||||
-01- 0
|
||||
11-1 0
|
||||
0101 1
|
||||
-01- 1
|
||||
--10 1
|
||||
1-0- 0
|
||||
-111 0
|
||||
-00- 0
|
||||
--00 0
|
||||
.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \
|
||||
cpu_est_2_.D
|
||||
0111 1
|
||||
1-0- 1
|
||||
10-- 1
|
||||
1--0 1
|
||||
1111 0
|
||||
0-0- 0
|
||||
00-- 0
|
||||
-0-0 0
|
||||
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
||||
RST_DLY_2_.BLIF RST_DLY_0_.D
|
||||
0--0 0
|
||||
.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
inst_CLK_000_NE_D0.BLIF cpu_est_3_.D
|
||||
1-111 1
|
||||
110-- 1
|
||||
101-- 1
|
||||
-110- 0
|
||||
-00-- 0
|
||||
-11-0 0
|
||||
0---- 0
|
||||
010-- 1
|
||||
-1--0 1
|
||||
--101 0
|
||||
00--- 0
|
||||
1-0-1 0
|
||||
0-1-1 0
|
||||
-0--0 0
|
||||
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
||||
RST_DLY_2_.BLIF RST_DLY_1_.D
|
||||
1--11 1
|
||||
|
|
@ -395,65 +383,15 @@ RST_DLY_2_.BLIF RST_DLY_2_.D
|
|||
01 1
|
||||
1- 0
|
||||
-0 0
|
||||
.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF inst_CLK_000_PE.BLIF \
|
||||
SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \
|
||||
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
|
||||
10--00-01-- 1
|
||||
10-10--01-- 1
|
||||
1-0---1--1- 1
|
||||
1---00-01-1 1
|
||||
1--10--01-1 1
|
||||
---0-1---0- 0
|
||||
---0-10---- 0
|
||||
--10-1----- 0
|
||||
-1-------00 0
|
||||
-1----0---0 0
|
||||
-11-------0 0
|
||||
--------00- 0
|
||||
-------1-0- 0
|
||||
----1----0- 0
|
||||
------0-0-- 0
|
||||
--1-----0-- 0
|
||||
------01--- 0
|
||||
--1----1--- 0
|
||||
----1-0---- 0
|
||||
--1-1------ 0
|
||||
0---------- 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
||||
inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
|
||||
-1-1- 1
|
||||
-10-- 1
|
||||
0---- 1
|
||||
-0--1 1
|
||||
1110- 0
|
||||
10--0 0
|
||||
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \
|
||||
inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
|
||||
-0--1-- 1
|
||||
-011--- 1
|
||||
-0---0- 1
|
||||
0------ 1
|
||||
-1----1 1
|
||||
10-001- 0
|
||||
100-01- 0
|
||||
11----0 0
|
||||
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
|
||||
SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
|
||||
--1100 1
|
||||
-10--- 1
|
||||
0----- 1
|
||||
100--- 0
|
||||
1-1-1- 0
|
||||
1-10-- 0
|
||||
1-1--1 0
|
||||
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \
|
||||
AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
|
||||
1-1-- 1
|
||||
1--11 1
|
||||
-0--- 1
|
||||
-100- 0
|
||||
-10-0 0
|
||||
01--- 0
|
||||
.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
|
||||
RST_DLY_2_.BLIF RST_DLY_0_.D
|
||||
1-111 1
|
||||
110-- 1
|
||||
101-- 1
|
||||
-110- 0
|
||||
-00-- 0
|
||||
-11-0 0
|
||||
0---- 0
|
||||
.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
|
||||
CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
|
||||
LDS_000.PIN.BLIF inst_AS_000_DMA.D
|
||||
|
|
@ -570,6 +508,30 @@ RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D
|
|||
-00--- 0
|
||||
0----- 0
|
||||
-0---0 0
|
||||
.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF inst_CLK_000_PE.BLIF \
|
||||
SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \
|
||||
SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
|
||||
10--00-01-- 1
|
||||
10-10--01-- 1
|
||||
1-0---1--1- 1
|
||||
1---00-01-1 1
|
||||
1--10--01-1 1
|
||||
---0-1---0- 0
|
||||
---0-10---- 0
|
||||
--10-1----- 0
|
||||
-1-------00 0
|
||||
-1----0---0 0
|
||||
-11-------0 0
|
||||
--------00- 0
|
||||
-------1-0- 0
|
||||
----1----0- 0
|
||||
------0-0-- 0
|
||||
--1-----0-- 0
|
||||
------01--- 0
|
||||
--1----1--- 0
|
||||
----1-0---- 0
|
||||
--1-1------ 0
|
||||
0---------- 0
|
||||
.names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \
|
||||
inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
|
||||
----01 1
|
||||
|
|
@ -596,23 +558,23 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.D
|
|||
-0--- 1
|
||||
-1101 0
|
||||
110-- 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF \
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF \
|
||||
inst_CLK_000_NE.BLIF inst_VMA_INTreg.D
|
||||
--0000-1- 1
|
||||
-1----1-- 1
|
||||
-1-0----- 1
|
||||
-10------ 1
|
||||
-1---0--- 1
|
||||
-1--0---- 1
|
||||
-1------0 1
|
||||
0-------- 1
|
||||
-1---1--- 1
|
||||
-1--1---- 1
|
||||
1-11000-1 0
|
||||
-1-1----- 1
|
||||
-11------ 1
|
||||
1-00110-1 0
|
||||
10-----0- 0
|
||||
10---1--- 0
|
||||
10--1---- 0
|
||||
10-1----- 0
|
||||
101------ 0
|
||||
10---1--- 0
|
||||
10--1---- 0
|
||||
.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A0.PIN.BLIF \
|
||||
inst_UDS_000_INT.D
|
||||
-10- 1
|
||||
|
|
@ -628,6 +590,41 @@ inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
|
|||
11-0- 0
|
||||
110-- 0
|
||||
10--0 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
|
||||
inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
|
||||
-1-1- 1
|
||||
-10-- 1
|
||||
0---- 1
|
||||
-0--1 1
|
||||
1110- 0
|
||||
10--0 0
|
||||
.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \
|
||||
inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
|
||||
-0--1-- 1
|
||||
-011--- 1
|
||||
-0---0- 1
|
||||
0------ 1
|
||||
-1----1 1
|
||||
10-001- 0
|
||||
100-01- 0
|
||||
11----0 0
|
||||
.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
|
||||
SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
|
||||
--1100 1
|
||||
-10--- 1
|
||||
0----- 1
|
||||
100--- 0
|
||||
1-1-1- 0
|
||||
1-10-- 0
|
||||
1-1--1 0
|
||||
.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \
|
||||
AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
|
||||
1-1-- 1
|
||||
1--11 1
|
||||
-0--- 1
|
||||
-100- 0
|
||||
-10-0 0
|
||||
01--- 0
|
||||
.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
|
||||
0- 1
|
||||
-1 1
|
||||
|
|
@ -637,7 +634,7 @@ inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
|
|||
1 0
|
||||
.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
|
||||
inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
|
||||
SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_210_i
|
||||
SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_317_i
|
||||
-1010------ 1
|
||||
---------1- 1
|
||||
--------1-- 1
|
||||
|
|
@ -663,12 +660,12 @@ SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_210_i
|
|||
.names inst_BGACK_030_INTreg.BLIF BGACK_030
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT
|
||||
.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OUT_INTreg.BLIF CLK_EXP
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_OUT_EXP_INT.BLIF CLK_EXP
|
||||
0 1
|
||||
1 0
|
||||
.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \
|
||||
A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS
|
||||
-------0- 1
|
||||
|
|
@ -686,12 +683,12 @@ A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS
|
|||
0 0
|
||||
.names AVEC
|
||||
1
|
||||
.names cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF E
|
||||
110 1
|
||||
001 1
|
||||
.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_1_.BLIF E
|
||||
010 1
|
||||
101 1
|
||||
-00 0
|
||||
1-1 0
|
||||
01- 0
|
||||
0-1 0
|
||||
11- 0
|
||||
.names inst_VMA_INTreg.BLIF VMA
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -741,12 +738,6 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names IPL_030DFF_0_reg.BLIF IPL_030_0_
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_5_.C
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -765,12 +756,6 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF SM_AMIGA_0_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF cpu_est_2_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF cpu_est_3_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF IPL_030DFF_0_reg.C
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -789,28 +774,10 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF IPL_D0_2_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
|
||||
.names CLK_OSZI.BLIF SM_AMIGA_6_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
|
||||
|
|
@ -854,28 +821,10 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF cpu_est_1_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
|
||||
.names CLK_OSZI.BLIF cpu_est_2_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
|
||||
.names CLK_OSZI.BLIF cpu_est_3_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
|
||||
|
|
@ -939,7 +888,28 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF RST_DLY_0_.C
|
||||
.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF RST_DLY_1_.C
|
||||
|
|
@ -951,19 +921,31 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
|
||||
.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_RW_000_DMA.C
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_RW_000_INT.C
|
||||
.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
||||
.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF RST_DLY_0_.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_AS_000_DMA.C
|
||||
|
|
@ -999,12 +981,7 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF inst_RESET_OUT.C
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
|
||||
10 1
|
||||
01 1
|
||||
00 0
|
||||
11 0
|
||||
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_25.C
|
||||
.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF BG_000DFFreg.C
|
||||
|
|
@ -1025,24 +1002,24 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF inst_A0_DMA.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_RW_000_DMA.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_RW_000_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_LDS_000_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_CLK_000_NE.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_OUT_PRE_D.BLIF inst_CLK_OUT_INTreg.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_CLK_OUT_INTreg.C
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -1055,18 +1032,18 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_EXP_INT.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_CLK_OUT_EXP_INT.C
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D
|
||||
.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C
|
||||
1 1
|
||||
0 0
|
||||
.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF CLK_OUT_INTreg.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000.BLIF inst_CLK_000_D0.D
|
||||
1 1
|
||||
0 0
|
||||
|
|
@ -1079,6 +1056,12 @@ inst_AS_030_D0.BLIF CIIN
|
|||
.names CLK_OSZI.BLIF inst_CLK_000_PE.C
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
|
||||
1 1
|
||||
0 0
|
||||
.names CLK_OSZI.BLIF inst_CLK_000_NE.C
|
||||
1 1
|
||||
0 0
|
||||
.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_
|
||||
01 1
|
||||
1- 0
|
||||
|
|
@ -1223,13 +1206,13 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
|
|||
11 1
|
||||
0- 0
|
||||
-0 0
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
|
||||
cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
|
||||
.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
|
||||
cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
|
||||
inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
|
||||
BERR.PIN.BLIF SM_AMIGA_3_.D.X2
|
||||
1-------1-10- 1
|
||||
1----------10 1
|
||||
1000010--101- 1
|
||||
1001000--101- 1
|
||||
1-----10-101- 1
|
||||
0------------ 0
|
||||
--------0--0- 0
|
||||
|
|
@ -1238,8 +1221,8 @@ BERR.PIN.BLIF SM_AMIGA_3_.D.X2
|
|||
----------111 0
|
||||
-1----0----11 0
|
||||
--1---0----11 0
|
||||
---1--0----11 0
|
||||
---0--0----11 0
|
||||
----1-0----11 0
|
||||
-----00----11 0
|
||||
-----10----11 0
|
||||
------11---11 0
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
// Signal Name Cross Reference File
|
||||
// ispLEVER Classic 1.8.00.04.29.14
|
||||
|
||||
// Design '68030_tk' created Sun Jan 24 16:20:54 2016
|
||||
// Design '68030_tk' created Mon Jan 25 07:24:19 2016
|
||||
|
||||
|
||||
// LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
Copyright(C), 1992-2014, Lattice Semiconductor Corp.
|
||||
All Rights Reserved.
|
||||
|
||||
Design bus68030 created Sun Jan 24 16:20:54 2016
|
||||
Design bus68030 created Mon Jan 25 07:24:19 2016
|
||||
|
||||
|
||||
P-Terms Fan-in Fan-out Type Name (attributes)
|
||||
|
|
@ -21,16 +21,17 @@ Design bus68030 created Sun Jan 24 16:20:54 2016
|
|||
1 2 1 Pin LDS_000.OE
|
||||
0 0 1 Pin BERR
|
||||
1 9 1 Pin BERR.OE
|
||||
1 1 1 Pin CLK_EXP
|
||||
1 1 1 Pin CLK_DIV_OUT.D
|
||||
1 1 1 Pin CLK_DIV_OUT.C
|
||||
1 9 1 Pin FPU_CS-
|
||||
1 0 1 Pin AVEC
|
||||
2 3 1 Pin E
|
||||
0 0 1 Pin RESET
|
||||
1 1 1 Pin RESET.OE
|
||||
0 0 1 Pin AMIGA_ADDR_ENABLE
|
||||
2 4 1 Pin AMIGA_BUS_DATA_DIR
|
||||
1 2 1 Pin SIZE_0_
|
||||
1 2 1 Pin SIZE_0_.OE
|
||||
2 4 1 Pin AMIGA_BUS_DATA_DIR
|
||||
1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
|
||||
2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
|
||||
1 13 1 Pin CIIN
|
||||
|
|
@ -51,8 +52,8 @@ Design bus68030 created Sun Jan 24 16:20:54 2016
|
|||
1 1 1 Pin BG_000.C
|
||||
3 5 1 Pin BGACK_030.D
|
||||
1 1 1 Pin BGACK_030.C
|
||||
1 1 1 Pin CLK_DIV_OUT.D
|
||||
1 1 1 Pin CLK_DIV_OUT.C
|
||||
1 1 1 Pin CLK_EXP.D
|
||||
1 1 1 Pin CLK_EXP.C
|
||||
1 1 1 Pin DSACK1.OE
|
||||
4 9 1 Pin DSACK1.D-
|
||||
1 1 1 Pin DSACK1.C
|
||||
|
|
@ -61,14 +62,15 @@ Design bus68030 created Sun Jan 24 16:20:54 2016
|
|||
1 2 1 Pin RW.OE
|
||||
2 5 1 Pin RW.D-
|
||||
1 1 1 Pin RW.C
|
||||
2 2 1 Node cpu_est_0_.D
|
||||
1 1 1 Node cpu_est_0_.C
|
||||
3 4 1 Node cpu_est_1_.D
|
||||
1 1 1 Node cpu_est_1_.C
|
||||
4 11 1 Node N_317_i-
|
||||
4 4 1 Node cpu_est_2_.D
|
||||
1 1 1 Node cpu_est_2_.C
|
||||
3 5 1 Node cpu_est_3_.D
|
||||
1 1 1 Node cpu_est_3_.C
|
||||
2 2 1 Node cpu_est_0_.D
|
||||
1 1 1 Node cpu_est_0_.C
|
||||
3 4 1 Node cpu_est_1_.D
|
||||
1 1 1 Node cpu_est_1_.C
|
||||
2 5 1 Node inst_AS_000_INT.D-
|
||||
1 1 1 Node inst_AS_000_INT.C
|
||||
3 6 1 Node SM_AMIGA_5_.D
|
||||
|
|
@ -109,17 +111,12 @@ Design bus68030 created Sun Jan 24 16:20:54 2016
|
|||
1 1 1 Node inst_RESET_OUT.C
|
||||
1 1 1 Node inst_CLK_OUT_PRE_50.D
|
||||
1 1 1 Node inst_CLK_OUT_PRE_50.C
|
||||
4 11 1 Node N_210_i-
|
||||
2 2 1 Node inst_CLK_OUT_PRE_25.D
|
||||
1 1 1 Node inst_CLK_OUT_PRE_25.C
|
||||
1 1 1 Node inst_CLK_000_D1.D
|
||||
1 1 1 Node inst_CLK_000_D1.C
|
||||
1 1 1 Node inst_CLK_000_D0.D
|
||||
1 1 1 Node inst_CLK_000_D0.C
|
||||
1 1 1 Node inst_CLK_000_PE.D
|
||||
1 1 1 Node inst_CLK_000_PE.C
|
||||
1 1 1 Node inst_CLK_OUT_EXP_INT.D
|
||||
1 1 1 Node inst_CLK_OUT_EXP_INT.C
|
||||
1 1 1 Node CLK_000_P_SYNC_9_.D
|
||||
1 1 1 Node CLK_000_P_SYNC_9_.C
|
||||
1 1 1 Node inst_CLK_000_NE.D
|
||||
|
|
@ -202,9 +199,9 @@ Design bus68030 created Sun Jan 24 16:20:54 2016
|
|||
1 1 1 Node SM_AMIGA_i_7_.C
|
||||
2 14 1 Node CIIN_0
|
||||
=========
|
||||
327 P-Term Total: 327
|
||||
323 P-Term Total: 323
|
||||
Total Pins: 61
|
||||
Total Nodes: 71
|
||||
Total Nodes: 69
|
||||
Average P-Term/Output: 2
|
||||
|
||||
|
||||
|
|
@ -238,14 +235,16 @@ BERR = (0);
|
|||
|
||||
BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
|
||||
|
||||
CLK_EXP = (!inst_CLK_OUT_EXP_INT.Q);
|
||||
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
|
||||
|
||||
CLK_DIV_OUT.C = (CLK_OSZI);
|
||||
|
||||
!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
|
||||
|
||||
AVEC = (1);
|
||||
|
||||
E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q
|
||||
# cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q);
|
||||
E = (cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_1_.Q
|
||||
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_1_.Q);
|
||||
|
||||
RESET = (0);
|
||||
|
||||
|
|
@ -253,13 +252,13 @@ RESET.OE = (!inst_RESET_OUT.Q);
|
|||
|
||||
AMIGA_ADDR_ENABLE = (0);
|
||||
|
||||
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
|
||||
# !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
|
||||
|
||||
SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
|
||||
|
||||
SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
|
||||
|
||||
AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
|
||||
# !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
|
||||
|
||||
!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
|
||||
|
||||
AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
|
||||
|
|
@ -335,9 +334,9 @@ BGACK_030.D = (!RST
|
|||
|
||||
BGACK_030.C = (CLK_OSZI);
|
||||
|
||||
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
|
||||
CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q);
|
||||
|
||||
CLK_DIV_OUT.C = (CLK_OSZI);
|
||||
CLK_EXP.C = (CLK_OSZI);
|
||||
|
||||
DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
|
||||
|
||||
|
|
@ -349,8 +348,8 @@ DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
|
|||
DSACK1.C = (CLK_OSZI);
|
||||
|
||||
VMA.T = (!RST & !VMA.Q
|
||||
# !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & inst_CLK_000_PE.Q
|
||||
# RST & VMA.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q);
|
||||
# !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_PE.Q
|
||||
# RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q);
|
||||
|
||||
VMA.C = (CLK_OSZI);
|
||||
|
||||
|
|
@ -361,6 +360,24 @@ RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
|
|||
|
||||
RW.C = (CLK_OSZI);
|
||||
|
||||
!N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
|
||||
|
||||
cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q
|
||||
# cpu_est_2_.Q & !cpu_est_1_.Q
|
||||
# cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
|
||||
# !cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_2_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_3_.D = (cpu_est_3_.Q & !inst_CLK_000_NE_D0.Q
|
||||
# !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q
|
||||
# cpu_est_2_.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_3_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
|
||||
# cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
|
||||
|
||||
|
|
@ -368,23 +385,10 @@ cpu_est_0_.C = (CLK_OSZI);
|
|||
|
||||
cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
|
||||
# cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
|
||||
# cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & inst_CLK_000_NE_D0.Q);
|
||||
# !cpu_est_3_.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_1_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_2_.D = (!cpu_est_0_.Q & cpu_est_2_.Q
|
||||
# !cpu_est_1_.Q & cpu_est_2_.Q
|
||||
# cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
|
||||
# cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_2_.C = (CLK_OSZI);
|
||||
|
||||
cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q
|
||||
# cpu_est_3_.Q & !inst_CLK_000_NE_D0.Q
|
||||
# cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
|
||||
|
||||
cpu_est_3_.C = (CLK_OSZI);
|
||||
|
||||
!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q
|
||||
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
|
||||
|
||||
|
|
@ -483,7 +487,7 @@ inst_LDS_000_INT.D = (!RST
|
|||
|
||||
inst_LDS_000_INT.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q);
|
||||
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
|
||||
|
||||
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
|
||||
|
||||
|
|
@ -500,16 +504,6 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
|
|||
|
||||
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
|
||||
|
||||
!N_210_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
|
||||
|
||||
inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
|
||||
# inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
|
||||
|
||||
inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
|
||||
|
||||
inst_CLK_000_D1.C = (CLK_OSZI);
|
||||
|
|
@ -522,10 +516,6 @@ inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
|
|||
|
||||
inst_CLK_000_PE.C = (CLK_OSZI);
|
||||
|
||||
inst_CLK_OUT_EXP_INT.D = (inst_CLK_OUT_PRE_50.Q);
|
||||
|
||||
inst_CLK_OUT_EXP_INT.C = (CLK_OSZI);
|
||||
|
||||
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
|
||||
|
||||
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
|
||||
|
|
@ -703,31 +693,31 @@ SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
|
|||
# SM_AMIGA_3_.Q & !BERR.PIN
|
||||
# RST & inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
|
||||
# inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q
|
||||
# !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q);
|
||||
# !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q);
|
||||
|
||||
SM_AMIGA_3_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
|
||||
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q);
|
||||
# RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q);
|
||||
|
||||
SM_AMIGA_2_.C = (CLK_OSZI);
|
||||
|
||||
SM_AMIGA_i_7_.D = (RST & N_210_i & !inst_CLK_000_PE.Q & BERR.PIN
|
||||
# RST & N_210_i & !SM_AMIGA_0_.Q & BERR.PIN
|
||||
# RST & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & N_210_i & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
|
||||
# RST & N_210_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & N_210_i & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
|
||||
SM_AMIGA_i_7_.D = (RST & N_317_i & !inst_CLK_000_PE.Q & BERR.PIN
|
||||
# RST & N_317_i & !SM_AMIGA_0_.Q & BERR.PIN
|
||||
# RST & N_317_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q
|
||||
# RST & N_317_i & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q
|
||||
# RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
|
||||
# RST & N_317_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
|
||||
# RST & N_317_i & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
|
||||
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
|
||||
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
|
||||
# RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
|
||||
|
||||
SM_AMIGA_i_7_.C = (CLK_OSZI);
|
||||
|
||||
|
|
|
|||
|
|
@ -34,36 +34,36 @@ DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030}
|
|||
DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000}
|
||||
DATA LOCATION BG_030:C_*_21 // INP
|
||||
DATA LOCATION CIIN:E_12_47 // OUT
|
||||
DATA LOCATION CIIN_0:E_9 // NOD
|
||||
DATA LOCATION CIIN_0:E_5 // NOD
|
||||
DATA LOCATION CLK_000:*_*_11 // INP
|
||||
DATA LOCATION CLK_000_N_SYNC_0_:G_11 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_0_:E_9 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_1_:F_2 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_2_:F_13 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_3_:D_15 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_4_:D_11 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_5_:A_14 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_6_:A_10 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_7_:G_7 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_8_:B_2 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_9_:D_7 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_0_:B_3 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_1_:B_14 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_2_:F_14 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_3_:F_10 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_4_:E_13 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_5_:B_10 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_6_:F_6 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_7_:B_6 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_8_:G_15 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_9_:F_3 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_1_:A_14 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_2_:B_14 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_3_:B_10 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_4_:B_6 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_5_:D_11 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_6_:G_6 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_7_:F_3 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_8_:A_10 // NOD
|
||||
DATA LOCATION CLK_000_N_SYNC_9_:A_6 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_0_:E_2 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_1_:B_7 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_2_:G_7 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_3_:E_13 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_4_:G_3 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_5_:G_14 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_6_:A_3 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_7_:B_3 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_8_:G_10 // NOD
|
||||
DATA LOCATION CLK_000_P_SYNC_9_:G_15 // NOD
|
||||
DATA LOCATION CLK_030:*_*_64 // INP
|
||||
DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT
|
||||
DATA LOCATION CLK_EXP:B_0_10 // OUT
|
||||
DATA LOCATION CLK_OSZI:*_*_61 // Cin
|
||||
DATA LOCATION CYCLE_DMA_0_:A_6 // NOD
|
||||
DATA LOCATION CYCLE_DMA_1_:A_2 // NOD
|
||||
DATA LOCATION CYCLE_DMA_0_:B_5 // NOD
|
||||
DATA LOCATION CYCLE_DMA_1_:C_12 // NOD
|
||||
DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1}
|
||||
DATA LOCATION DS_030:A_0_98 // OUT
|
||||
DATA LOCATION DTACK:D_*_30 // INP
|
||||
|
|
@ -78,11 +78,11 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_}
|
|||
DATA LOCATION IPL_0_:G_*_67 // INP
|
||||
DATA LOCATION IPL_1_:F_*_56 // INP
|
||||
DATA LOCATION IPL_2_:G_*_68 // INP
|
||||
DATA LOCATION IPL_D0_0_:B_15 // NOD
|
||||
DATA LOCATION IPL_D0_1_:B_11 // NOD
|
||||
DATA LOCATION IPL_D0_2_:B_7 // NOD
|
||||
DATA LOCATION IPL_D0_0_:G_11 // NOD
|
||||
DATA LOCATION IPL_D0_1_:D_15 // NOD
|
||||
DATA LOCATION IPL_D0_2_:B_11 // NOD
|
||||
DATA LOCATION LDS_000:D_12_31 // IO
|
||||
DATA LOCATION N_210_i:C_9 // NOD
|
||||
DATA LOCATION N_317_i:F_14 // NOD
|
||||
DATA LOCATION RESET:B_1_3 // OUT
|
||||
DATA LOCATION RN_A0:G_8 // NOD {A0}
|
||||
DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030}
|
||||
|
|
@ -95,55 +95,53 @@ DATA LOCATION RN_RW:G_0 // NOD {RW}
|
|||
DATA LOCATION RN_RW_000:H_0 // NOD {RW_000}
|
||||
DATA LOCATION RN_VMA:D_0 // NOD {VMA}
|
||||
DATA LOCATION RST:*_*_86 // INP
|
||||
DATA LOCATION RST_DLY_0_:G_14 // NOD
|
||||
DATA LOCATION RST_DLY_1_:G_10 // NOD
|
||||
DATA LOCATION RST_DLY_2_:G_3 // NOD
|
||||
DATA LOCATION RST_DLY_0_:D_3 // NOD
|
||||
DATA LOCATION RST_DLY_1_:D_14 // NOD
|
||||
DATA LOCATION RST_DLY_2_:D_7 // NOD
|
||||
DATA LOCATION RW:G_0_71 // IO {RN_RW}
|
||||
DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000}
|
||||
DATA LOCATION SIZE_0_:G_12_70 // IO
|
||||
DATA LOCATION SIZE_1_:H_12_79 // IO
|
||||
DATA LOCATION SIZE_DMA_0_:G_2 // NOD
|
||||
DATA LOCATION SIZE_DMA_1_:G_13 // NOD
|
||||
DATA LOCATION SIZE_DMA_0_:G_13 // NOD
|
||||
DATA LOCATION SIZE_DMA_1_:G_9 // NOD
|
||||
DATA LOCATION SM_AMIGA_0_:F_1 // NOD
|
||||
DATA LOCATION SM_AMIGA_1_:A_8 // NOD
|
||||
DATA LOCATION SM_AMIGA_2_:F_12 // NOD
|
||||
DATA LOCATION SM_AMIGA_3_:F_5 // NOD
|
||||
DATA LOCATION SM_AMIGA_1_:F_5 // NOD
|
||||
DATA LOCATION SM_AMIGA_2_:F_10 // NOD
|
||||
DATA LOCATION SM_AMIGA_3_:F_6 // NOD
|
||||
DATA LOCATION SM_AMIGA_4_:F_9 // NOD
|
||||
DATA LOCATION SM_AMIGA_5_:F_4 // NOD
|
||||
DATA LOCATION SM_AMIGA_6_:C_4 // NOD
|
||||
DATA LOCATION SM_AMIGA_i_7_:F_8 // NOD
|
||||
DATA LOCATION SM_AMIGA_5_:F_8 // NOD
|
||||
DATA LOCATION SM_AMIGA_6_:F_4 // NOD
|
||||
DATA LOCATION SM_AMIGA_i_7_:F_0 // NOD
|
||||
DATA LOCATION UDS_000:D_8_32 // IO
|
||||
DATA LOCATION VMA:D_0_35 // IO {RN_VMA}
|
||||
DATA LOCATION VPA:*_*_36 // INP
|
||||
DATA LOCATION cpu_est_0_:D_10 // NOD
|
||||
DATA LOCATION cpu_est_1_:D_6 // NOD
|
||||
DATA LOCATION cpu_est_0_:D_6 // NOD
|
||||
DATA LOCATION cpu_est_1_:D_2 // NOD
|
||||
DATA LOCATION cpu_est_2_:D_13 // NOD
|
||||
DATA LOCATION cpu_est_3_:D_2 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:B_5 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_9 // NOD
|
||||
DATA LOCATION inst_AS_000_DMA:A_12 // NOD
|
||||
DATA LOCATION inst_AS_000_INT:B_13 // NOD
|
||||
DATA LOCATION inst_AS_030_000_SYNC:C_5 // NOD
|
||||
DATA LOCATION inst_AS_030_D0:H_13 // NOD
|
||||
DATA LOCATION inst_BGACK_030_INT_D:E_8 // NOD
|
||||
DATA LOCATION inst_CLK_000_D0:D_9 // NOD
|
||||
DATA LOCATION inst_CLK_000_D1:C_8 // NOD
|
||||
DATA LOCATION inst_CLK_000_NE:G_9 // NOD
|
||||
DATA LOCATION inst_CLK_000_NE_D0:D_14 // NOD
|
||||
DATA LOCATION inst_CLK_000_PE:F_0 // NOD
|
||||
DATA LOCATION inst_CLK_030_H:A_13 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_EXP_INT:E_2 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_25:G_6 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_50:E_5 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_D:D_3 // NOD
|
||||
DATA LOCATION inst_DS_000_DMA:A_9 // NOD
|
||||
DATA LOCATION inst_DS_000_ENABLE:C_12 // NOD
|
||||
DATA LOCATION inst_DTACK_D0:A_3 // NOD
|
||||
DATA LOCATION inst_LDS_000_INT:A_1 // NOD
|
||||
DATA LOCATION inst_RESET_OUT:G_5 // NOD
|
||||
DATA LOCATION inst_UDS_000_INT:A_5 // NOD
|
||||
DATA LOCATION inst_VPA_D:C_1 // NOD
|
||||
DATA LOCATION inst_nEXP_SPACE_D0reg:H_5 // NOD
|
||||
DATA LOCATION cpu_est_3_:F_12 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:B_13 // NOD
|
||||
DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_2 // NOD
|
||||
DATA LOCATION inst_AS_000_DMA:A_1 // NOD
|
||||
DATA LOCATION inst_AS_000_INT:C_1 // NOD
|
||||
DATA LOCATION inst_AS_030_000_SYNC:C_4 // NOD
|
||||
DATA LOCATION inst_AS_030_D0:H_3 // NOD
|
||||
DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD
|
||||
DATA LOCATION inst_CLK_000_D0:B_9 // NOD
|
||||
DATA LOCATION inst_CLK_000_D1:E_8 // NOD
|
||||
DATA LOCATION inst_CLK_000_NE:G_2 // NOD
|
||||
DATA LOCATION inst_CLK_000_NE_D0:D_10 // NOD
|
||||
DATA LOCATION inst_CLK_000_PE:G_5 // NOD
|
||||
DATA LOCATION inst_CLK_030_H:A_2 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_50:F_13 // NOD
|
||||
DATA LOCATION inst_CLK_OUT_PRE_D:A_12 // NOD
|
||||
DATA LOCATION inst_DS_000_DMA:A_13 // NOD
|
||||
DATA LOCATION inst_DS_000_ENABLE:C_8 // NOD
|
||||
DATA LOCATION inst_DTACK_D0:B_15 // NOD
|
||||
DATA LOCATION inst_LDS_000_INT:A_5 // NOD
|
||||
DATA LOCATION inst_RESET_OUT:D_9 // NOD
|
||||
DATA LOCATION inst_UDS_000_INT:A_9 // NOD
|
||||
DATA LOCATION inst_VPA_D:F_2 // NOD
|
||||
DATA LOCATION inst_nEXP_SPACE_D0reg:A_8 // NOD
|
||||
DATA LOCATION nEXP_SPACE:*_*_14 // INP
|
||||
DATA IO_DIR A0:BI
|
||||
DATA IO_DIR A1:IN
|
||||
|
|
@ -213,18 +211,18 @@ DATA PW_LEVEL A_31_:1
|
|||
DATA SLEW A_31_:1
|
||||
DATA PW_LEVEL IPL_2_:1
|
||||
DATA SLEW IPL_2_:1
|
||||
DATA PW_LEVEL FC_1_:1
|
||||
DATA SLEW FC_1_:1
|
||||
DATA PW_LEVEL IPL_1_:1
|
||||
DATA SLEW IPL_1_:1
|
||||
DATA PW_LEVEL AS_030:1
|
||||
DATA SLEW AS_030:1
|
||||
DATA PW_LEVEL FC_1_:1
|
||||
DATA SLEW FC_1_:1
|
||||
DATA PW_LEVEL IPL_0_:1
|
||||
DATA SLEW IPL_0_:1
|
||||
DATA PW_LEVEL AS_000:1
|
||||
DATA SLEW AS_000:1
|
||||
DATA PW_LEVEL AS_030:1
|
||||
DATA SLEW AS_030:1
|
||||
DATA PW_LEVEL FC_0_:1
|
||||
DATA SLEW FC_0_:1
|
||||
DATA PW_LEVEL AS_000:1
|
||||
DATA SLEW AS_000:1
|
||||
DATA PW_LEVEL DS_030:1
|
||||
DATA SLEW DS_030:1
|
||||
DATA PW_LEVEL UDS_000:1
|
||||
|
|
@ -243,8 +241,8 @@ DATA SLEW BGACK_000:1
|
|||
DATA SLEW CLK_030:1
|
||||
DATA SLEW CLK_000:1
|
||||
DATA SLEW CLK_OSZI:1
|
||||
DATA PW_LEVEL CLK_EXP:1
|
||||
DATA SLEW CLK_EXP:0
|
||||
DATA PW_LEVEL CLK_DIV_OUT:1
|
||||
DATA SLEW CLK_DIV_OUT:0
|
||||
DATA PW_LEVEL FPU_CS:1
|
||||
DATA SLEW FPU_CS:0
|
||||
DATA PW_LEVEL FPU_SENSE:1
|
||||
|
|
@ -261,22 +259,22 @@ DATA PW_LEVEL RESET:1
|
|||
DATA SLEW RESET:1
|
||||
DATA PW_LEVEL AMIGA_ADDR_ENABLE:1
|
||||
DATA SLEW AMIGA_ADDR_ENABLE:0
|
||||
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
|
||||
DATA SLEW AMIGA_BUS_DATA_DIR:0
|
||||
DATA PW_LEVEL SIZE_0_:1
|
||||
DATA SLEW SIZE_0_:1
|
||||
DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1
|
||||
DATA SLEW AMIGA_BUS_ENABLE_LOW:0
|
||||
DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1
|
||||
DATA SLEW AMIGA_BUS_DATA_DIR:0
|
||||
DATA PW_LEVEL A_30_:1
|
||||
DATA SLEW A_30_:1
|
||||
DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
|
||||
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
|
||||
DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1
|
||||
DATA SLEW AMIGA_BUS_ENABLE_LOW:0
|
||||
DATA PW_LEVEL A_29_:1
|
||||
DATA SLEW A_29_:1
|
||||
DATA PW_LEVEL CIIN:1
|
||||
DATA SLEW CIIN:1
|
||||
DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1
|
||||
DATA SLEW AMIGA_BUS_ENABLE_HIGH:0
|
||||
DATA PW_LEVEL A_28_:1
|
||||
DATA SLEW A_28_:1
|
||||
DATA PW_LEVEL CIIN:1
|
||||
DATA SLEW CIIN:1
|
||||
DATA PW_LEVEL A_27_:1
|
||||
DATA SLEW A_27_:1
|
||||
DATA PW_LEVEL A_26_:1
|
||||
|
|
@ -315,22 +313,24 @@ DATA PW_LEVEL BG_000:1
|
|||
DATA SLEW BG_000:1
|
||||
DATA PW_LEVEL BGACK_030:1
|
||||
DATA SLEW BGACK_030:1
|
||||
DATA PW_LEVEL CLK_DIV_OUT:1
|
||||
DATA SLEW CLK_DIV_OUT:0
|
||||
DATA PW_LEVEL CLK_EXP:1
|
||||
DATA SLEW CLK_EXP:0
|
||||
DATA PW_LEVEL DSACK1:1
|
||||
DATA SLEW DSACK1:1
|
||||
DATA PW_LEVEL VMA:1
|
||||
DATA SLEW VMA:1
|
||||
DATA PW_LEVEL RW:1
|
||||
DATA SLEW RW:1
|
||||
DATA PW_LEVEL cpu_est_0_:1
|
||||
DATA SLEW cpu_est_0_:1
|
||||
DATA PW_LEVEL cpu_est_1_:1
|
||||
DATA SLEW cpu_est_1_:1
|
||||
DATA PW_LEVEL N_317_i:1
|
||||
DATA SLEW N_317_i:1
|
||||
DATA PW_LEVEL cpu_est_2_:1
|
||||
DATA SLEW cpu_est_2_:1
|
||||
DATA PW_LEVEL cpu_est_3_:1
|
||||
DATA SLEW cpu_est_3_:1
|
||||
DATA PW_LEVEL cpu_est_0_:1
|
||||
DATA SLEW cpu_est_0_:1
|
||||
DATA PW_LEVEL cpu_est_1_:1
|
||||
DATA SLEW cpu_est_1_:1
|
||||
DATA PW_LEVEL inst_AS_000_INT:1
|
||||
DATA SLEW inst_AS_000_INT:1
|
||||
DATA PW_LEVEL SM_AMIGA_5_:1
|
||||
|
|
@ -371,18 +371,12 @@ DATA PW_LEVEL inst_RESET_OUT:1
|
|||
DATA SLEW inst_RESET_OUT:1
|
||||
DATA PW_LEVEL inst_CLK_OUT_PRE_50:1
|
||||
DATA SLEW inst_CLK_OUT_PRE_50:1
|
||||
DATA PW_LEVEL N_210_i:1
|
||||
DATA SLEW N_210_i:1
|
||||
DATA PW_LEVEL inst_CLK_OUT_PRE_25:1
|
||||
DATA SLEW inst_CLK_OUT_PRE_25:1
|
||||
DATA PW_LEVEL inst_CLK_000_D1:1
|
||||
DATA SLEW inst_CLK_000_D1:1
|
||||
DATA PW_LEVEL inst_CLK_000_D0:1
|
||||
DATA SLEW inst_CLK_000_D0:1
|
||||
DATA PW_LEVEL inst_CLK_000_PE:1
|
||||
DATA SLEW inst_CLK_000_PE:1
|
||||
DATA PW_LEVEL inst_CLK_OUT_EXP_INT:1
|
||||
DATA SLEW inst_CLK_OUT_EXP_INT:1
|
||||
DATA PW_LEVEL CLK_000_P_SYNC_9_:1
|
||||
DATA SLEW CLK_000_P_SYNC_9_:1
|
||||
DATA PW_LEVEL inst_CLK_000_NE:1
|
||||
|
|
|
|||
|
|
@ -1,27 +1,28 @@
|
|||
|
||||
GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT
|
||||
SM_AMIGA_1_ CYCLE_DMA_1_ CYCLE_DMA_0_ inst_UDS_000_INT inst_DTACK_D0
|
||||
CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ DS_030 AVEC
|
||||
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
|
||||
RN_IPL_030_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
CLK_000_P_SYNC_0_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_P_SYNC_1_
|
||||
CLK_000_P_SYNC_5_ CLK_000_P_SYNC_7_ CLK_000_N_SYNC_8_ CLK_EXP RESET
|
||||
inst_UDS_000_INT inst_nEXP_SPACE_D0reg CLK_000_P_SYNC_6_ CLK_000_N_SYNC_1_
|
||||
CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ inst_CLK_OUT_PRE_D DS_030 AVEC
|
||||
|
||||
GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_DS_000_ENABLE SM_AMIGA_6_ inst_VPA_D
|
||||
inst_CLK_000_D1 AMIGA_BUS_ENABLE_LOW N_210_i
|
||||
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 cpu_est_3_ cpu_est_1_ cpu_est_2_
|
||||
cpu_est_0_ inst_CLK_000_D0 CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_9_
|
||||
inst_CLK_OUT_PRE_D inst_CLK_000_NE_D0 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH
|
||||
GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
|
||||
RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
CYCLE_DMA_0_ inst_DTACK_D0 IPL_D0_2_ inst_CLK_000_D0 CLK_000_P_SYNC_1_
|
||||
CLK_000_P_SYNC_7_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_
|
||||
RESET
|
||||
GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_DS_000_ENABLE CYCLE_DMA_1_ inst_AS_000_INT
|
||||
AMIGA_BUS_ENABLE_LOW
|
||||
GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_RESET_OUT RST_DLY_0_
|
||||
RST_DLY_1_ RST_DLY_2_ cpu_est_2_ cpu_est_1_ cpu_est_0_ IPL_D0_1_
|
||||
CLK_000_N_SYNC_5_ inst_CLK_000_NE_D0 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH
|
||||
AMIGA_ADDR_ENABLE
|
||||
GROUP MACH_SEG_E inst_BGACK_030_INT_D CLK_000_P_SYNC_4_ inst_CLK_OUT_PRE_50
|
||||
inst_CLK_OUT_EXP_INT CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
|
||||
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_4_
|
||||
SM_AMIGA_5_ inst_CLK_000_PE CLK_000_P_SYNC_9_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_
|
||||
CLK_000_P_SYNC_6_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_
|
||||
GROUP MACH_SEG_G A0 RN_A0 RW RN_RW CLK_DIV_OUT inst_RESET_OUT SIZE_DMA_0_
|
||||
SIZE_DMA_1_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_OUT_PRE_25
|
||||
CLK_000_N_SYNC_0_ inst_CLK_000_NE CLK_000_P_SYNC_8_ CLK_000_N_SYNC_7_
|
||||
GROUP MACH_SEG_E CLK_000_P_SYNC_0_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_3_
|
||||
inst_CLK_000_D1 CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0
|
||||
GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_6_ SM_AMIGA_1_
|
||||
SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ inst_VPA_D CLK_000_N_SYNC_7_
|
||||
inst_CLK_OUT_PRE_50 N_317_i
|
||||
GROUP MACH_SEG_G A0 RN_A0 RW RN_RW CLK_DIV_OUT SIZE_DMA_0_ SIZE_DMA_1_
|
||||
IPL_D0_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_P_SYNC_2_
|
||||
CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_6_
|
||||
SIZE_0_ E
|
||||
GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030
|
||||
inst_nEXP_SPACE_D0reg inst_AS_030_D0 CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_
|
||||
inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_
|
||||
FPU_CS AS_030 SIZE_1_
|
||||
|
|
@ -1,2 +1 @@
|
|||
<LATTICE_ENCRYPTED_BLIF>44:;035:/
|
||||
i ,
|
||||
<LATTICE_ENCRYPTED_BLIF>9420425ah[j@bK
|
||||
1029
Logic/68030_tk.jed
1029
Logic/68030_tk.jed
File diff suppressed because it is too large
Load Diff
|
|
@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
|
|||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
DATE = 1/24/16;
|
||||
TIME = 16:20:59;
|
||||
DATE = 1/25/16;
|
||||
TIME = 07:24:24;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
|
@ -79,12 +79,12 @@ Layer = OFF;
|
|||
SIZE_1_ = pin,79,-,H,-;
|
||||
A_31_ = pin,4,-,B,-;
|
||||
IPL_2_ = pin,68,-,G,-;
|
||||
FC_1_ = pin,58,-,F,-;
|
||||
IPL_1_ = pin,56,-,F,-;
|
||||
AS_030 = pin,82,-,H,-;
|
||||
FC_1_ = pin,58,-,F,-;
|
||||
IPL_0_ = pin,67,-,G,-;
|
||||
AS_000 = pin,42,-,E,-;
|
||||
AS_030 = pin,82,-,H,-;
|
||||
FC_0_ = pin,57,-,F,-;
|
||||
AS_000 = pin,42,-,E,-;
|
||||
DS_030 = pin,98,-,A,-;
|
||||
UDS_000 = pin,32,-,D,-;
|
||||
LDS_000 = pin,31,-,D,-;
|
||||
|
|
@ -96,7 +96,7 @@ BGACK_000 = pin,28,-,D,-;
|
|||
CLK_030 = pin,64,-,-,-;
|
||||
CLK_000 = pin,11,-,-,-;
|
||||
CLK_OSZI = pin,61,-,-,-;
|
||||
CLK_EXP = pin,10,-,B,-;
|
||||
CLK_DIV_OUT = pin,65,-,G,-;
|
||||
FPU_CS = pin,78,-,H,-;
|
||||
FPU_SENSE = pin,91,-,A,-;
|
||||
DTACK = pin,30,-,D,-;
|
||||
|
|
@ -106,14 +106,14 @@ VPA = pin,36,-,-,-;
|
|||
RST = pin,86,-,-,-;
|
||||
RESET = pin,3,-,B,-;
|
||||
AMIGA_ADDR_ENABLE = pin,33,-,D,-;
|
||||
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
|
||||
SIZE_0_ = pin,70,-,G,-;
|
||||
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
|
||||
AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
|
||||
A_30_ = pin,5,-,B,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
|
||||
AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
|
||||
A_29_ = pin,6,-,B,-;
|
||||
CIIN = pin,47,-,E,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
|
||||
A_28_ = pin,15,-,C,-;
|
||||
CIIN = pin,47,-,E,-;
|
||||
A_27_ = pin,16,-,C,-;
|
||||
A_26_ = pin,17,-,C,-;
|
||||
A_25_ = pin,18,-,C,-;
|
||||
|
|
@ -133,81 +133,79 @@ RW_000 = pin,80,-,H,-;
|
|||
A0 = pin,69,-,G,-;
|
||||
BG_000 = pin,29,-,D,-;
|
||||
BGACK_030 = pin,83,-,H,-;
|
||||
CLK_DIV_OUT = pin,65,-,G,-;
|
||||
CLK_EXP = pin,10,-,B,-;
|
||||
DSACK1 = pin,81,-,H,-;
|
||||
VMA = pin,35,-,D,-;
|
||||
RW = pin,71,-,G,-;
|
||||
cpu_est_0_ = node,-,-,D,10;
|
||||
cpu_est_1_ = node,-,-,D,6;
|
||||
N_317_i = node,-,-,F,14;
|
||||
cpu_est_2_ = node,-,-,D,13;
|
||||
cpu_est_3_ = node,-,-,D,2;
|
||||
inst_AS_000_INT = node,-,-,B,13;
|
||||
SM_AMIGA_5_ = node,-,-,F,4;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,9;
|
||||
inst_AS_030_D0 = node,-,-,H,13;
|
||||
inst_nEXP_SPACE_D0reg = node,-,-,H,5;
|
||||
inst_AS_030_000_SYNC = node,-,-,C,5;
|
||||
inst_BGACK_030_INT_D = node,-,-,E,8;
|
||||
inst_AS_000_DMA = node,-,-,A,12;
|
||||
inst_DS_000_DMA = node,-,-,A,9;
|
||||
CYCLE_DMA_0_ = node,-,-,A,6;
|
||||
CYCLE_DMA_1_ = node,-,-,A,2;
|
||||
SIZE_DMA_0_ = node,-,-,G,2;
|
||||
SIZE_DMA_1_ = node,-,-,G,13;
|
||||
inst_VPA_D = node,-,-,C,1;
|
||||
inst_UDS_000_INT = node,-,-,A,5;
|
||||
inst_LDS_000_INT = node,-,-,A,1;
|
||||
inst_CLK_OUT_PRE_D = node,-,-,D,3;
|
||||
inst_DTACK_D0 = node,-,-,A,3;
|
||||
inst_RESET_OUT = node,-,-,G,5;
|
||||
inst_CLK_OUT_PRE_50 = node,-,-,E,5;
|
||||
N_210_i = node,-,-,C,9;
|
||||
inst_CLK_OUT_PRE_25 = node,-,-,G,6;
|
||||
inst_CLK_000_D1 = node,-,-,C,8;
|
||||
inst_CLK_000_D0 = node,-,-,D,9;
|
||||
inst_CLK_000_PE = node,-,-,F,0;
|
||||
inst_CLK_OUT_EXP_INT = node,-,-,E,2;
|
||||
CLK_000_P_SYNC_9_ = node,-,-,F,3;
|
||||
inst_CLK_000_NE = node,-,-,G,9;
|
||||
cpu_est_3_ = node,-,-,F,12;
|
||||
cpu_est_0_ = node,-,-,D,6;
|
||||
cpu_est_1_ = node,-,-,D,2;
|
||||
inst_AS_000_INT = node,-,-,C,1;
|
||||
SM_AMIGA_5_ = node,-,-,F,8;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,2;
|
||||
inst_AS_030_D0 = node,-,-,H,3;
|
||||
inst_nEXP_SPACE_D0reg = node,-,-,A,8;
|
||||
inst_AS_030_000_SYNC = node,-,-,C,4;
|
||||
inst_BGACK_030_INT_D = node,-,-,H,13;
|
||||
inst_AS_000_DMA = node,-,-,A,1;
|
||||
inst_DS_000_DMA = node,-,-,A,13;
|
||||
CYCLE_DMA_0_ = node,-,-,B,5;
|
||||
CYCLE_DMA_1_ = node,-,-,C,12;
|
||||
SIZE_DMA_0_ = node,-,-,G,13;
|
||||
SIZE_DMA_1_ = node,-,-,G,9;
|
||||
inst_VPA_D = node,-,-,F,2;
|
||||
inst_UDS_000_INT = node,-,-,A,9;
|
||||
inst_LDS_000_INT = node,-,-,A,5;
|
||||
inst_CLK_OUT_PRE_D = node,-,-,A,12;
|
||||
inst_DTACK_D0 = node,-,-,B,15;
|
||||
inst_RESET_OUT = node,-,-,D,9;
|
||||
inst_CLK_OUT_PRE_50 = node,-,-,F,13;
|
||||
inst_CLK_000_D1 = node,-,-,E,8;
|
||||
inst_CLK_000_D0 = node,-,-,B,9;
|
||||
inst_CLK_000_PE = node,-,-,G,5;
|
||||
CLK_000_P_SYNC_9_ = node,-,-,G,15;
|
||||
inst_CLK_000_NE = node,-,-,G,2;
|
||||
CLK_000_N_SYNC_11_ = node,-,-,H,6;
|
||||
IPL_D0_0_ = node,-,-,B,15;
|
||||
IPL_D0_1_ = node,-,-,B,11;
|
||||
IPL_D0_2_ = node,-,-,B,7;
|
||||
inst_CLK_000_NE_D0 = node,-,-,D,14;
|
||||
IPL_D0_0_ = node,-,-,G,11;
|
||||
IPL_D0_1_ = node,-,-,D,15;
|
||||
IPL_D0_2_ = node,-,-,B,11;
|
||||
inst_CLK_000_NE_D0 = node,-,-,D,10;
|
||||
SM_AMIGA_0_ = node,-,-,F,1;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,B,5;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,B,13;
|
||||
SM_AMIGA_4_ = node,-,-,F,9;
|
||||
inst_DS_000_ENABLE = node,-,-,C,12;
|
||||
RST_DLY_0_ = node,-,-,G,14;
|
||||
RST_DLY_1_ = node,-,-,G,10;
|
||||
RST_DLY_2_ = node,-,-,G,3;
|
||||
CLK_000_P_SYNC_0_ = node,-,-,B,3;
|
||||
CLK_000_P_SYNC_1_ = node,-,-,B,14;
|
||||
CLK_000_P_SYNC_2_ = node,-,-,F,14;
|
||||
CLK_000_P_SYNC_3_ = node,-,-,F,10;
|
||||
CLK_000_P_SYNC_4_ = node,-,-,E,13;
|
||||
CLK_000_P_SYNC_5_ = node,-,-,B,10;
|
||||
CLK_000_P_SYNC_6_ = node,-,-,F,6;
|
||||
CLK_000_P_SYNC_7_ = node,-,-,B,6;
|
||||
CLK_000_P_SYNC_8_ = node,-,-,G,15;
|
||||
CLK_000_N_SYNC_0_ = node,-,-,G,11;
|
||||
CLK_000_N_SYNC_1_ = node,-,-,F,2;
|
||||
CLK_000_N_SYNC_2_ = node,-,-,F,13;
|
||||
CLK_000_N_SYNC_3_ = node,-,-,D,15;
|
||||
CLK_000_N_SYNC_4_ = node,-,-,D,11;
|
||||
CLK_000_N_SYNC_5_ = node,-,-,A,14;
|
||||
CLK_000_N_SYNC_6_ = node,-,-,A,10;
|
||||
CLK_000_N_SYNC_7_ = node,-,-,G,7;
|
||||
CLK_000_N_SYNC_8_ = node,-,-,B,2;
|
||||
CLK_000_N_SYNC_9_ = node,-,-,D,7;
|
||||
inst_DS_000_ENABLE = node,-,-,C,8;
|
||||
RST_DLY_0_ = node,-,-,D,3;
|
||||
RST_DLY_1_ = node,-,-,D,14;
|
||||
RST_DLY_2_ = node,-,-,D,7;
|
||||
CLK_000_P_SYNC_0_ = node,-,-,E,2;
|
||||
CLK_000_P_SYNC_1_ = node,-,-,B,7;
|
||||
CLK_000_P_SYNC_2_ = node,-,-,G,7;
|
||||
CLK_000_P_SYNC_3_ = node,-,-,E,13;
|
||||
CLK_000_P_SYNC_4_ = node,-,-,G,3;
|
||||
CLK_000_P_SYNC_5_ = node,-,-,G,14;
|
||||
CLK_000_P_SYNC_6_ = node,-,-,A,3;
|
||||
CLK_000_P_SYNC_7_ = node,-,-,B,3;
|
||||
CLK_000_P_SYNC_8_ = node,-,-,G,10;
|
||||
CLK_000_N_SYNC_0_ = node,-,-,E,9;
|
||||
CLK_000_N_SYNC_1_ = node,-,-,A,14;
|
||||
CLK_000_N_SYNC_2_ = node,-,-,B,14;
|
||||
CLK_000_N_SYNC_3_ = node,-,-,B,10;
|
||||
CLK_000_N_SYNC_4_ = node,-,-,B,6;
|
||||
CLK_000_N_SYNC_5_ = node,-,-,D,11;
|
||||
CLK_000_N_SYNC_6_ = node,-,-,G,6;
|
||||
CLK_000_N_SYNC_7_ = node,-,-,F,3;
|
||||
CLK_000_N_SYNC_8_ = node,-,-,A,10;
|
||||
CLK_000_N_SYNC_9_ = node,-,-,A,6;
|
||||
CLK_000_N_SYNC_10_ = node,-,-,H,2;
|
||||
SM_AMIGA_6_ = node,-,-,C,4;
|
||||
inst_CLK_030_H = node,-,-,A,13;
|
||||
SM_AMIGA_1_ = node,-,-,A,8;
|
||||
SM_AMIGA_3_ = node,-,-,F,5;
|
||||
SM_AMIGA_2_ = node,-,-,F,12;
|
||||
SM_AMIGA_i_7_ = node,-,-,F,8;
|
||||
CIIN_0 = node,-,-,E,9;
|
||||
SM_AMIGA_6_ = node,-,-,F,4;
|
||||
inst_CLK_030_H = node,-,-,A,2;
|
||||
SM_AMIGA_1_ = node,-,-,F,5;
|
||||
SM_AMIGA_3_ = node,-,-,F,6;
|
||||
SM_AMIGA_2_ = node,-,-,F,10;
|
||||
SM_AMIGA_i_7_ = node,-,-,F,0;
|
||||
CIIN_0 = node,-,-,E,5;
|
||||
|
||||
[GROUP ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
|
|
|
|||
|
|
@ -1609,6 +1609,152 @@
|
|||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 7 13 -1
|
||||
10 CLK_000 1 -1 -1 1 3 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
140 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
||||
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
||||
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
||||
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 366 6 1 0 68 -1 3 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
||||
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
||||
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
||||
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
||||
34 VMA 5 370 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 367 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
2 RESET 0 1 0 2 -1 1 0 21
|
||||
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
||||
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
||||
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
||||
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
||||
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
||||
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
||||
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
||||
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
||||
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
||||
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
||||
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
||||
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
||||
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
||||
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
||||
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
||||
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
||||
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
||||
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
||||
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
||||
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
||||
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
||||
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
||||
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
||||
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
||||
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
||||
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
||||
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
||||
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
||||
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
||||
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
||||
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
||||
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
||||
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
||||
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
||||
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
||||
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
||||
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
||||
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
||||
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
||||
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
||||
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
||||
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
||||
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
||||
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
||||
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
||||
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
||||
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
||||
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
||||
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
59 A1 1 -1 -1 1 1 59 -1
|
||||
35 VPA 1 -1 -1 1 5 35 -1
|
||||
29 DTACK 1 -1 -1 1 1 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
||||
10 CLK_000 1 -1 -1 1 1 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
|
|
@ -8,18 +8,18 @@
|
|||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Sun Jan 24 16:20:59 2016
|
||||
; DATE Mon Jan 25 07:24:24 2016
|
||||
|
||||
|
||||
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
|
||||
Pin 4 A_31_
|
||||
Pin 68 IPL_2_
|
||||
Pin 58 FC_1_
|
||||
Pin 56 IPL_1_
|
||||
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
|
||||
Pin 58 FC_1_
|
||||
Pin 67 IPL_0_
|
||||
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
|
||||
Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281
|
||||
Pin 57 FC_0_
|
||||
Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203
|
||||
Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101
|
||||
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
|
||||
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
|
||||
|
|
@ -31,7 +31,7 @@ Pin 28 BGACK_000
|
|||
Pin 64 CLK_030
|
||||
Pin 11 CLK_000
|
||||
Pin 61 CLK_OSZI
|
||||
Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 125
|
||||
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
|
||||
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271
|
||||
Pin 91 FPU_SENSE
|
||||
Pin 30 DTACK
|
||||
|
|
@ -41,14 +41,14 @@ Pin 36 VPA
|
|||
Pin 86 RST
|
||||
Pin 3 RESET Comb ; S6=1 S9=1 Pair 127
|
||||
Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181
|
||||
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
|
||||
Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263
|
||||
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
|
||||
Pin 5 A_30_
|
||||
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179
|
||||
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 6 A_29_
|
||||
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179
|
||||
Pin 15 A_28_
|
||||
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||
Pin 16 A_27_
|
||||
Pin 17 A_26_
|
||||
Pin 18 A_25_
|
||||
|
|
@ -68,7 +68,7 @@ Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
|
|||
Pin 69 A0 Reg ; S6=1 S9=1 Pair 257
|
||||
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
|
||||
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
|
||||
Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247
|
||||
Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 125
|
||||
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283
|
||||
Pin 35 VMA Reg ; S6=1 S9=1 Pair 173
|
||||
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
|
||||
|
|
@ -89,76 +89,74 @@ Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
|
|||
Node 283 RN_DSACK1 Reg ; S6=1 S9=1
|
||||
Node 173 RN_VMA Reg ; S6=1 S9=1
|
||||
Node 245 RN_RW Reg ; S6=1 S9=1
|
||||
Node 188 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 182 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 242 N_317_i Comb ; S6=1 S9=1
|
||||
Node 193 cpu_est_2_ Reg ; S6=1 S9=1
|
||||
Node 176 cpu_est_3_ Reg ; S6=1 S9=1
|
||||
Node 145 inst_AS_000_INT Reg ; S6=1 S9=1
|
||||
Node 227 SM_AMIGA_5_ Reg ; S6=1 S9=1
|
||||
Node 139 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
|
||||
Node 289 inst_AS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 277 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1
|
||||
Node 157 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 209 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
|
||||
Node 119 inst_AS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 115 inst_DS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 110 CYCLE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 104 CYCLE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 265 SIZE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 151 inst_VPA_D Reg ; S6=1 S9=1
|
||||
Node 109 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 103 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 178 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
|
||||
Node 106 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 253 inst_RESET_OUT Reg ; S6=1 S9=1
|
||||
Node 205 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 163 N_210_i Comb ; S6=1 S9=1
|
||||
Node 254 inst_CLK_OUT_PRE_25 Reg ; S6=1 S9=1
|
||||
Node 161 inst_CLK_000_D1 Reg ; S6=1 S9=1
|
||||
Node 187 inst_CLK_000_D0 Reg ; S6=1 S9=1
|
||||
Node 221 inst_CLK_000_PE Reg ; S6=1 S9=1
|
||||
Node 200 inst_CLK_OUT_EXP_INT Reg ; S6=1 S9=1
|
||||
Node 226 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 259 inst_CLK_000_NE Reg ; S6=1 S9=1
|
||||
Node 239 cpu_est_3_ Reg ; S6=1 S9=1
|
||||
Node 182 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 176 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 151 inst_AS_000_INT Reg ; S6=1 S9=1
|
||||
Node 233 SM_AMIGA_5_ Reg ; S6=1 S9=1
|
||||
Node 128 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1
|
||||
Node 274 inst_AS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 113 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1
|
||||
Node 155 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
|
||||
Node 103 inst_AS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 121 inst_DS_000_DMA Reg ; S6=1 S9=1
|
||||
Node 133 CYCLE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 167 CYCLE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 265 SIZE_DMA_0_ Reg ; S6=1 S9=1
|
||||
Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1
|
||||
Node 224 inst_VPA_D Reg ; S6=1 S9=1
|
||||
Node 115 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 109 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 119 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1
|
||||
Node 148 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 187 inst_RESET_OUT Reg ; S6=1 S9=1
|
||||
Node 241 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 209 inst_CLK_000_D1 Reg ; S6=1 S9=1
|
||||
Node 139 inst_CLK_000_D0 Reg ; S6=1 S9=1
|
||||
Node 253 inst_CLK_000_PE Reg ; S6=1 S9=1
|
||||
Node 268 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 248 inst_CLK_000_NE Reg ; S6=1 S9=1
|
||||
Node 278 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1
|
||||
Node 148 IPL_D0_0_ Reg ; S6=1 S9=1
|
||||
Node 142 IPL_D0_1_ Reg ; S6=1 S9=1
|
||||
Node 136 IPL_D0_2_ Reg ; S6=1 S9=1
|
||||
Node 194 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
|
||||
Node 262 IPL_D0_0_ Reg ; S6=1 S9=1
|
||||
Node 196 IPL_D0_1_ Reg ; S6=1 S9=1
|
||||
Node 142 IPL_D0_2_ Reg ; S6=1 S9=1
|
||||
Node 188 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
|
||||
Node 223 SM_AMIGA_0_ Reg ; S6=1 S9=1
|
||||
Node 133 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
|
||||
Node 145 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1
|
||||
Node 235 SM_AMIGA_4_ Reg ; S6=1 S9=1
|
||||
Node 167 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 266 RST_DLY_0_ Reg ; S6=1 S9=1
|
||||
Node 260 RST_DLY_1_ Reg ; S6=1 S9=1
|
||||
Node 250 RST_DLY_2_ Reg ; S6=1 S9=1
|
||||
Node 130 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 146 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 242 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 236 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 217 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 140 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 230 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 134 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 268 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 262 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 224 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 241 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 196 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 190 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 122 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 116 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 256 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 128 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 184 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 161 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 178 RST_DLY_0_ Reg ; S6=1 S9=1
|
||||
Node 194 RST_DLY_1_ Reg ; S6=1 S9=1
|
||||
Node 184 RST_DLY_2_ Reg ; S6=1 S9=1
|
||||
Node 200 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 136 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 256 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 217 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 250 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 266 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 106 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 130 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 260 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 211 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 122 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 146 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 140 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 134 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 190 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 254 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 226 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 116 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 110 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1
|
||||
Node 155 SM_AMIGA_6_ Reg ; S6=1 S9=1
|
||||
Node 121 inst_CLK_030_H Reg ; S6=1 S9=1
|
||||
Node 113 SM_AMIGA_1_ Reg ; S6=1 S9=1
|
||||
Node 229 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 239 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 233 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
|
||||
Node 211 CIIN_0 Comb ; S6=1 S9=1
|
||||
Node 227 SM_AMIGA_6_ Reg ; S6=1 S9=1
|
||||
Node 104 inst_CLK_030_H Reg ; S6=1 S9=1
|
||||
Node 229 SM_AMIGA_1_ Reg ; S6=1 S9=1
|
||||
Node 230 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 236 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 221 SM_AMIGA_i_7_ Reg ; S6=1 S9=1
|
||||
Node 205 CIIN_0 Comb ; S6=1 S9=1
|
||||
; Unused Pins & Nodes
|
||||
; -> None Found.
|
||||
|
|
|
|||
1188
Logic/68030_tk.prd
1188
Logic/68030_tk.prd
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -81,10 +81,10 @@ inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
|
|||
RN_VMA 1 1 0 0 .. .. 1 1
|
||||
RW 1 1 0 0 .. .. 1 1
|
||||
RN_RW 1 1 0 0 .. .. 1 1
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_1_ .. .. 1 1 .. .. 1 1
|
||||
cpu_est_2_ .. .. 1 1 .. .. 1 1
|
||||
cpu_est_3_ .. .. 1 1 .. .. 1 1
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 1
|
||||
cpu_est_1_ .. .. 1 1 .. .. 1 1
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. ..
|
||||
inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1
|
||||
inst_VPA_D 1 1 .. .. .. .. 1 1
|
||||
|
|
@ -92,9 +92,7 @@ inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1
|
|||
inst_DTACK_D0 1 1 .. .. .. .. 1 1
|
||||
inst_RESET_OUT 1 1 .. .. .. .. .. ..
|
||||
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_PE .. .. .. .. .. .. 1 1
|
||||
inst_CLK_OUT_EXP_INT .. .. 1 1 .. .. .. ..
|
||||
CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_NE .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1
|
||||
|
|
|
|||
1131
Logic/68030_tk.tt2
1131
Logic/68030_tk.tt2
File diff suppressed because it is too large
Load Diff
1131
Logic/68030_tk.tt3
1131
Logic/68030_tk.tt3
File diff suppressed because it is too large
Load Diff
|
|
@ -1,65 +1,64 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Sun Jan 24 16:20:54 2016
|
||||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ DS_030
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
|
||||
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
CLK_EXP FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
|
||||
AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH
|
||||
A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_
|
||||
A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030
|
||||
CLK_DIV_OUT DSACK1 VMA RW
|
||||
#$ NODES 71 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT
|
||||
CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
|
||||
SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_
|
||||
AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_
|
||||
A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000
|
||||
BGACK_030 CLK_EXP DSACK1 VMA RW
|
||||
#$ NODES 69 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
|
||||
SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
|
||||
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
|
||||
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
|
||||
inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
|
||||
inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0
|
||||
inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE
|
||||
CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_
|
||||
RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_
|
||||
CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_
|
||||
CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_
|
||||
CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_
|
||||
CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_
|
||||
CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_
|
||||
SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
|
||||
inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE
|
||||
CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_
|
||||
IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_
|
||||
CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_
|
||||
CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_
|
||||
CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_
|
||||
CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_
|
||||
CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_
|
||||
SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
|
||||
CIIN_0
|
||||
.type f
|
||||
.i 123
|
||||
.o 194
|
||||
.i 121
|
||||
.o 191
|
||||
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
|
||||
A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q
|
||||
cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AS_000_INT.Q
|
||||
N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q
|
||||
SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
|
||||
inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q
|
||||
inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
|
||||
SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
|
||||
inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
|
||||
N_210_i inst_CLK_OUT_PRE_25.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
|
||||
inst_CLK_000_PE.Q inst_CLK_OUT_EXP_INT.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q
|
||||
CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q
|
||||
SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q
|
||||
inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q
|
||||
CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q
|
||||
CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q
|
||||
CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q
|
||||
CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q
|
||||
CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q
|
||||
SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
|
||||
SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
|
||||
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN
|
||||
BERR.PIN RW.PIN CIIN_0
|
||||
inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
|
||||
inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
|
||||
inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
|
||||
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
|
||||
CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q
|
||||
CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q
|
||||
CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q
|
||||
CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q
|
||||
CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q
|
||||
RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q
|
||||
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
|
||||
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
|
||||
A0.PIN BERR.PIN RW.PIN CIIN_0
|
||||
.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE
|
||||
UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_EXP FPU_CS% AVEC E
|
||||
RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ SIZE_0_.OE
|
||||
AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D%
|
||||
IPL_030_2_.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C RW_000.D%
|
||||
RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C
|
||||
CLK_DIV_OUT.D CLK_DIV_OUT.C DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C
|
||||
RW.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D
|
||||
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C inst_AS_000_INT.D% inst_AS_000_INT.C
|
||||
SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
|
||||
UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C
|
||||
FPU_CS% AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE SIZE_0_ SIZE_0_.OE
|
||||
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE
|
||||
IPL_030_2_.D% IPL_030_2_.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C
|
||||
RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D
|
||||
BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D%
|
||||
RW.C RW.OE N_317_i% cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C
|
||||
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C inst_AS_000_INT.D%
|
||||
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C
|
||||
inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D%
|
||||
inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C
|
||||
|
|
@ -69,253 +68,248 @@
|
|||
inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
|
||||
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C
|
||||
inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
|
||||
N_210_i% inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_000_D1.D
|
||||
inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D
|
||||
inst_CLK_000_PE.C inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C
|
||||
CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C
|
||||
CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D%
|
||||
IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C
|
||||
SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D%
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D SM_AMIGA_4_.C
|
||||
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D
|
||||
RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C
|
||||
CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C
|
||||
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C
|
||||
CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C
|
||||
CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C
|
||||
CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C
|
||||
CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C
|
||||
CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C
|
||||
CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C
|
||||
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C
|
||||
CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C
|
||||
inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T
|
||||
SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0
|
||||
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
.p 225
|
||||
-------------------------------------------------01------------------------------------------------------------------------ 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
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|
||||
--------------------------------0---------0-------------1------------------------------------------------------------------ 00010001000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------0-------------------------------------------------------------------------0---------- 00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
--------------------------------------------------------------------------------------------------------------------------- 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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---------------------------------0-0100-------------0---------------1---0------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
----------------------------------------------------1---0-----------1---0------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1-----------------------------------------------1----------1------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------------------------------------------------------------------------------------------------1--------------0-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1-------------------0-0100-------------0---------------1----------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1--------------------------------------1---0-----------1----------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1-----------------------------------------------------------------------------------------11---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1-----------------------------------------------0------------------------------------------1-------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1-------------------010100-------------0--------1-1----10--------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----------------1---0----1-1----10--------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------010100-0-----------0--------1------10--------------------------------0------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0-----------1---0----1------10--------------------------------0------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1--------------------------1-1-----0---------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0--------------------1-------0--------------------------------00----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------010100-------------0----------1----10--0---------------------------0---0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----------------1---0------1----10--0---------------------------0---0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------010100-0-----------0---------------10--0---------------------------0-0-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0-----------1---0-----------10--0---------------------------0-0-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1----------------------------1-----0--0---------------------------0--00---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0----------------------------0--0---------------------------0-000---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1--------------------------0--------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1----------------------------------0------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -1,65 +1,64 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Sun Jan 24 16:20:54 2016
|
||||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ DS_030
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
|
||||
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
CLK_EXP FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
|
||||
AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH
|
||||
A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_
|
||||
A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030
|
||||
CLK_DIV_OUT DSACK1 VMA RW
|
||||
#$ NODES 71 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT
|
||||
CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
|
||||
SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_
|
||||
AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_
|
||||
A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000
|
||||
BGACK_030 CLK_EXP DSACK1 VMA RW
|
||||
#$ NODES 69 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT
|
||||
SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
|
||||
inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
|
||||
CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
|
||||
inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
|
||||
inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0
|
||||
inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE
|
||||
CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_
|
||||
RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_
|
||||
CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_
|
||||
CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_
|
||||
CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_
|
||||
CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_
|
||||
CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_
|
||||
SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
|
||||
inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE
|
||||
CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_
|
||||
IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH
|
||||
SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_
|
||||
CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_
|
||||
CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_
|
||||
CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_
|
||||
CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_
|
||||
CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_
|
||||
SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
|
||||
CIIN_0
|
||||
.type f
|
||||
.i 123
|
||||
.o 194
|
||||
.i 121
|
||||
.o 191
|
||||
.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
|
||||
A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q
|
||||
cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AS_000_INT.Q
|
||||
N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q
|
||||
SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
|
||||
inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q
|
||||
inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
|
||||
SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
|
||||
inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
|
||||
N_210_i inst_CLK_OUT_PRE_25.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
|
||||
inst_CLK_000_PE.Q inst_CLK_OUT_EXP_INT.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q
|
||||
CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q
|
||||
SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q
|
||||
inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q
|
||||
CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q
|
||||
CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q
|
||||
CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q
|
||||
CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q
|
||||
CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q
|
||||
SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
|
||||
SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
|
||||
AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN
|
||||
BERR.PIN RW.PIN CIIN_0
|
||||
inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q
|
||||
inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q
|
||||
inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q
|
||||
SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q
|
||||
CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q
|
||||
CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q
|
||||
CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q
|
||||
CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q
|
||||
CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q
|
||||
RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q
|
||||
SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q
|
||||
AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN
|
||||
A0.PIN BERR.PIN RW.PIN CIIN_0
|
||||
.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE
|
||||
UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_EXP FPU_CS- AVEC E
|
||||
RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ SIZE_0_.OE
|
||||
AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D-
|
||||
IPL_030_2_.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C RW_000.D-
|
||||
RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C
|
||||
CLK_DIV_OUT.D CLK_DIV_OUT.C DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C
|
||||
RW.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D
|
||||
cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C inst_AS_000_INT.D- inst_AS_000_INT.C
|
||||
SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
|
||||
UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C
|
||||
FPU_CS- AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE SIZE_0_ SIZE_0_.OE
|
||||
AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE
|
||||
IPL_030_2_.D- IPL_030_2_.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C
|
||||
RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D
|
||||
BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D-
|
||||
RW.C RW.OE N_317_i- cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C
|
||||
cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C inst_AS_000_INT.D-
|
||||
inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
|
||||
inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D-
|
||||
inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C
|
||||
|
|
@ -69,253 +68,248 @@
|
|||
inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
|
||||
inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C
|
||||
inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
|
||||
N_210_i- inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_000_D1.D
|
||||
inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D
|
||||
inst_CLK_000_PE.C inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C
|
||||
CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C
|
||||
CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D-
|
||||
IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C
|
||||
SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D SM_AMIGA_4_.C
|
||||
inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D
|
||||
RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C
|
||||
CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C
|
||||
CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C
|
||||
CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C
|
||||
CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C
|
||||
CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C
|
||||
CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C
|
||||
CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C
|
||||
CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C
|
||||
CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C
|
||||
CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C
|
||||
inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T
|
||||
SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0
|
||||
.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
|
||||
.p 225
|
||||
-------------------------------------------------01------------------------------------------------------------------------ 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------0---------0-------------------------------------------------------------------------------- 01000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---------------------------------------------0-------------------------------------------------------------------0--------- 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------0---------0-------------1------------------------------------------------------------------ 00010001000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------0-------------------------------------------------------------------------0---------- 00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------1-----------------------1------------------------------------------------------------------ 00000100010100000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------0------------------------------------------------------------------0--------- 00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------------0----------------------1----------------------------------------------- 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------------0---------------------1----------------------------------------------- 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------------------------------------------------------------------- 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--1---1---1--------------0010--1--------------------------------------------------------------------------------0---------- 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---------------------------------------------------------------0----------------------------------------------------------- 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--1---1---0--------------0010--1--------------------------------------------------------------------------------0---------- 00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------001------------------------------------------------------------------------------------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------110------------------------------------------------------------------------------------- 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------0------------------------------------------------------------------ 00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------0---------0----------------------------------------------------------------------01-------- 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------1---------------------------------------------------------------------------------0-------- 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------10------------------------------------------------------------------------ 00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------0-------0---------------------------------------------------------------------------------- 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------0---------------------------------------1-------------------------------------------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------1--------------------------------------------------------------------------0--------------- 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
0-------------00000001111----------------0--------------------------------------------------------------------------------- 00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
|
||||
--------------------------------------------------------------------------------------------------------------------------1 00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0-----------1---------------11------------------------------------110----------------------------------------------------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0-----------1---------------10------------------------------------010----------------------------------------------------- 00000000000000000000000000001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0-----------1---------------01------------------------------------100----------------------------------------------------- 00000000000000000000000000001010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0-----------1---------------00------------------------------------000----------------------------------------------------- 00000000000000000000000000001010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0-----------1-------------------------------------------------------------------------------------------------0----------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1----------------0------------------------------------1-------------------------------------------0----------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1----------------1------------------------------------0-------------------------------------------0----------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1---------------0--------------------------------------1------------------------------------------0----------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1---------------1--------------------------------------0------------------------------------------0----------- 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
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||||
---------------------------------0-0000----------------------1----------------------------------------------------------- 00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------1-0011-------------0----------1--------------------------------------------------------- 00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------1------------1----------------------------------------------------0---------------------- 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0-------------------------------------------------------------------------------0-------- 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------0------------------------1--------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------0--0-------------------------0--0---------------------------0-000---------------- 00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------0---1------------------------0--0---------------------------0-000---------------- 00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------0------------------0---------0--0---------------------------0-000---------------- 00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------0-------------------1--------0--0---------------------------0-000---------------- 00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------1-0----------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------1--0---------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------0-11-----------------------------1---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------1--------------------------------0---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------010----------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------1-11-----------------------------1---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------1-------------------------------0---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------0------------------------------1---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------1------------------------------0---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------01---------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------010-----------------------------1---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------1-----------------------------0---------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------1-------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------0--0---------------------------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------0--------------------1--------------------------------------1-------------------- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------1----------------------0------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------1-----------------------------------------------------------1-----------------1-- 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---1---------1------------------0---------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------1--------0---1--------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------------------------------------------------------0---------- 00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----0--------1----------------------------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1----------------------------0-0-------------------------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--0----------1------------------1---------01-1-----------------------------------------------------------0------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-----------1------1---------01-1-----------------------------------------------------------0------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------1-----1---------01-1-----------------------------------------------------------0------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------0----1---------01-1-----------------------------------------------------------0------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------1---1---------01-1-----------------------------------------------------------0------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-----------------01---------01-1-----------------------------------------------------------0------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0---------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------1---------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------0--------------------------------------1-------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------11----------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------00----------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---------------------------------------------------------------------------------------------------------------1--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------------------------------------------------------------------------11------ 00000000000000000000000000000000000000000000000000000000000000000000000000000010100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------0---------------------------------------1----------------------------------------------------------------0-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------1--------------------------------------1------------------------------------------------------1----------0-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------1-----------------------------------------------------0----------0-------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0---------------0------------1-------------------------------------------------0--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0---------------1------------0-------------------------------------------------0--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0---------------01-------------------------------------------------------------0--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0---------------10-----------1-------------------------------------------------0--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0----------------1-----------0-------------------------------------------------0--------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------1------------0--------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------1-----------------0---------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------0--------------------------------------------------------------------------------00------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------1------------1-----1--------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------0--------------------------------------------------------------------------------00------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------01----------------------------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1---------------------------------------0----------------------------------------------0-------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------------------------------------------------------------------1----------------0--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------------1---------------------------------------------0-------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------------------------------------------------------------1--------------100--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------------------1-------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-----------0-1----------------------------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------1--------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------1----------111-------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------------------0-------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------------------1------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------1---------------------------------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------1---------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------------------------------------------1----------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
----------------------------------------------------------------1-------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------------------------------------------------------1------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1----------------0------------------------------------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1---------------0------------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000
|
||||
-0-----------1----------------------------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000
|
||||
---------------------------------------------------------------1--------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------1-----0--------------------------------1------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-----------------------------------------------0-------1------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
|
||||
---0---------1------------------0---------------------------------------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------1------------1------------------------0-------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------1----------------------1--------------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------1-------------------------------1------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-----------------------------------------------0----------1---------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------0--------------------1-------0------------------------------0----1--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------0----------------------------0--0---------------------------0----1--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1----------------------------0------------------------------1--------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-----------------------------------------------1-------0------------------------------0----1-------------1- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------------0--0---------------------------0----1-------------1- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------0----------1---------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------1----------0---------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------------------111-------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------0-----------1--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
-------------1------------------------------------------------------------01--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------1----------10--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------------------11-------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
|
||||
-------------1-------------------------------------------------1----------11--------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000
|
||||
-------------1--------------------------------------------------------------1-------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------------------01------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000
|
||||
-----------------------------------------------------------------------------1------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000
|
||||
------------------------------------------------------------------------------1------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000
|
||||
-------------------------------------------------------------------------------1----------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000
|
||||
--------------------------------------------------------------------------------1---------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000
|
||||
---------------------------------------------------------------------------------1--------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
|
||||
----------------------------------------------------------------------------------1-------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
|
||||
-----------------------------------------------------------------------------------1------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000
|
||||
------------------------------------------------------------------------------------1------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000
|
||||
-----------------------------------------------------------10------------------------------------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000
|
||||
--------------------------------------------------------------------------------------1---------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
|
||||
---------------------------------------------------------------------------------------1--------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
|
||||
----------------------------------------------------------------------------------------1-------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
|
||||
-----------------------------------------------------------------------------------------1------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
|
||||
------------------------------------------------------------------------------------------1------------------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000
|
||||
-------------------------------------------------------------------------------------------1----------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000
|
||||
--------------------------------------------------------------------------------------------1---------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
|
||||
---------------------------------------------------------------------------------------------1--------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000
|
||||
----------------------------------------------------------------------------------------------1-------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000
|
||||
-----------------------------------------------------------------------------------------------1------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000
|
||||
-------------1-----------------------------10--------------10--------------------------------------------0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------------1--------------------------------------------------------------------------------------1----0--------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------------1-----------------------------------------------0--------------------------------------1-----------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
|
||||
-------0-----1------------------0-------------0-01-------------------------------------------------------------0-0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------0-----1------------------0-------------0-10-------------------------------------------------------------0-0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1------------------0---------------01---------------------------------------------------1---------0-0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1------------------0---------------10---------------------------------------------------1---------0-0------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------0-----1------------------0-------------0-01-------------------------------------------------------------0--0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------0-----1------------------0-------------0-10-------------------------------------------------------------0--0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1------------------0---------------01---------------------------------------------------1---------0--0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1------------------0---------------10---------------------------------------------------1---------0--0------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
|
||||
-------------1-----------------------------------------------1----------------------------------------0-1---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
|
||||
-------------1-------------------------------------------------0--------------------------------------1---------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
|
||||
-------------1----------------------------------------------------------------------------------------1-1-------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
|
||||
-------------0-----------------------------------------------------------------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
---------------------------------0-0100-------------0---------------1---0------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
----------------------------------------------------1---0-----------1---0------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1-----------------------------------------------1----------1------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------------------------------------------------------------------------------------------------1--------------0-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
|
||||
-------------1-------------------0-0100-------------0---------------1----------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1--------------------------------------1---0-----------1----------------------------------1----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1-----------------------------------------------------------------------------------------11---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1-----------------------------------------------0------------------------------------------1-------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
|
||||
-------------1-------------------010100-------------0--------1-1----10--------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----------------1---0----1-1----10--------------------------------------------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------010100-0-----------0--------1------10--------------------------------0------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0-----------1---0----1------10--------------------------------0------------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1--------------------------1-1-----0---------------------------------0----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0--------------------1-------0--------------------------------00----------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------010100-------------0----------1----10--0---------------------------0---0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----------------1---0------1----10--0---------------------------0---0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1-------------------010100-0-----------0---------------10--0---------------------------0-0-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0-----------1---0-----------10--0---------------------------0-0-0---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1----------------------------1-----0--0---------------------------0--00---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1-----0----------------------------0--0---------------------------0-000---------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1--------------------------0--------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
-------------1--------------------1----------------------------------0------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
|
||||
.end
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 1/24/16;
|
||||
TIME = 16:20:59;
|
||||
DATE = 1/25/16;
|
||||
TIME = 07:24:24;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
@ -136,9 +136,9 @@ layer = OFF;
|
|||
[LOCATION ASSIGNMENT]
|
||||
|
||||
Layer = OFF
|
||||
BERR = OUTPUT,41,4,-;
|
||||
RW_000 = BIDIR,80,7,-;
|
||||
AS_000 = OUTPUT,42,4,-;
|
||||
RW_000 = BIDIR,80,7,-;
|
||||
BERR = OUTPUT,41,4,-;
|
||||
RW = BIDIR,71,6,-;
|
||||
AS_030 = OUTPUT,82,7,-;
|
||||
UDS_000 = OUTPUT,32,3,-;
|
||||
|
|
@ -166,84 +166,82 @@ AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
|
|||
CLK_EXP = OUTPUT,10,1,-;
|
||||
RESET = OUTPUT,3,1,-;
|
||||
RN_BGACK_030 = NODE,-1,7,-;
|
||||
inst_RESET_OUT = NODE,*,6,-;
|
||||
inst_nEXP_SPACE_D0reg = NODE,*,7,-;
|
||||
inst_CLK_000_PE = NODE,*,5,-;
|
||||
inst_AS_030_D0 = NODE,*,7,-;
|
||||
SM_AMIGA_1_ = NODE,*,0,-;
|
||||
SM_AMIGA_5_ = NODE,*,5,-;
|
||||
inst_CLK_000_NE = NODE,*,6,-;
|
||||
inst_CLK_000_D0 = NODE,*,3,-;
|
||||
inst_nEXP_SPACE_D0reg = NODE,*,0,-;
|
||||
inst_RESET_OUT = NODE,*,3,-;
|
||||
inst_CLK_000_PE = NODE,*,6,-;
|
||||
SM_AMIGA_i_7_ = NODE,*,5,-;
|
||||
SM_AMIGA_2_ = NODE,*,5,-;
|
||||
inst_AS_030_D0 = NODE,*,7,-;
|
||||
cpu_est_2_ = NODE,*,3,-;
|
||||
SM_AMIGA_6_ = NODE,*,2,-;
|
||||
cpu_est_3_ = NODE,*,3,-;
|
||||
SM_AMIGA_6_ = NODE,*,5,-;
|
||||
SM_AMIGA_5_ = NODE,*,5,-;
|
||||
cpu_est_1_ = NODE,*,3,-;
|
||||
cpu_est_3_ = NODE,*,5,-;
|
||||
SM_AMIGA_0_ = NODE,*,5,-;
|
||||
inst_CLK_000_D1 = NODE,*,2,-;
|
||||
inst_BGACK_030_INT_D = NODE,*,4,-;
|
||||
CYCLE_DMA_0_ = NODE,*,1,-;
|
||||
inst_CLK_000_D0 = NODE,*,1,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,*,0,-;
|
||||
inst_BGACK_030_INT_D = NODE,*,7,-;
|
||||
inst_AS_000_DMA = NODE,*,0,-;
|
||||
SM_AMIGA_3_ = NODE,*,5,-;
|
||||
inst_AS_030_000_SYNC = NODE,*,2,-;
|
||||
inst_DS_000_ENABLE = NODE,*,2,-;
|
||||
RN_VMA = NODE,-1,3,-;
|
||||
SM_AMIGA_1_ = NODE,*,5,-;
|
||||
SM_AMIGA_4_ = NODE,*,5,-;
|
||||
inst_LDS_000_INT = NODE,*,0,-;
|
||||
SIZE_DMA_1_ = NODE,*,6,-;
|
||||
SIZE_DMA_0_ = NODE,*,6,-;
|
||||
CYCLE_DMA_1_ = NODE,*,2,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,1,-;
|
||||
inst_CLK_OUT_PRE_25 = NODE,*,6,-;
|
||||
inst_UDS_000_INT = NODE,*,0,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,1,-;
|
||||
inst_AS_000_INT = NODE,*,1,-;
|
||||
inst_AS_000_INT = NODE,*,2,-;
|
||||
cpu_est_0_ = NODE,*,3,-;
|
||||
inst_CLK_000_NE_D0 = NODE,*,3,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,*,4,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,*,3,-;
|
||||
inst_VPA_D = NODE,*,2,-;
|
||||
inst_CLK_000_NE = NODE,*,6,-;
|
||||
inst_CLK_000_D1 = NODE,*,4,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,*,5,-;
|
||||
inst_VPA_D = NODE,*,5,-;
|
||||
RN_IPL_030_0_ = NODE,-1,1,-;
|
||||
RN_IPL_030_1_ = NODE,-1,1,-;
|
||||
RN_IPL_030_2_ = NODE,-1,1,-;
|
||||
inst_DS_000_DMA = NODE,*,0,-;
|
||||
inst_CLK_030_H = NODE,*,0,-;
|
||||
inst_AS_030_000_SYNC = NODE,*,2,-;
|
||||
SM_AMIGA_3_ = NODE,*,5,-;
|
||||
RN_DSACK1 = NODE,-1,7,-;
|
||||
RST_DLY_1_ = NODE,*,6,-;
|
||||
N_210_i = NODE,*,2,-;
|
||||
SM_AMIGA_2_ = NODE,*,5,-;
|
||||
RST_DLY_1_ = NODE,*,3,-;
|
||||
N_317_i = NODE,*,5,-;
|
||||
RN_A0 = NODE,-1,6,-;
|
||||
RN_RW_000 = NODE,-1,7,-;
|
||||
RST_DLY_0_ = NODE,*,6,-;
|
||||
CYCLE_DMA_1_ = NODE,*,0,-;
|
||||
RST_DLY_0_ = NODE,*,3,-;
|
||||
RN_RW = NODE,-1,6,-;
|
||||
RN_BG_000 = NODE,-1,3,-;
|
||||
CIIN_0 = NODE,*,4,-;
|
||||
RST_DLY_2_ = NODE,*,6,-;
|
||||
CYCLE_DMA_0_ = NODE,*,0,-;
|
||||
RST_DLY_2_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_10_ = NODE,*,7,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,*,1,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,*,6,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,*,0,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,*,0,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,*,5,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,*,5,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,*,6,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,*,0,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,*,0,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,*,5,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,*,6,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,*,3,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,*,1,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,*,1,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,*,1,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,*,0,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,*,4,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,*,1,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,*,5,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,*,1,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,*,4,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,*,5,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,*,5,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,*,0,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,*,4,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,*,6,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,*,1,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,*,1,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,*,4,-;
|
||||
IPL_D0_2_ = NODE,*,1,-;
|
||||
IPL_D0_1_ = NODE,*,1,-;
|
||||
IPL_D0_0_ = NODE,*,1,-;
|
||||
IPL_D0_1_ = NODE,*,3,-;
|
||||
IPL_D0_0_ = NODE,*,6,-;
|
||||
CLK_000_N_SYNC_11_ = NODE,*,7,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,*,5,-;
|
||||
inst_CLK_OUT_EXP_INT = NODE,*,4,-;
|
||||
inst_DTACK_D0 = NODE,*,0,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,*,6,-;
|
||||
inst_DTACK_D0 = NODE,*,1,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 1/24/16;
|
||||
TIME = 16:20:59;
|
||||
DATE = 1/25/16;
|
||||
TIME = 07:24:24;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
@ -139,12 +139,12 @@ Layer = OFF;
|
|||
SIZE_1_ = BIDIR,79, H,-;
|
||||
A_31_ = INPUT,4, B,-;
|
||||
IPL_2_ = INPUT,68, G,-;
|
||||
FC_1_ = INPUT,58, F,-;
|
||||
IPL_1_ = INPUT,56, F,-;
|
||||
AS_030 = BIDIR,82, H,-;
|
||||
FC_1_ = INPUT,58, F,-;
|
||||
IPL_0_ = INPUT,67, G,-;
|
||||
AS_000 = BIDIR,42, E,-;
|
||||
AS_030 = BIDIR,82, H,-;
|
||||
FC_0_ = INPUT,57, F,-;
|
||||
AS_000 = BIDIR,42, E,-;
|
||||
DS_030 = OUTPUT,98, A,-;
|
||||
UDS_000 = BIDIR,32, D,-;
|
||||
LDS_000 = BIDIR,31, D,-;
|
||||
|
|
@ -156,7 +156,7 @@ BGACK_000 = INPUT,28, D,-;
|
|||
CLK_030 = INPUT,64,-,-;
|
||||
CLK_000 = INPUT,11,-,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
CLK_EXP = OUTPUT,10, B,-;
|
||||
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||
FPU_CS = OUTPUT,78, H,-;
|
||||
FPU_SENSE = INPUT,91, A,-;
|
||||
DTACK = INPUT,30, D,-;
|
||||
|
|
@ -166,14 +166,14 @@ VPA = INPUT,36,-,-;
|
|||
RST = INPUT,86,-,-;
|
||||
RESET = OUTPUT,3, B,-;
|
||||
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||
SIZE_0_ = BIDIR,70, G,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||
A_30_ = INPUT,5, B,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||
A_29_ = INPUT,6, B,-;
|
||||
CIIN = OUTPUT,47, E,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
|
||||
A_28_ = INPUT,15, C,-;
|
||||
CIIN = OUTPUT,47, E,-;
|
||||
A_27_ = INPUT,16, C,-;
|
||||
A_26_ = INPUT,17, C,-;
|
||||
A_25_ = INPUT,18, C,-;
|
||||
|
|
@ -193,78 +193,76 @@ RW_000 = BIDIR,80, H,-;
|
|||
A0 = BIDIR,69, G,-;
|
||||
BG_000 = OUTPUT,29, D,-;
|
||||
BGACK_030 = OUTPUT,83, H,-;
|
||||
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||
CLK_EXP = OUTPUT,10, B,-;
|
||||
DSACK1 = OUTPUT,81, H,-;
|
||||
VMA = OUTPUT,35, D,-;
|
||||
RW = BIDIR,71, G,-;
|
||||
cpu_est_0_ = NODE,10, D,-;
|
||||
cpu_est_1_ = NODE,6, D,-;
|
||||
N_317_i = NODE,14, F,-;
|
||||
cpu_est_2_ = NODE,13, D,-;
|
||||
cpu_est_3_ = NODE,2, D,-;
|
||||
inst_AS_000_INT = NODE,13, B,-;
|
||||
SM_AMIGA_5_ = NODE,4, F,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,9, B,-;
|
||||
inst_AS_030_D0 = NODE,13, H,-;
|
||||
inst_nEXP_SPACE_D0reg = NODE,5, H,-;
|
||||
inst_AS_030_000_SYNC = NODE,5, C,-;
|
||||
inst_BGACK_030_INT_D = NODE,8, E,-;
|
||||
inst_AS_000_DMA = NODE,12, A,-;
|
||||
inst_DS_000_DMA = NODE,9, A,-;
|
||||
CYCLE_DMA_0_ = NODE,6, A,-;
|
||||
CYCLE_DMA_1_ = NODE,2, A,-;
|
||||
SIZE_DMA_0_ = NODE,2, G,-;
|
||||
SIZE_DMA_1_ = NODE,13, G,-;
|
||||
inst_VPA_D = NODE,1, C,-;
|
||||
inst_UDS_000_INT = NODE,5, A,-;
|
||||
inst_LDS_000_INT = NODE,1, A,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,3, D,-;
|
||||
inst_DTACK_D0 = NODE,3, A,-;
|
||||
inst_RESET_OUT = NODE,5, G,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,5, E,-;
|
||||
N_210_i = NODE,9, C,-;
|
||||
inst_CLK_OUT_PRE_25 = NODE,6, G,-;
|
||||
inst_CLK_000_D1 = NODE,8, C,-;
|
||||
inst_CLK_000_D0 = NODE,9, D,-;
|
||||
inst_CLK_000_PE = NODE,0, F,-;
|
||||
inst_CLK_OUT_EXP_INT = NODE,2, E,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,3, F,-;
|
||||
inst_CLK_000_NE = NODE,9, G,-;
|
||||
cpu_est_3_ = NODE,12, F,-;
|
||||
cpu_est_0_ = NODE,6, D,-;
|
||||
cpu_est_1_ = NODE,2, D,-;
|
||||
inst_AS_000_INT = NODE,1, C,-;
|
||||
SM_AMIGA_5_ = NODE,8, F,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,2, B,-;
|
||||
inst_AS_030_D0 = NODE,3, H,-;
|
||||
inst_nEXP_SPACE_D0reg = NODE,8, A,-;
|
||||
inst_AS_030_000_SYNC = NODE,4, C,-;
|
||||
inst_BGACK_030_INT_D = NODE,13, H,-;
|
||||
inst_AS_000_DMA = NODE,1, A,-;
|
||||
inst_DS_000_DMA = NODE,13, A,-;
|
||||
CYCLE_DMA_0_ = NODE,5, B,-;
|
||||
CYCLE_DMA_1_ = NODE,12, C,-;
|
||||
SIZE_DMA_0_ = NODE,13, G,-;
|
||||
SIZE_DMA_1_ = NODE,9, G,-;
|
||||
inst_VPA_D = NODE,2, F,-;
|
||||
inst_UDS_000_INT = NODE,9, A,-;
|
||||
inst_LDS_000_INT = NODE,5, A,-;
|
||||
inst_CLK_OUT_PRE_D = NODE,12, A,-;
|
||||
inst_DTACK_D0 = NODE,15, B,-;
|
||||
inst_RESET_OUT = NODE,9, D,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,13, F,-;
|
||||
inst_CLK_000_D1 = NODE,8, E,-;
|
||||
inst_CLK_000_D0 = NODE,9, B,-;
|
||||
inst_CLK_000_PE = NODE,5, G,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,15, G,-;
|
||||
inst_CLK_000_NE = NODE,2, G,-;
|
||||
CLK_000_N_SYNC_11_ = NODE,6, H,-;
|
||||
IPL_D0_0_ = NODE,15, B,-;
|
||||
IPL_D0_1_ = NODE,11, B,-;
|
||||
IPL_D0_2_ = NODE,7, B,-;
|
||||
inst_CLK_000_NE_D0 = NODE,14, D,-;
|
||||
IPL_D0_0_ = NODE,11, G,-;
|
||||
IPL_D0_1_ = NODE,15, D,-;
|
||||
IPL_D0_2_ = NODE,11, B,-;
|
||||
inst_CLK_000_NE_D0 = NODE,10, D,-;
|
||||
SM_AMIGA_0_ = NODE,1, F,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,5, B,-;
|
||||
inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,13, B,-;
|
||||
SM_AMIGA_4_ = NODE,9, F,-;
|
||||
inst_DS_000_ENABLE = NODE,12, C,-;
|
||||
RST_DLY_0_ = NODE,14, G,-;
|
||||
RST_DLY_1_ = NODE,10, G,-;
|
||||
RST_DLY_2_ = NODE,3, G,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,3, B,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,14, B,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,14, F,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,10, F,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,13, E,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,10, B,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,6, F,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,6, B,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,15, G,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,11, G,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,2, F,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,13, F,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,15, D,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,11, D,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,14, A,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,10, A,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,7, G,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,2, B,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,7, D,-;
|
||||
inst_DS_000_ENABLE = NODE,8, C,-;
|
||||
RST_DLY_0_ = NODE,3, D,-;
|
||||
RST_DLY_1_ = NODE,14, D,-;
|
||||
RST_DLY_2_ = NODE,7, D,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,2, E,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,7, B,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,7, G,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,13, E,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,3, G,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,14, G,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,3, A,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,3, B,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,10, G,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,9, E,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,14, A,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,14, B,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,10, B,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,6, B,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,11, D,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,6, G,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,3, F,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,10, A,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,6, A,-;
|
||||
CLK_000_N_SYNC_10_ = NODE,2, H,-;
|
||||
SM_AMIGA_6_ = NODE,4, C,-;
|
||||
inst_CLK_030_H = NODE,13, A,-;
|
||||
SM_AMIGA_1_ = NODE,8, A,-;
|
||||
SM_AMIGA_3_ = NODE,5, F,-;
|
||||
SM_AMIGA_2_ = NODE,12, F,-;
|
||||
SM_AMIGA_i_7_ = NODE,8, F,-;
|
||||
CIIN_0 = NODE,9, E,-;
|
||||
SM_AMIGA_6_ = NODE,4, F,-;
|
||||
inst_CLK_030_H = NODE,2, A,-;
|
||||
SM_AMIGA_1_ = NODE,5, F,-;
|
||||
SM_AMIGA_3_ = NODE,6, F,-;
|
||||
SM_AMIGA_2_ = NODE,10, F,-;
|
||||
SM_AMIGA_i_7_ = NODE,0, F,-;
|
||||
CIIN_0 = NODE,5, E,-;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Signal Name Cross Reference File
|
|||
|
||||
ispLEVER Classic 1.8.00.04.29.14
|
||||
|
||||
Design '68030_tk' created Sun Jan 24 16:20:54 2016
|
||||
Design '68030_tk' created Mon Jan 25 07:24:19 2016
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
2917
Logic/BUS68030.bl0
2917
Logic/BUS68030.bl0
File diff suppressed because it is too large
Load Diff
2940
Logic/BUS68030.bl1
2940
Logic/BUS68030.bl1
File diff suppressed because it is too large
Load Diff
4768
Logic/BUS68030.edi
4768
Logic/BUS68030.edi
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Sun Jan 24 16:20:40 2016
|
||||
#-- Written on Mon Jan 25 07:24:04 2016
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
6043
Logic/BUS68030.srm
6043
Logic/BUS68030.srm
File diff suppressed because it is too large
Load Diff
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Sun Jan 24 16:20:47 2016
|
||||
#Mon Jan 25 07:24:12 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -27,6 +27,8 @@ Post processing for work.bus68030.behavioral
|
|||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
|
|
@ -46,10 +48,10 @@ State machine has 8 reachable states with original encodings of:
|
|||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:47 2016
|
||||
# Mon Jan 25 07:24:12 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
|
|
@ -59,7 +61,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:48 2016
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -84,15 +86,15 @@ original code -> new code
|
|||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 80 uses
|
||||
DFF 78 uses
|
||||
BI_DIR 10 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 46 uses
|
||||
OBUF 15 uses
|
||||
AND2 297 uses
|
||||
AND2 299 uses
|
||||
INV 261 uses
|
||||
OR2 27 uses
|
||||
XOR2 8 uses
|
||||
XOR2 7 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -102,6 +104,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:49 2016
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
Binary file not shown.
1029
Logic/bus68030.exf
1029
Logic/bus68030.exf
File diff suppressed because it is too large
Load Diff
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Sun Jan 24 16:20:47 2016
|
||||
#Mon Jan 25 07:24:12 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -27,6 +27,8 @@ Post processing for work.bus68030.behavioral
|
|||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
|
|
@ -46,10 +48,10 @@ State machine has 8 reachable states with original encodings of:
|
|||
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:47 2016
|
||||
# Mon Jan 25 07:24:12 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
|
|
@ -59,7 +61,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:48 2016
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -84,15 +86,15 @@ original code -> new code
|
|||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 80 uses
|
||||
DFF 78 uses
|
||||
BI_DIR 10 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 46 uses
|
||||
OBUF 15 uses
|
||||
AND2 297 uses
|
||||
AND2 299 uses
|
||||
INV 261 uses
|
||||
OR2 27 uses
|
||||
XOR2 8 uses
|
||||
XOR2 7 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -102,6 +104,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:49 2016
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -26,10 +26,10 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
|
|||
SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
|
||||
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
|
||||
SR<qM3="lkF8DHCVDRC"P(=""
|
||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jc3jn6U("
|
||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
|
||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
|
||||
/>SqS<R"M=3MOF#M0N0C_soP"R=J"&k;F0ABtqid_jjh_Qa)_u &R4J0kF;>"/
|
||||
<SSq=RM"03#lH0D#H00lRC"Pj="36j4n".6/S>
|
||||
<SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>
|
||||
SR<qMF="s_HoH0M#_"FVR"P=&FJk0z;A1jnUdJj&k;F0"
|
||||
/>SqS<R"M=3HFsolhNCP"R=J"&k;F0Anz1Ujjd&FJk0/;">
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Sun Jan 24 16:20:47 2016
|
||||
#-- Written on Mon Jan 25 07:24:12 2016
|
||||
|
||||
|
||||
#project files
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:48 2016
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -18,15 +18,15 @@ original code -> new code
|
|||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 80 uses
|
||||
DFF 78 uses
|
||||
BI_DIR 10 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 46 uses
|
||||
OBUF 15 uses
|
||||
AND2 297 uses
|
||||
AND2 299 uses
|
||||
INV 261 uses
|
||||
OR2 27 uses
|
||||
XOR2 8 uses
|
||||
XOR2 7 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
@ -36,6 +36,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:49 2016
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>11</data>
|
||||
<data>13</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
|
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1453648847</data>
|
||||
<data type="timestamp">1453703052</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -4,6 +4,8 @@
|
|||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>105MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1453648849</data>
|
||||
<data type="timestamp">1453703054</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<html><body><samp><pre>
|
||||
<!@TC:1453648847>
|
||||
<!@TC:1453703052>
|
||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: C:\ispLever\synpbase
|
||||
#OS: Windows 7 6.2
|
||||
|
|
@ -8,32 +8,34 @@
|
|||
#Implementation: logic
|
||||
|
||||
<a name=compilerReport1>$ Start of Compile</a>
|
||||
#Sun Jan 24 16:20:47 2016
|
||||
#Mon Jan 25 07:24:12 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1453648847> | Running in 64-bit mode
|
||||
@N: : <!@TM:1453703052> | Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1453648847> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453648847> | Top entity is set to BUS68030.
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1453703052> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453703052> | Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453648847> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1453648847> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1453648847> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1453648847> | Signal clk_out_pre is undriven </font>
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453703052> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1453703052> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1453703052> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1453703052> | Signal clk_out_pre is undriven </font>
|
||||
Post processing for work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1453648847> | Pruning register CLK_000_D4_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1453648847> | Pruning register CLK_000_D3_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1453648847> | Pruning register CLK_000_D2_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1453648847> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:61:134:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1453648847> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453648847> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Trying to extract state machine for register SM_AMIGA
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1453703052> | Pruning register CLK_000_D4_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1453703052> | Pruning register CLK_000_D3_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1453703052> | Pruning register CLK_000_D2_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:34:126:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1453703052> | Pruning register CLK_OUT_EXP_INT_1 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1453703052> | Pruning register CLK_OUT_PRE_25_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1453703052> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:61:134:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1453703052> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453703052> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -44,24 +46,24 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1453648847> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1453703052> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:47 2016
|
||||
# Mon Jan 25 07:24:12 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1453648848> | Running in 64-bit mode
|
||||
@N: : <!@TM:1453703053> | Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:48 2016
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -69,8 +71,8 @@ Map & Optimize Report
|
|||
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1453648849> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N::@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648849> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1453703054> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N::@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703054> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -81,30 +83,30 @@ original code -> new code
|
|||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453648849> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453703054> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||
---------------------------------------
|
||||
<a name=resourceUsage3>Resource Usage Report</a>
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 80 uses
|
||||
DFF 78 uses
|
||||
BI_DIR 10 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 46 uses
|
||||
OBUF 15 uses
|
||||
AND2 297 uses
|
||||
AND2 299 uses
|
||||
INV 261 uses
|
||||
OR2 27 uses
|
||||
XOR2 8 uses
|
||||
XOR2 7 uses
|
||||
|
||||
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1453648849> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1453703054> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Jan 24 16:20:49 2016
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (16:20 24-Jan)</a>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (07:24 25-Jan)</a>
|
||||
<ul ></ul></li> </ul>
|
||||
</li>
|
||||
</ul>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
Synopsys, Inc.
|
||||
Version I-2014.03LC
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Sun Jan 24 16:20:47 2016
|
||||
Written on Mon Jan 25 07:24:12 2016
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -33,12 +33,12 @@
|
|||
<tr>
|
||||
<td class="optionTitle">Compile Input</td><td>Complete</td>
|
||||
<td>8</td>
|
||||
<td>11</td>
|
||||
<td>13</td>
|
||||
<td>0</td>
|
||||
<td>-</td>
|
||||
<td>0m:00s</td>
|
||||
<td>-</td>
|
||||
<td><font size="-1">24.01.2016</font><br/><font size="-2">16:20:47</font></td>
|
||||
<td><font size="-1">25.01.2016</font><br/><font size="-2">07:24:12</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
|
|
@ -49,12 +49,12 @@
|
|||
<td>0m:00s</td>
|
||||
<td>0m:00s</td>
|
||||
<td>105MB</td>
|
||||
<td><font size="-1">24.01.2016</font><br/><font size="-2">16:20:49</font></td>
|
||||
<td><font size="-1">25.01.2016</font><br/><font size="-2">07:24:14</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Multi-srs Generator</td>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">24.01.2016</font><br/><font size="-2">16:20:48</font></td> </tbody>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">25.01.2016</font><br/><font size="-2">07:24:13</font></td> </tbody>
|
||||
</table>
|
||||
</td></tr></table></body>
|
||||
</html>
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453648836
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453703040
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453648836
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453703040
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -8,6 +8,8 @@ Post processing for work.bus68030.behavioral
|
|||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
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Loading…
Reference in New Issue