mirror of https://github.com/kr239/68030tk.git
Some jed-files generated
This commit is contained in:
MHeinrichs
parent
63002d2099
commit
96a7e32d95
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@ -351364,3 +351364,409 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
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########## Tcl recorder end at 01/25/16 07:24:04 ###########
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########## Tcl recorder starts at 01/27/16 21:48:06 ##########
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# Commands to make the Process:
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# JEDEC File
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if [catch {open 68030_tk.rsp w} rspFile] {
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puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
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} else {
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puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
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"
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close $rspFile
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}
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if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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file delete 68030_tk.rsp
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if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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########## Tcl recorder end at 01/27/16 21:48:06 ###########
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########## Tcl recorder starts at 01/27/16 21:48:29 ##########
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# Commands to make the Process:
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# Hierarchy
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if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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########## Tcl recorder end at 01/27/16 21:48:29 ###########
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########## Tcl recorder starts at 01/27/16 21:48:29 ##########
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# Commands to make the Process:
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# JEDEC File
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if [catch {open BUS68030.cmd w} rspFile] {
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puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
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} else {
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puts $rspFile "STYFILENAME: 68030_tk.sty
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PROJECT: BUS68030
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WORKING_PATH: \"$proj_dir\"
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MODULE: BUS68030
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VHDL_FILE_LIST: 68030-68000-bus.vhd
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OUTPUT_FILE_NAME: BUS68030
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SUFFIX_NAME: edi
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PART: M4A5-128/64-10VC
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"
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close $rspFile
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}
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if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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file delete BUS68030.cmd
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if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [catch {open 68030_tk.rsp w} rspFile] {
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puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
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} else {
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puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
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"
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close $rspFile
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}
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if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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file delete 68030_tk.rsp
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if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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########## Tcl recorder end at 01/27/16 21:48:29 ###########
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########## Tcl recorder starts at 01/27/16 21:56:36 ##########
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# Commands to make the Process:
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# Hierarchy
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if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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########## Tcl recorder end at 01/27/16 21:56:36 ###########
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########## Tcl recorder starts at 01/27/16 21:56:36 ##########
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# Commands to make the Process:
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# JEDEC File
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if [catch {open BUS68030.cmd w} rspFile] {
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puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
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} else {
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puts $rspFile "STYFILENAME: 68030_tk.sty
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PROJECT: BUS68030
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WORKING_PATH: \"$proj_dir\"
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MODULE: BUS68030
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VHDL_FILE_LIST: 68030-68000-bus.vhd
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OUTPUT_FILE_NAME: BUS68030
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SUFFIX_NAME: edi
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PART: M4A5-128/64-10VC
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"
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close $rspFile
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}
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if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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file delete BUS68030.cmd
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if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
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return
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} else {
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vwait done
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if [checkResult $done] {
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return
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}
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}
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if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
|
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return
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} else {
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vwait done
|
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if [checkResult $done] {
|
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return
|
||||
}
|
||||
}
|
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if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
|
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return
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} else {
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vwait done
|
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if [checkResult $done] {
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return
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}
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}
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if [catch {open 68030_tk.rsp w} rspFile] {
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puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
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} else {
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puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
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"
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close $rspFile
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}
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if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
|
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return
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} else {
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vwait done
|
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if [checkResult $done] {
|
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return
|
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}
|
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}
|
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file delete 68030_tk.rsp
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if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
|
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return
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} else {
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vwait done
|
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if [checkResult $done] {
|
||||
return
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||||
}
|
||||
}
|
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if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
|
||||
return
|
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} else {
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vwait done
|
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if [checkResult $done] {
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return
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}
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}
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########## Tcl recorder end at 01/27/16 21:56:36 ###########
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File diff suppressed because it is too large
Load Diff
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@ -10,7 +10,7 @@ AUTHOR:
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PATTERN:
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COMPANY:
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REVISION:
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DATE: Mon Jan 25 07:24:24 2016
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DATE: Wed Jan 27 21:56:53 2016
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ABEL mach447a
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*
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File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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#$ TOOL ispLEVER Classic 1.8.00.04.29.14
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#$ DATE Mon Jan 25 07:24:19 2016
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#$ DATE Wed Jan 27 21:56:48 2016
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#$ MODULE 68030_tk
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#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \
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# IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \
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|
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@ -1,5 +1,5 @@
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#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
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#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ DATE Wed Jan 27 21:56:48 2016
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ \
|
||||
# AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
// Signal Name Cross Reference File
|
||||
// ispLEVER Classic 1.8.00.04.29.14
|
||||
|
||||
// Design '68030_tk' created Mon Jan 25 07:24:19 2016
|
||||
// Design '68030_tk' created Wed Jan 27 21:56:48 2016
|
||||
|
||||
|
||||
// LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
Copyright(C), 1992-2014, Lattice Semiconductor Corp.
|
||||
All Rights Reserved.
|
||||
|
||||
Design bus68030 created Mon Jan 25 07:24:19 2016
|
||||
Design bus68030 created Wed Jan 27 21:56:48 2016
|
||||
|
||||
|
||||
P-Terms Fan-in Fan-out Type Name (attributes)
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
<LATTICE_ENCRYPTED_BLIF>9420425ah[j@bK
|
||||
<LATTICE_ENCRYPTED_BLIF>910;6<5r } [
|
||||
|
|
@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
|
|||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
DATE = 1/25/16;
|
||||
TIME = 07:24:24;
|
||||
DATE = 1/27/16;
|
||||
TIME = 21:56:53;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
|
|
|||
|
|
@ -1725,6 +1725,445 @@
|
|||
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
||||
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
59 A1 1 -1 -1 1 1 59 -1
|
||||
35 VPA 1 -1 -1 1 5 35 -1
|
||||
29 DTACK 1 -1 -1 1 1 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
||||
10 CLK_000 1 -1 -1 1 1 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
140 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
||||
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
||||
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
||||
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 366 6 1 0 68 -1 3 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
||||
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
||||
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
||||
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
||||
34 VMA 5 370 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 367 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
2 RESET 0 1 0 2 -1 1 0 21
|
||||
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
||||
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
||||
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
||||
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
||||
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
||||
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
||||
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
||||
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
||||
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
||||
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
||||
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
||||
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
||||
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
||||
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
||||
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
||||
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
||||
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
||||
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
||||
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
||||
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
||||
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
||||
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
||||
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
||||
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
||||
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
||||
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
||||
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
||||
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
||||
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
||||
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
||||
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
||||
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
||||
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
||||
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
||||
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
||||
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
||||
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
||||
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
||||
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
||||
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
||||
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
||||
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
||||
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
||||
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
||||
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
||||
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
||||
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
||||
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
||||
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 2 4 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 2 4 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 2 4 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 2 4 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
67 IPL_2_ 1 -1 -1 1 1 67 -1
|
||||
59 A1 1 -1 -1 1 1 59 -1
|
||||
35 VPA 1 -1 -1 1 5 35 -1
|
||||
29 DTACK 1 -1 -1 1 1 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 0 13 -1
|
||||
10 CLK_000 1 -1 -1 1 1 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
141 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21
|
||||
79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21
|
||||
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
|
||||
70 RW 5 372 6 2 5 7 70 -1 2 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 367 6 1 1 68 -1 3 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21
|
||||
8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21
|
||||
80 DSACK1 5 370 7 0 80 -1 4 0 21
|
||||
82 BGACK_030 5 369 7 0 82 -1 3 0 21
|
||||
34 VMA 5 371 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 368 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
2 RESET 0 1 0 2 -1 1 0 21
|
||||
369 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21
|
||||
315 inst_RESET_OUT 3 -1 5 7 0 1 3 4 5 6 7 -1 -1 2 0 21
|
||||
301 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
||||
320 inst_CLK_000_PE 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21
|
||||
300 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21
|
||||
361 SM_AMIGA_i_7_ 3 -1 2 4 2 3 5 7 -1 -1 14 0 21
|
||||
298 SM_AMIGA_5_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21
|
||||
322 inst_CLK_000_NE 3 -1 4 4 0 2 3 5 -1 -1 1 0 21
|
||||
294 cpu_est_2_ 3 -1 6 3 2 3 6 -1 -1 4 0 21
|
||||
355 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21
|
||||
330 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21
|
||||
295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
||||
293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21
|
||||
328 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21
|
||||
296 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21
|
||||
319 inst_CLK_000_D0 3 -1 0 3 2 3 4 -1 -1 1 0 21
|
||||
313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21
|
||||
304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
302 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21
|
||||
331 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21
|
||||
371 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21
|
||||
357 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21
|
||||
312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21
|
||||
309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21
|
||||
317 inst_CLK_OUT_PRE_25 3 -1 6 2 3 6 -1 -1 2 0 21
|
||||
311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21
|
||||
299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21
|
||||
297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21
|
||||
327 inst_CLK_000_NE_D0 3 -1 5 2 2 6 -1 -1 1 0 21
|
||||
318 inst_CLK_000_D1 3 -1 4 2 2 4 -1 -1 1 0 21
|
||||
316 inst_CLK_OUT_PRE_50 3 -1 5 2 5 6 -1 -1 1 0 21
|
||||
310 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21
|
||||
303 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21
|
||||
365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
358 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21
|
||||
370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
359 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21
|
||||
333 RST_DLY_1_ 3 -1 5 1 5 -1 -1 4 0 21
|
||||
367 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
332 RST_DLY_0_ 3 -1 5 1 5 -1 -1 3 0 21
|
||||
307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21
|
||||
372 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
360 N_199_i 3 -1 2 1 2 -1 -1 2 0 21
|
||||
334 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21
|
||||
306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21
|
||||
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
||||
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
||||
352 CLK_000_N_SYNC_8_ 3 -1 3 1 0 -1 -1 1 0 21
|
||||
351 CLK_000_N_SYNC_7_ 3 -1 3 1 3 -1 -1 1 0 21
|
||||
350 CLK_000_N_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21
|
||||
349 CLK_000_N_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21
|
||||
348 CLK_000_N_SYNC_4_ 3 -1 1 1 2 -1 -1 1 0 21
|
||||
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
||||
343 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
342 CLK_000_P_SYNC_7_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
341 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21
|
||||
340 CLK_000_P_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
339 CLK_000_P_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
||||
338 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
337 CLK_000_P_SYNC_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
336 CLK_000_P_SYNC_1_ 3 -1 0 1 3 -1 -1 1 0 21
|
||||
335 CLK_000_P_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
||||
326 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
325 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21
|
||||
324 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
323 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21
|
||||
321 CLK_000_P_SYNC_9_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
314 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
96 A_19_ 1 -1 -1 3 4 5 7 96 -1
|
||||
95 A_16_ 1 -1 -1 3 4 5 7 95 -1
|
||||
94 A_18_ 1 -1 -1 3 4 5 7 94 -1
|
||||
58 A_17_ 1 -1 -1 3 4 5 7 58 -1
|
||||
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
|
||||
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
|
||||
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
|
||||
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
|
||||
66 IPL_0_ 1 -1 -1 2 0 1 66 -1
|
||||
63 CLK_030 1 -1 -1 2 0 7 63 -1
|
||||
55 IPL_1_ 1 -1 -1 2 1 2 55 -1
|
||||
27 BGACK_000 1 -1 -1 2 4 7 27 -1
|
||||
93 A_21_ 1 -1 -1 1 4 93 -1
|
||||
92 A_20_ 1 -1 -1 1 4 92 -1
|
||||
84 A_23_ 1 -1 -1 1 4 84 -1
|
||||
83 A_22_ 1 -1 -1 1 4 83 -1
|
||||
59 A1 1 -1 -1 1 6 59 -1
|
||||
35 VPA 1 -1 -1 1 3 35 -1
|
||||
29 DTACK 1 -1 -1 1 6 29 -1
|
||||
20 BG_030 1 -1 -1 1 3 20 -1
|
||||
18 A_24_ 1 -1 -1 1 4 18 -1
|
||||
17 A_25_ 1 -1 -1 1 4 17 -1
|
||||
16 A_26_ 1 -1 -1 1 4 16 -1
|
||||
15 A_27_ 1 -1 -1 1 4 15 -1
|
||||
14 A_28_ 1 -1 -1 1 4 14 -1
|
||||
13 nEXP_SPACE 1 -1 -1 1 5 13 -1
|
||||
10 CLK_000 1 -1 -1 1 0 10 -1
|
||||
5 A_29_ 1 -1 -1 1 4 5 -1
|
||||
4 A_30_ 1 -1 -1 1 4 4 -1
|
||||
3 A_31_ 1 -1 -1 1 4 3 -1
|
||||
140 "number of signals after reading design file"
|
||||
|
||||
"sig sig sig pair blk fan PT xor sync"
|
||||
"num name type sig num out pin node cnt PT type"
|
||||
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
|
||||
|
||||
41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21
|
||||
79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21
|
||||
40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21
|
||||
70 RW 5 371 6 2 2 7 70 -1 2 0 21
|
||||
81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21
|
||||
31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21
|
||||
30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21
|
||||
68 A0 5 366 6 1 0 68 -1 3 0 21
|
||||
78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21
|
||||
69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21
|
||||
8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21
|
||||
7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21
|
||||
6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21
|
||||
80 DSACK1 5 369 7 0 80 -1 4 0 21
|
||||
82 BGACK_030 5 368 7 0 82 -1 3 0 21
|
||||
34 VMA 5 370 3 0 34 -1 3 0 21
|
||||
65 E 0 6 0 65 -1 2 0 21
|
||||
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
|
||||
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
|
||||
28 BG_000 5 367 3 0 28 -1 2 0 21
|
||||
97 DS_030 0 0 0 97 -1 1 0 21
|
||||
91 AVEC 0 0 0 91 -1 1 0 21
|
||||
77 FPU_CS 0 7 0 77 -1 1 0 21
|
||||
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
|
||||
46 CIIN 0 4 0 46 -1 1 0 21
|
||||
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
|
||||
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
|
||||
9 CLK_EXP 0 1 0 9 -1 1 0 21
|
||||
2 RESET 0 1 0 2 -1 1 0 21
|
||||
368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21
|
||||
302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21
|
||||
316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21
|
||||
320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21
|
||||
360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21
|
||||
301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21
|
||||
294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
|
||||
355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21
|
||||
299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21
|
||||
297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
|
||||
295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21
|
||||
328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21
|
||||
307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21
|
||||
319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21
|
||||
314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21
|
||||
304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21
|
||||
305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
|
||||
303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21
|
||||
331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21
|
||||
370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
|
||||
357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
|
||||
330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21
|
||||
313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21
|
||||
310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21
|
||||
308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21
|
||||
329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
|
||||
312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21
|
||||
300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21
|
||||
298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
|
||||
296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21
|
||||
327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21
|
||||
322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21
|
||||
318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21
|
||||
317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21
|
||||
311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21
|
||||
364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21
|
||||
363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21
|
||||
362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21
|
||||
306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
|
||||
356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
|
||||
358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
|
||||
369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21
|
||||
359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21
|
||||
333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21
|
||||
293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21
|
||||
366 RN_A0 3 68 6 1 6 68 -1 3 0 21
|
||||
365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21
|
||||
332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21
|
||||
371 RN_RW 3 70 6 1 6 70 -1 2 0 21
|
||||
367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
|
||||
361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
|
||||
334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21
|
||||
354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21
|
||||
353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21
|
||||
352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21
|
||||
351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21
|
||||
350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21
|
||||
349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21
|
||||
348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21
|
||||
347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21
|
||||
343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21
|
||||
340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21
|
||||
339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21
|
||||
337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21
|
||||
336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21
|
||||
335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21
|
||||
326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
|
||||
325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
|
||||
324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
|
||||
323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21
|
||||
321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21
|
||||
315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21
|
||||
60 CLK_OSZI 9 -1 0 60 -1
|
||||
85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Mon Jan 25 07:24:24 2016
|
||||
; DATE Wed Jan 27 21:56:53 2016
|
||||
|
||||
|
||||
Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@
|
|||
|--------------------------------------------|
|
||||
|
||||
|
||||
Start: Mon Jan 25 07:24:24 2016
|
||||
End : Mon Jan 25 07:24:24 2016 $$$ Elapsed time: 00:00:00
|
||||
Start: Wed Jan 27 21:56:53 2016
|
||||
End : Wed Jan 27 21:56:53 2016 $$$ Elapsed time: 00:00:00
|
||||
===========================================================================
|
||||
Part [C:/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ Project_Summary
|
|||
|
||||
Project Name : 68030_tk
|
||||
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
|
||||
Project Fitted on : Mon Jan 25 07:24:24 2016
|
||||
Project Fitted on : Wed Jan 27 21:56:53 2016
|
||||
|
||||
Device : M4A5-128/64
|
||||
Package : 100TQFP
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ DATE Wed Jan 27 21:56:48 2016
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW
|
||||
#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ DATE Wed Jan 27 21:56:48 2016
|
||||
#$ MODULE 68030_tk
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW
|
||||
#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ DATE Wed Jan 27 21:56:48 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
|
||||
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ DATE Wed Jan 27 21:56:48 2016
|
||||
#$ MODULE BUS68030
|
||||
#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030
|
||||
UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 1/25/16;
|
||||
TIME = 07:24:24;
|
||||
DATE = 1/27/16;
|
||||
TIME = 21:56:53;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@ Parent = m4a5.lci;
|
|||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 1/25/16;
|
||||
TIME = 07:24:24;
|
||||
DATE = 1/27/16;
|
||||
TIME = 21:56:53;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ Signal Name Cross Reference File
|
|||
|
||||
ispLEVER Classic 1.8.00.04.29.14
|
||||
|
||||
Design '68030_tk' created Mon Jan 25 07:24:19 2016
|
||||
Design '68030_tk' created Wed Jan 27 21:56:48 2016
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ DATE Wed Jan 27 21:56:48 2016
|
||||
#$ TOOL EDIF2BLIF version IspLever 1.0
|
||||
#$ MODULE bus68030
|
||||
#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ A_12_ A_11_ A_10_ A_9_
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#$ TOOL ispLEVER Classic 1.8.00.04.29.14
|
||||
#$ DATE Mon Jan 25 07:24:19 2016
|
||||
#$ DATE Wed Jan 27 21:56:48 2016
|
||||
#$ MODULE bus68030
|
||||
#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \
|
||||
# IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timeStamp 2016 1 25 7 24 13)
|
||||
(timeStamp 2016 1 27 21 56 45)
|
||||
(author "Synopsys, Inc.")
|
||||
(program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R"))
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Mon Jan 25 07:24:04 2016
|
||||
#-- Written on Wed Jan 27 21:56:36 2016
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
6669
Logic/BUS68030.srm
6669
Logic/BUS68030.srm
File diff suppressed because it is too large
Load Diff
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Mon Jan 25 07:24:12 2016
|
||||
#Wed Jan 27 21:56:43 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -51,7 +51,7 @@ State machine has 8 reachable states with original encodings of:
|
|||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:12 2016
|
||||
# Wed Jan 27 21:56:44 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
|
|
@ -61,7 +61,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
# Wed Jan 27 21:56:45 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -104,6 +104,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
# Wed Jan 27 21:56:45 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -18,9 +18,9 @@
|
|||
<BScanLen>1</BScanLen>
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk-50MHz.jed</File>
|
||||
<FileTime>10/10/15 21:57:01</FileTime>
|
||||
<JedecChecksum>0x5646</JedecChecksum>
|
||||
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
|
||||
<FileTime>01/25/16 07:24:24</FileTime>
|
||||
<JedecChecksum>0x2728</JedecChecksum>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ Section Member Rename Array-Notation Array Number
|
|||
Port FC_0_ FC[0] 3 1
|
||||
End
|
||||
Section Cross Reference File
|
||||
Design 'BUS68030' created Mon Jan 25 07:24:19 2016
|
||||
Design 'BUS68030' created Wed Jan 27 21:56:48 2016
|
||||
Type New Name Original Name
|
||||
// ----------------------------------------------------------------------
|
||||
Inst i_z3S3S AS_030
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Mon Jan 25 07:24:12 2016
|
||||
#Wed Jan 27 21:56:43 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
|
@ -51,7 +51,7 @@ State machine has 8 reachable states with original encodings of:
|
|||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:12 2016
|
||||
# Wed Jan 27 21:56:44 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
|
|
@ -61,49 +61,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
001 -> 00000011
|
||||
010 -> 00000101
|
||||
011 -> 00001001
|
||||
100 -> 00010001
|
||||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 78 uses
|
||||
BI_DIR 10 uses
|
||||
BUFTH 4 uses
|
||||
IBUF 46 uses
|
||||
OBUF 15 uses
|
||||
AND2 299 uses
|
||||
INV 261 uses
|
||||
OR2 27 uses
|
||||
XOR2 7 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
# Wed Jan 27 21:56:45 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -26,8 +26,8 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
|
|||
SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
|
||||
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
|
||||
SR<qM3="lkF8DHCVDRC"P(=""
|
||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
|
||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
|
||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jc3jn6U("
|
||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
|
||||
/>SqS<R"M=3MOF#M0N0C_soP"R=J"&k;F0ABtqid_jjh_Qa)_u &R4J0kF;>"/
|
||||
<SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>
|
||||
SR<qMF="s_HoH0M#_"FVR"P=&FJk0z;A1jnUdJj&k;F0"
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Mon Jan 25 07:24:12 2016
|
||||
#-- Written on Wed Jan 27 21:56:43 2016
|
||||
|
||||
|
||||
#project files
|
||||
|
|
|
|||
|
|
@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
|
|||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
# Wed Jan 27 21:56:45 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -36,6 +36,6 @@ Mapper successful!
|
|||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
# Wed Jan 27 21:56:45 2016
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Real Time">
|
||||
<data>0h:00m:00s</data>
|
||||
<data>0h:00m:01s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1453703052</data>
|
||||
<data type="timestamp">1453928204</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>105MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1453703054</data>
|
||||
<data type="timestamp">1453928205</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
<html><body><samp><pre>
|
||||
<!@TC:1453703052>
|
||||
<!@TC:1453928203>
|
||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: C:\ispLever\synpbase
|
||||
#OS: Windows 7 6.2
|
||||
|
|
@ -8,34 +8,34 @@
|
|||
#Implementation: logic
|
||||
|
||||
<a name=compilerReport1>$ Start of Compile</a>
|
||||
#Mon Jan 25 07:24:12 2016
|
||||
#Wed Jan 27 21:56:43 2016
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1453703052> | Running in 64-bit mode
|
||||
@N: : <!@TM:1453928204> | Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1453703052> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453703052> | Top entity is set to BUS68030.
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1453928204> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453928204> | Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453703052> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1453703052> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1453703052> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1453703052> | Signal clk_out_pre is undriven </font>
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453928204> | Synthesizing work.bus68030.behavioral
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1453928204> | Using sequential encoding for type sm_e
|
||||
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1453928204> | Using sequential encoding for type sm_68000
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1453928204> | Signal clk_out_pre is undriven </font>
|
||||
Post processing for work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1453703052> | Pruning register CLK_000_D4_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1453703052> | Pruning register CLK_000_D3_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1453703052> | Pruning register CLK_000_D2_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:34:126:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1453703052> | Pruning register CLK_OUT_EXP_INT_1 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1453703052> | Pruning register CLK_OUT_PRE_25_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1453703052> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:61:134:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1453703052> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453703052> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Trying to extract state machine for register SM_AMIGA
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Pruning register DS_030_D0_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1453928204> | Pruning register CLK_000_D4_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1453928204> | Pruning register CLK_000_D3_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1453928204> | Pruning register CLK_000_D2_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:34:126:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1453928204> | Pruning register CLK_OUT_EXP_INT_1 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1453928204> | Pruning register CLK_OUT_PRE_25_3 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1453928204> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:61:134:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1453928204> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453928204> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -46,24 +46,24 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703052> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1453703052> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928204> | Trying to extract state machine for register cpu_est
|
||||
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1453928204> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:12 2016
|
||||
# Wed Jan 27 21:56:44 2016
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1453703053> | Running in 64-bit mode
|
||||
@N: : <!@TM:1453928205> | Running in 64-bit mode
|
||||
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:13 2016
|
||||
# Wed Jan 27 21:56:45 2016
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
|
@ -71,8 +71,8 @@ Map & Optimize Report
|
|||
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1453703054> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N::@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453703054> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1453928205> | Running in 64-bit mode.
|
||||
@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N::@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453928205> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
|
|
@ -83,7 +83,7 @@ original code -> new code
|
|||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453703054> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453928205> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||
---------------------------------------
|
||||
<a name=resourceUsage3>Resource Usage Report</a>
|
||||
|
||||
|
|
@ -99,14 +99,14 @@ OR2 27 uses
|
|||
XOR2 7 uses
|
||||
|
||||
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1453703054> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1453928205> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Mon Jan 25 07:24:14 2016
|
||||
# Wed Jan 27 21:56:45 2016
|
||||
|
||||
###########################################################]
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (07:24 25-Jan)</a>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (21:56 27-Jan)</a>
|
||||
<ul ></ul></li> </ul>
|
||||
</li>
|
||||
</ul>
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
Synopsys, Inc.
|
||||
Version I-2014.03LC
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Mon Jan 25 07:24:12 2016
|
||||
Written on Wed Jan 27 21:56:43 2016
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -36,9 +36,9 @@
|
|||
<td>13</td>
|
||||
<td>0</td>
|
||||
<td>-</td>
|
||||
<td>0m:00s</td>
|
||||
<td>0m:01s</td>
|
||||
<td>-</td>
|
||||
<td><font size="-1">25.01.2016</font><br/><font size="-2">07:24:12</font></td>
|
||||
<td><font size="-1">27.01.2016</font><br/><font size="-2">21:56:44</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
|
|
@ -49,12 +49,12 @@
|
|||
<td>0m:00s</td>
|
||||
<td>0m:00s</td>
|
||||
<td>105MB</td>
|
||||
<td><font size="-1">25.01.2016</font><br/><font size="-2">07:24:14</font></td>
|
||||
<td><font size="-1">27.01.2016</font><br/><font size="-2">21:56:45</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Multi-srs Generator</td>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">25.01.2016</font><br/><font size="-2">07:24:13</font></td> </tbody>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">27.01.2016</font><br/><font size="-2">21:56:45</font></td> </tbody>
|
||||
</table>
|
||||
</td></tr></table></body>
|
||||
</html>
|
||||
|
|
@ -9,7 +9,7 @@
|
|||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453703040
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453928190
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@
|
|||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453703040
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453928190
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
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Loading…
Reference in New Issue