Wing Commander works but generally instable?!

Logic/68030-68000-bus.vhd

@@ -319,8 +319,8 @@ begin
 
 		
 			--interrupt buffering to avoid ghost interrupts
-			if(CLK_000_NE='1')then
-			--if(CLK_000_D1='0' and CLK_000_D0='1')then
+			--if(CLK_000_NE='1')then
+			if(CLK_000_D0='0' and CLK_000_D1='1')then
 				IPL_030<=IPL;			
 			end if;
 		
@@ -499,17 +499,24 @@ begin
 			CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
 		end if;
 	end process process_33_clk; 
-	AMIGA_BUS_ENABLE_LOW <= '1';
 
 	
 
 	--output clock assignment
 	CLK_DIV_OUT	<= CLK_OUT_INT;
 	CLK_EXP		<= CLK_OUT_INT;
-	--CLK_DIV_OUT	<= CLK_OUT_PRE_33;
-	--CLK_EXP		<= CLK_OUT_PRE_33;
-	AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
+
+	-- bus drivers
+	AMIGA_ADDR_ENABLE	<= AMIGA_BUS_ENABLE_INT;
 	AMIGA_BUS_ENABLE_HIGH <= AMIGA_BUS_ENABLE_INT;
+	AMIGA_BUS_ENABLE_LOW <= '1';
+	AMIGA_BUS_DATA_DIR 	 <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
+							'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
+							'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
+							'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
+							'0'; --Point towarts TK
+	
+	
 	--dma stuff
 	DTACK	<= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
 					DSACK1;
@@ -533,20 +540,11 @@ begin
 
 
 
-	--cache inhibit: For now: disable
-	CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE
-			--'1' WHEN A(31 downto 20) = x"002" ELSE
-			--'1' WHEN A(31 downto 20) = x"004" ELSE
-			'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE
-			'0';
+	--cache inhibit:  Tristate for expansion (it decides) and off for the Amiga 
+	CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
+			'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides)
+			'0'; --off for the Amiga
 
-	--bus buffers
-	AMIGA_BUS_DATA_DIR 	 <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
-							'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
-							'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
-							'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
-							'0'; --Point towarts TK
-	--AMIGA_BUS_ENABLE_LOW <= CLK_OUT_NE; --for now: allways off
 		
 	--e and VMA		
 	E		<= cpu_est(3);

Logic/68030_TK.STY

@@ -1,6 +1,6 @@
-[synthesis-type]
-tool=Synplify
 [STRATEGY-LIST]
 Normal=True, 1385910337
 [TOUCHED-REPORT]
 Design.tt4File=1405595332
+[synthesis-type]
+tool=Synplify

Logic/68030_tk.crf

@@ -1,7 +1,7 @@
 // Signal Name Cross Reference File
 // ispLEVER Classic 1.7.00.05.28.13
 
-// Design '68030_tk' created Fri Jul 18 14:05:32 2014
+// Design '68030_tk' created Sat Aug 09 13:04:43 2014
 
 
 // LEGEND:  '>'  Functional Block Port Separator

Logic/68030_tk.ipr

@@ -1 +1 @@
-<LATTICE_ENCRYPTED_BLIF>3236<332f[6P(
+<LATTICE_ENCRYPTED_BLIF>4901<01Y{x}p

Logic/BUS68030.prj

@@ -1,6 +1,6 @@
 #-- Lattice Semiconductor Corporation Ltd.
 #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
-#-- Written on Fri Jul 18 14:05:26 2014
+#-- Written on Sat Aug 09 13:04:37 2014
 
 
 #device options

Logic/Programming.xcf

@@ -19,8 +19,8 @@
 				<BScanVal>0</BScanVal>
 			</Bypass>
 			<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
-			<FileTime>07/18/14 14:05:38</FileTime>
-			<JedecChecksum>0xE862</JedecChecksum>
+			<FileTime>08/09/14 13:04:48</FileTime>
+			<JedecChecksum>0xF4B9</JedecChecksum>
 			<Operation>Erase,Program,Verify</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>

Logic/bus68030.srf

@@ -6,7 +6,7 @@
 #Implementation: logic
 
 $ Start of Compile
-#Fri Jul 18 14:05:26 2014
+#Sat Aug 09 13:04:37 2014
 
 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
 @N|Running in 64-bit mode
@@ -58,7 +58,7 @@ State machine has 11 reachable states with original encodings of:
    1111
 @END
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Jul 18 14:05:26 2014
+# Sat Aug 09 13:04:37 2014
 
 ###########################################################]
 Map & Optimize Report
@@ -101,9 +101,9 @@ BI_DIR          13 uses
 IBUF            30 uses
 OBUF            16 uses
 BUFTH           1 use
-AND2            203 uses
-INV             161 uses
-OR2             21 uses
+AND2            196 uses
+INV             160 uses
+OR2             22 uses
 XOR2            2 uses
 
 
@@ -114,6 +114,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Jul 18 14:05:28 2014
+# Sat Aug 09 13:04:39 2014
 
 ###########################################################]

Logic/run_options.txt

@@ -1,7 +1,7 @@
 #--  Synopsys, Inc.
 #--  Version G-2012.09LC-SP1 
 #--  Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
-#--  Written on Fri Jul 18 14:05:26 2014
+#--  Written on Sat Aug 09 13:04:37 2014
 
 
 #project files

Logic/synlog/bus68030_fpga_mapper.srr

@@ -36,9 +36,9 @@ BI_DIR          13 uses
 IBUF            30 uses
 OBUF            16 uses
 BUFTH           1 use
-AND2            203 uses
-INV             161 uses
-OR2             21 uses
+AND2            196 uses
+INV             160 uses
+OR2             22 uses
 XOR2            2 uses
 
 
@@ -49,6 +49,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Fri Jul 18 14:05:28 2014
+# Sat Aug 09 13:04:39 2014
 
 ###########################################################]

Logic/synlog/report/BUS68030_compiler_errors.txt

@@ -1,3 +1,3 @@
-@E: CG119 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":426:92:426:93|Expecting closing )
+@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":410:31:410:31|No identifier "dtack_d" in scope
 @E|Parse errors encountered - exiting
 

Logic/synlog/report/BUS68030_compiler_runstatus.xml

@@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
   <data>-</data>
   </info>
 			<info name="Date &amp;Time">
-  <data type="timestamp">1405685126</data>
+  <data type="timestamp">1407582277</data>
   </info>
 			</job_info>
 </job_run_status>

Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml

@@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
 <data>96MB</data>
 </info>
 <info name="Date &amp; Time">
-<data type="timestamp">1405685128</data>
+<data type="timestamp">1407582279</data>
 </info>
 </job_info>
 </job_run_status>

Logic/syntmp/run_option.xml

@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version G-2012.09LC-SP1 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Fri Jul 18 14:05:26 2014
+  Written on Sat Aug 09 13:04:37 2014
 
 
 --> 

Logic/synwork/BUS68030_compiler.fdep

@@ -10,7 +10,7 @@
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1405685121
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407582273
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)

Logic/synwork/BUS68030_compiler.fdeporig

@@ -10,7 +10,7 @@
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1405685121
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407582273
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)