mirror of https://github.com/kr239/68030tk.git
Wing Commander works but generally instable?!
This commit is contained in:
parent
f3a861ba82
commit
c402614193
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@ -319,8 +319,8 @@ begin
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--interrupt buffering to avoid ghost interrupts
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--interrupt buffering to avoid ghost interrupts
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if(CLK_000_NE='1')then
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--if(CLK_000_NE='1')then
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--if(CLK_000_D1='0' and CLK_000_D0='1')then
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if(CLK_000_D0='0' and CLK_000_D1='1')then
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IPL_030<=IPL;
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IPL_030<=IPL;
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end if;
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end if;
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@ -499,17 +499,24 @@ begin
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CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
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CLK_OUT_PRE_33 <= not CLK_OUT_PRE_33;
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end if;
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end if;
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end process process_33_clk;
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end process process_33_clk;
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AMIGA_BUS_ENABLE_LOW <= '1';
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--output clock assignment
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--output clock assignment
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CLK_DIV_OUT <= CLK_OUT_INT;
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CLK_DIV_OUT <= CLK_OUT_INT;
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CLK_EXP <= CLK_OUT_INT;
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CLK_EXP <= CLK_OUT_INT;
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--CLK_DIV_OUT <= CLK_OUT_PRE_33;
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--CLK_EXP <= CLK_OUT_PRE_33;
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-- bus drivers
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AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
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AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
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AMIGA_BUS_ENABLE_HIGH <= AMIGA_BUS_ENABLE_INT;
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AMIGA_BUS_ENABLE_HIGH <= AMIGA_BUS_ENABLE_INT;
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AMIGA_BUS_ENABLE_LOW <= '1';
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AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
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'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
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'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
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'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
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'0'; --Point towarts TK
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--dma stuff
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--dma stuff
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DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
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DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' OR AS_000_DMA ='1' else
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DSACK1;
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DSACK1;
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@ -533,20 +540,11 @@ begin
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--cache inhibit: For now: disable
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--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
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CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE
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CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
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--'1' WHEN A(31 downto 20) = x"002" ELSE
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'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides)
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--'1' WHEN A(31 downto 20) = x"004" ELSE
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'0'; --off for the Amiga
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'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE = '0' ELSE
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'0';
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--bus buffers
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AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
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'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
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'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
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'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
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'0'; --Point towarts TK
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--AMIGA_BUS_ENABLE_LOW <= CLK_OUT_NE; --for now: allways off
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--e and VMA
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--e and VMA
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E <= cpu_est(3);
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E <= cpu_est(3);
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@ -1,6 +1,6 @@
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[synthesis-type]
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tool=Synplify
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[STRATEGY-LIST]
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[STRATEGY-LIST]
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Normal=True, 1385910337
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Normal=True, 1385910337
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[TOUCHED-REPORT]
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[TOUCHED-REPORT]
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Design.tt4File=1405595332
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Design.tt4File=1405595332
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[synthesis-type]
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tool=Synplify
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3644
Logic/68030_TK.tcl
3644
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
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@ -1,7 +1,7 @@
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// Signal Name Cross Reference File
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// Signal Name Cross Reference File
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// ispLEVER Classic 1.7.00.05.28.13
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// ispLEVER Classic 1.7.00.05.28.13
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// Design '68030_tk' created Fri Jul 18 14:05:32 2014
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// Design '68030_tk' created Sat Aug 09 13:04:43 2014
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// LEGEND: '>' Functional Block Port Separator
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// LEGEND: '>' Functional Block Port Separator
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@ -1 +1 @@
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<LATTICE_ENCRYPTED_BLIF>3236<332f[6P(
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<LATTICE_ENCRYPTED_BLIF>4901<01Y{x}p
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1110
Logic/68030_tk.jed
1110
Logic/68030_tk.jed
File diff suppressed because it is too large
Load Diff
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@ -1,6 +1,6 @@
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#-- Lattice Semiconductor Corporation Ltd.
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#-- Lattice Semiconductor Corporation Ltd.
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#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
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#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
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#-- Written on Fri Jul 18 14:05:26 2014
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#-- Written on Sat Aug 09 13:04:37 2014
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#device options
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#device options
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@ -19,8 +19,8 @@
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<BScanVal>0</BScanVal>
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<BScanVal>0</BScanVal>
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</Bypass>
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</Bypass>
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<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
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<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
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<FileTime>07/18/14 14:05:38</FileTime>
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<FileTime>08/09/14 13:04:48</FileTime>
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<JedecChecksum>0xE862</JedecChecksum>
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<JedecChecksum>0xF4B9</JedecChecksum>
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<Operation>Erase,Program,Verify</Operation>
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<Operation>Erase,Program,Verify</Operation>
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<Option>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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@ -6,7 +6,7 @@
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#Implementation: logic
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#Implementation: logic
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$ Start of Compile
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$ Start of Compile
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#Fri Jul 18 14:05:26 2014
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#Sat Aug 09 13:04:37 2014
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Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
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Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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@ -58,7 +58,7 @@ State machine has 11 reachable states with original encodings of:
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1111
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1111
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@END
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@END
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Fri Jul 18 14:05:26 2014
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# Sat Aug 09 13:04:37 2014
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###########################################################]
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###########################################################]
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Map & Optimize Report
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Map & Optimize Report
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@ -101,9 +101,9 @@ BI_DIR 13 uses
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IBUF 30 uses
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IBUF 30 uses
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OBUF 16 uses
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OBUF 16 uses
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BUFTH 1 use
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BUFTH 1 use
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AND2 203 uses
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AND2 196 uses
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INV 161 uses
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INV 160 uses
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OR2 21 uses
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OR2 22 uses
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XOR2 2 uses
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XOR2 2 uses
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@ -114,6 +114,6 @@ Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Fri Jul 18 14:05:28 2014
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# Sat Aug 09 13:04:39 2014
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###########################################################]
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###########################################################]
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@ -1,7 +1,7 @@
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#-- Synopsys, Inc.
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#-- Synopsys, Inc.
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#-- Version G-2012.09LC-SP1
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#-- Version G-2012.09LC-SP1
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#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
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#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
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#-- Written on Fri Jul 18 14:05:26 2014
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#-- Written on Sat Aug 09 13:04:37 2014
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#project files
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#project files
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@ -36,9 +36,9 @@ BI_DIR 13 uses
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IBUF 30 uses
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IBUF 30 uses
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OBUF 16 uses
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OBUF 16 uses
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BUFTH 1 use
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BUFTH 1 use
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AND2 203 uses
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AND2 196 uses
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INV 161 uses
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INV 160 uses
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OR2 21 uses
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OR2 22 uses
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XOR2 2 uses
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XOR2 2 uses
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@ -49,6 +49,6 @@ Mapper successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Fri Jul 18 14:05:28 2014
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# Sat Aug 09 13:04:39 2014
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###########################################################]
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###########################################################]
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@ -1,3 +1,3 @@
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@E: CG119 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":426:92:426:93|Expecting closing )
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@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":410:31:410:31|No identifier "dtack_d" in scope
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@E|Parse errors encountered - exiting
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@E|Parse errors encountered - exiting
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@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
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<data>-</data>
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<data>-</data>
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</info>
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</info>
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<info name="Date &Time">
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<info name="Date &Time">
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<data type="timestamp">1405685126</data>
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<data type="timestamp">1407582277</data>
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</info>
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</info>
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</job_info>
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</job_info>
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</job_run_status>
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</job_run_status>
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<data>96MB</data>
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<data>96MB</data>
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</info>
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</info>
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<info name="Date & Time">
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<info name="Date & Time">
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<data type="timestamp">1405685128</data>
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<data type="timestamp">1407582279</data>
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</info>
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</info>
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</job_info>
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</job_info>
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</job_run_status>
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</job_run_status>
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@ -3,7 +3,7 @@
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Synopsys, Inc.
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Synopsys, Inc.
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Version G-2012.09LC-SP1
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Version G-2012.09LC-SP1
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Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
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Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
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Written on Fri Jul 18 14:05:26 2014
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Written on Sat Aug 09 13:04:37 2014
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-->
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-->
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@ -10,7 +10,7 @@
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
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#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1405685121
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#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407582273
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0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
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0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
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# Dependency Lists (Uses list)
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# Dependency Lists (Uses list)
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
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#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
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#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1405685121
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#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407582273
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0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
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0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
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# Dependency Lists (Uses list)
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# Dependency Lists (Uses list)
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