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68030tk
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Updated some JEDs

This commit is contained in:
MHeinrichs 2016-10-26 22:26:40 +02:00
parent ba4bc7b8fc
commit e79ab9bae7
47 changed files with 4565 additions and 3955 deletions
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366
Logic/68030_TK.tcl
View File

@ -415062,3 +415062,369 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
########## Tcl recorder end at 10/15/16 23:47:55 ###########
########## Tcl recorder starts at 10/26/16 21:16:44 ##########
# Commands to make the Process:
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/26/16 21:16:44 ###########
########## Tcl recorder starts at 10/26/16 21:16:44 ##########
# Commands to make the Process:
# JEDEC File
if [catch {open BUS68030.cmd w} rspFile] {
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
} else {
puts $rspFile "STYFILENAME: 68030_tk.sty
PROJECT: BUS68030
WORKING_PATH: \"$proj_dir\"
MODULE: BUS68030
VHDL_FILE_LIST: 68030-68000-bus.vhd
OUTPUT_FILE_NAME: BUS68030
SUFFIX_NAME: edi
PART: M4A5-128/64-10VC
"
close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete BUS68030.cmd
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [catch {open 68030_tk.rsp w} rspFile] {
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
} else {
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
"
close $rspFile
}
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete 68030_tk.rsp
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/26/16 21:16:44 ###########
########## Tcl recorder starts at 10/26/16 22:25:56 ##########
# Commands to make the Process:
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/26/16 22:25:56 ###########
########## Tcl recorder starts at 10/26/16 22:25:56 ##########
# Commands to make the Process:
# JEDEC File
if [catch {open BUS68030.cmd w} rspFile] {
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
} else {
puts $rspFile "STYFILENAME: 68030_tk.sty
PROJECT: BUS68030
WORKING_PATH: \"$proj_dir\"
MODULE: BUS68030
VHDL_FILE_LIST: 68030-68000-bus.vhd
OUTPUT_FILE_NAME: BUS68030
SUFFIX_NAME: edi
PART: M4A5-128/64-10VC
"
close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete BUS68030.cmd
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [catch {open 68030_tk.rsp w} rspFile] {
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
} else {
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
"
close $rspFile
}
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete 68030_tk.rsp
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/26/16 22:25:56 ###########

980
Logic/68030_tk-25new.jed
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File diff suppressed because it is too large Load Diff

968
Logic/68030_tk-50Mhz-New.jed
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.bl2
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ MODULE 68030_tk
#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \
# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \

2
Logic/68030_tk.bl3
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ MODULE 68030_tk
#$ PINS 61 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \
# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \

2
Logic/68030_tk.crf
View File

@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 2.0.00.17.20.15
// Design '68030_tk' created Sat Oct 15 23:48:24 2016
// Design '68030_tk' created Wed Oct 26 22:26:25 2016
// LEGEND: '>' Functional Block Port Separator

2
Logic/68030_tk.eq3
View File

@ -2,7 +2,7 @@
Copyright(C), 1992-2015, Lattice Semiconductor Corp.
All Rights Reserved.
Design bus68030 created Sat Oct 15 23:48:24 2016
Design bus68030 created Wed Oct 26 22:26:25 2016
P-Terms Fan-in Fan-out Type Name (attributes)

2
Logic/68030_tk.ipr
View File

@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>513;200c7,FKup
<LATTICE_ENCRYPTED_BLIF>5970501@qV_IP

2
Logic/68030_tk.jed
View File

@ -10,7 +10,7 @@ AUTHOR:
PATTERN:
COMPANY:
REVISION:
DATE: Sat Oct 15 23:48:29 2016
DATE: Wed Oct 26 22:26:30 2016
ABEL mach447a
*

4
Logic/68030_tk.lco
View File

@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 10/15/16;
TIME = 23:48:29;
DATE = 10/26/16;
TIME = 22:26:30;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;

245
Logic/68030_tk.out
View File

@ -1926,6 +1926,251 @@
317 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
314 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
60 CLK_OSZI 9 -1 0 60 -1
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1
57 FC_1_ 1 -1 -1 3 4 5 7 57 -1
56 FC_0_ 1 -1 -1 3 4 5 7 56 -1
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
66 IPL_0_ 1 -1 -1 2 1 6 66 -1
59 A_1_ 1 -1 -1 2 2 5 59 -1
55 IPL_1_ 1 -1 -1 2 1 3 55 -1
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
67 IPL_2_ 1 -1 -1 1 1 67 -1
63 CLK_030 1 -1 -1 1 0 63 -1
35 VPA 1 -1 -1 1 0 35 -1
29 DTACK 1 -1 -1 1 1 29 -1
20 BG_030 1 -1 -1 1 3 20 -1
10 CLK_000 1 -1 -1 1 2 10 -1
117 "number of signals after reading design file"
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
81 AS_030 5 -1 7 5 2 3 4 5 7 81 -1 1 0 21
79 RW_000 5 340 7 3 0 4 6 79 -1 4 0 21
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21
70 RW 5 345 6 2 5 7 70 -1 2 0 21
78 SIZE_1_ 5 338 7 1 2 78 -1 3 0 21
69 SIZE_0_ 5 343 6 1 2 69 -1 3 0 21
68 A_0_ 5 346 6 1 2 68 -1 3 0 21
40 BERR 5 -1 4 1 5 40 -1 1 0 21
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
8 IPL_030_2_ 5 339 1 0 8 -1 9 0 21
7 IPL_030_0_ 5 348 1 0 7 -1 9 0 21
6 IPL_030_1_ 5 347 1 0 6 -1 9 0 21
82 BGACK_030 5 342 7 0 82 -1 3 0 21
34 VMA 5 344 3 0 34 -1 3 0 21
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
28 BG_000 5 341 3 0 28 -1 2 0 21
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
80 DSACK1 0 7 0 80 -1 1 0 21
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
2 RESET 0 1 0 2 -1 1 0 21
342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
311 CLK_000_D_0_ 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
310 CLK_000_D_1_ 3 -1 7 6 0 1 3 5 6 7 -1 -1 1 0 21
323 SM_AMIGA_6_ 3 -1 1 5 1 2 3 5 7 -1 -1 3 0 21
301 inst_BGACK_030_INT_D 3 -1 4 5 1 2 5 6 7 -1 -1 1 0 21
300 inst_AS_030_000_SYNC 3 -1 2 3 1 2 3 -1 -1 7 0 21
295 cpu_est_3_ 3 -1 6 3 3 5 6 -1 -1 4 0 21
293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 21
336 SM_AMIGA_i_7_ 3 -1 1 3 1 2 7 -1 -1 3 1 21
296 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 21
299 inst_AS_030_D0 3 -1 4 3 2 3 4 -1 -1 1 0 21
294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 1 1 21
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
335 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 5 0 21
344 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21
326 SM_AMIGA_0_ 3 -1 7 2 1 7 -1 -1 3 0 21
325 SM_AMIGA_1_ 3 -1 0 2 0 7 -1 -1 3 0 21
324 SM_AMIGA_4_ 3 -1 3 2 3 5 -1 -1 3 0 21
321 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 3 0 21
320 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21
332 inst_AS_000_INT 3 -1 3 2 3 4 -1 -1 2 0 21
322 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21
313 inst_CLK_OUT_PRE_25 3 -1 0 2 0 2 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21
314 inst_CLK_OUT_PRE_D 3 -1 2 2 1 6 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_50 3 -1 2 2 0 2 -1 -1 1 0 21
307 CLK_000_D_3_ 3 -1 2 2 1 7 -1 -1 1 0 21
306 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21
348 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21
347 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21
339 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
330 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
334 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21
340 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
327 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
346 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
343 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
338 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
333 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 3 0 21
304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
345 RN_RW 3 70 6 1 6 70 -1 2 0 21
341 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
337 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
331 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21
329 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
328 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
319 CLK_000_D_4_ 3 -1 7 1 1 -1 -1 1 0 21
318 CLK_000_D_2_ 3 -1 0 1 2 -1 -1 1 0 21
317 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21
316 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21
315 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21
308 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21
60 CLK_OSZI 9 -1 0 60 -1
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1
13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1
96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1
95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1
94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1
58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1
57 FC_1_ 1 -1 -1 3 2 4 7 57 -1
56 FC_0_ 1 -1 -1 3 2 4 7 56 -1
90 FPU_SENSE 1 -1 -1 2 4 7 90 -1
67 IPL_2_ 1 -1 -1 2 1 3 67 -1
59 A_1_ 1 -1 -1 2 1 5 59 -1
55 IPL_1_ 1 -1 -1 2 0 1 55 -1
27 BGACK_000 1 -1 -1 2 4 7 27 -1
93 A_DECODE_21_ 1 -1 -1 1 4 93 -1
92 A_DECODE_20_ 1 -1 -1 1 4 92 -1
84 A_DECODE_23_ 1 -1 -1 1 4 84 -1
83 A_DECODE_22_ 1 -1 -1 1 4 83 -1
66 IPL_0_ 1 -1 -1 1 1 66 -1
63 CLK_030 1 -1 -1 1 0 63 -1
35 VPA 1 -1 -1 1 6 35 -1
29 DTACK 1 -1 -1 1 0 29 -1
20 BG_030 1 -1 -1 1 3 20 -1
10 CLK_000 1 -1 -1 1 6 10 -1
116 "number of signals after reading design file"
"sig sig sig pair blk fan PT xor sync"
"num name type sig num out pin node cnt PT type"
"--- ---- ---- ---- --- --- --- ---- --- --- ----"
81 AS_030 5 -1 7 6 1 2 3 4 5 7 81 -1 1 0 21
79 RW_000 5 339 7 3 0 4 6 79 -1 4 0 21
41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21
31 UDS_000 5 -1 3 3 0 6 7 31 -1 1 0 21
30 LDS_000 5 -1 3 3 0 6 7 30 -1 1 0 21
70 RW 5 344 6 2 1 7 70 -1 2 0 21
40 BERR 5 -1 4 2 0 3 40 -1 1 0 21
78 SIZE_1_ 5 337 7 1 5 78 -1 3 0 21
69 SIZE_0_ 5 341 6 1 5 69 -1 3 0 21
68 A_0_ 5 345 6 1 5 68 -1 3 0 21
18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21
17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21
16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21
15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21
14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21
5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21
4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21
3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21
8 IPL_030_2_ 5 338 1 0 8 -1 9 0 21
7 IPL_030_0_ 5 347 1 0 7 -1 9 0 21
6 IPL_030_1_ 5 346 1 0 6 -1 9 0 21
82 BGACK_030 5 342 7 0 82 -1 3 0 21
34 VMA 5 343 3 0 34 -1 3 0 21
65 E 0 6 0 65 -1 2 0 21
47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21
33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21
28 BG_000 5 340 3 0 28 -1 2 0 21
97 DS_030 0 0 0 97 -1 1 0 21
91 AVEC 0 0 0 91 -1 1 0 21
80 DSACK1 0 7 0 80 -1 1 0 21
77 FPU_CS 0 7 0 77 -1 1 0 21
64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
46 CIIN 0 4 0 46 -1 1 0 21
32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21
19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
9 CLK_EXP 0 1 0 9 -1 1 0 21
2 RESET 0 1 0 2 -1 1 0 21
342 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21
309 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21
311 CLK_000_D_0_ 3 -1 2 7 0 1 2 3 5 6 7 -1 -1 1 0 21
310 CLK_000_D_1_ 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 21
322 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21
301 inst_BGACK_030_INT_D 3 -1 4 4 2 5 6 7 -1 -1 1 0 21
300 inst_AS_030_000_SYNC 3 -1 5 3 2 3 5 -1 -1 7 0 21
296 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21
294 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 4 0 21
335 SM_AMIGA_i_7_ 3 -1 2 3 2 5 7 -1 -1 3 1 21
295 cpu_est_0_ 3 -1 6 3 0 3 6 -1 -1 3 0 21
299 inst_AS_030_D0 3 -1 4 3 3 4 5 -1 -1 1 0 21
293 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 1 1 21
302 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21
334 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21
333 SM_AMIGA_3_ 3 -1 3 2 0 3 -1 -1 5 0 21
343 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21
332 SM_AMIGA_5_ 3 -1 2 2 2 3 -1 -1 3 0 21
325 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 3 0 21
324 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
323 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 3 0 21
320 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 3 0 21
319 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21
331 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21
321 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21
298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21
297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21
313 inst_CLK_OUT_PRE_D 3 -1 3 2 1 6 -1 -1 1 0 21
312 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21
308 inst_DTACK_D0 3 -1 1 2 0 3 -1 -1 1 0 21
307 CLK_000_D_3_ 3 -1 3 2 1 2 -1 -1 1 0 21
306 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21
347 RN_IPL_030_0_ 3 7 1 1 1 7 -1 9 0 21
346 RN_IPL_030_1_ 3 6 1 1 1 6 -1 9 0 21
338 RN_IPL_030_2_ 3 8 1 1 1 8 -1 9 0 21
303 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21
329 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21
339 RN_RW_000 3 79 7 1 7 79 -1 4 0 21
326 RST_DLY_0_ 3 -1 6 1 6 -1 -1 4 0 21
305 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21
345 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21
341 RN_SIZE_0_ 3 69 6 1 6 69 -1 3 0 21
337 RN_SIZE_1_ 3 78 7 1 7 78 -1 3 0 21
304 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21
344 RN_RW 3 70 6 1 6 70 -1 2 0 21
340 RN_BG_000 3 28 3 1 3 28 -1 2 0 21
336 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21
330 inst_DSACK1_INT 3 -1 7 1 7 -1 -1 2 0 21
328 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21
327 RST_DLY_1_ 3 -1 6 1 6 -1 -1 2 1 21
318 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21
317 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21
316 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21
315 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21
314 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21
60 CLK_OSZI 9 -1 0 60 -1
85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1

2
Logic/68030_tk.plc
View File

@ -8,7 +8,7 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
; DATE Sat Oct 15 23:48:29 2016
; DATE Wed Oct 26 22:26:30 2016
Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143

4
Logic/68030_tk.prd
View File

@ -5,8 +5,8 @@
|--------------------------------------------|
Start: Sat Oct 15 23:48:29 2016
End : Sat Oct 15 23:48:29 2016 $$$ Elapsed time: 00:00:00
Start: Wed Oct 26 22:26:30 2016
End : Wed Oct 26 22:26:30 2016 $$$ Elapsed time: 00:00:00
===========================================================================
Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]

2
Logic/68030_tk.rpt
View File

@ -12,7 +12,7 @@ Project_Summary
Project Name : 68030_tk
Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic
Project Fitted on : Sat Oct 15 23:48:29 2016
Project Fitted on : Wed Oct 26 22:26:30 2016
Device : M4A5-128/64
Package : 100TQFP

2
Logic/68030_tk.tt2
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ MODULE 68030_tk
#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 43 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_

2
Logic/68030_tk.tt3
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ MODULE 68030_tk
#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_1_ IPL_0_ FC_0_ A_1_ SIZE_1_ IPL_030_2_ RW_000 BG_000 SIZE_0_ BGACK_030 CLK_EXP VMA RW A_0_ IPL_030_1_ IPL_030_0_
#$ NODES 43 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_RESET_OUT CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_LDS_000_INT inst_DS_000_ENABLE inst_UDS_000_INT SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_030_H inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_

2
Logic/68030_tk.tt4
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ MODULE BUS68030
#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000
LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_

2
Logic/68030_tk.tte
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ MODULE BUS68030
#$ PINS 61 AHIGH_31_ A_DECODE_23_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000
LDS_000 nEXP_SPACE BERR BG_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_

4
Logic/68030_tk.vcl
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 10/15/16;
TIME = 23:48:29;
DATE = 10/26/16;
TIME = 22:26:30;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;

4
Logic/68030_tk.vco
View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 10/15/16;
TIME = 23:48:29;
DATE = 10/26/16;
TIME = 22:26:30;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;

2
Logic/68030_tk.xrf
View File

@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 2.0.00.17.20.15
Design '68030_tk' created Sat Oct 15 23:48:24 2016
Design '68030_tk' created Wed Oct 26 22:26:25 2016
LEGEND: '>' Functional Block Port Separator

BIN
Logic/68030tk-logik.zip Normal file
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Binary file not shown.

2
Logic/BUS68030.bl0
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@ -1,4 +1,4 @@
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ TOOL EDIF2BLIF version IspLever 1.0
#$ MODULE bus68030
#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ BGACK_000 AHIGH_29_ CLK_030 AHIGH_28_ CLK_000 AHIGH_27_ CLK_OSZI AHIGH_26_ CLK_DIV_OUT AHIGH_25_ CLK_EXP AHIGH_24_ FPU_CS A_DECODE_22_ FPU_SENSE A_DECODE_21_ DSACK1 A_DECODE_20_ DTACK A_DECODE_19_ AVEC A_DECODE_18_ E A_DECODE_17_ VPA A_DECODE_16_ VMA A_DECODE_15_ RST A_DECODE_14_ RESET A_DECODE_13_ RW A_DECODE_12_ AMIGA_ADDR_ENABLE A_DECODE_11_ AMIGA_BUS_DATA_DIR A_DECODE_10_ AMIGA_BUS_ENABLE_LOW A_DECODE_9_ AMIGA_BUS_ENABLE_HIGH A_DECODE_8_ CIIN A_DECODE_7_ A_DECODE_6_ A_DECODE_5_ A_DECODE_4_ A_DECODE_3_ A_DECODE_2_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ FC_0_ A_1_

2
Logic/BUS68030.bl1
View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 2.0.00.17.20.15
#$ DATE Sat Oct 15 23:48:24 2016
#$ DATE Wed Oct 26 22:26:25 2016
#$ MODULE bus68030
#$ PINS 75 SIZE_1_ AHIGH_31_ A_DECODE_23_ IPL_030_2_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 \
# DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 SIZE_0_ BGACK_030 AHIGH_30_ \

2
Logic/BUS68030.edi
View File

@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2016 10 15 23 48 19)
(timeStamp 2016 10 26 22 26 20)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R"))
)

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj
#-- Written on Sat Oct 15 23:47:55 2016
#-- Written on Wed Oct 26 22:25:56 2016
#device options

5817
Logic/BUS68030.srm
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File diff suppressed because it is too large Load Diff

8
Logic/BUS68030.srr
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Sat Oct 15 23:48:18 2016
#Wed Oct 26 22:26:19 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -47,7 +47,7 @@ State machine has 8 reachable states with original encodings of:
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:18 2016
# Wed Oct 26 22:26:19 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -57,7 +57,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:19 2016
# Wed Oct 26 22:26:20 2016
###########################################################]
Map & Optimize Report
@ -99,6 +99,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:19 2016
# Wed Oct 26 22:26:20 2016
###########################################################]

BIN
Logic/BUS68030.srs
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Binary file not shown.

2
Logic/bus68030.exf
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@ -54,7 +54,7 @@ Section Member Rename Array-Notation Array Number
Port FC_0_ FC[0] 3 1
End
Section Cross Reference File
Design 'BUS68030' created Sat Oct 15 23:48:24 2016
Design 'BUS68030' created Wed Oct 26 22:26:25 2016
Type New Name Original Name
// ----------------------------------------------------------------------
Inst i_z3737 AS_030

6
Logic/bus68030.srf
View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Sat Oct 15 23:48:18 2016
#Wed Oct 26 22:26:19 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N|Running in 64-bit mode
@ -47,7 +47,7 @@ State machine has 8 reachable states with original encodings of:
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:18 2016
# Wed Oct 26 22:26:19 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@ -57,6 +57,6 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:19 2016
# Wed Oct 26 22:26:20 2016
###########################################################]

2
Logic/dm/BUS68030_comp.xdm
View File

@ -27,7 +27,7 @@ SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
SR<qM3="lkF8DHCVDRC"P(=""
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j66n."
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjjjjj/j">S
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version I-2014.03LC
#-- Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\run_options.txt
#-- Written on Sat Oct 15 23:48:18 2016
#-- Written on Wed Oct 26 22:26:19 2016
#project files

2
Logic/synlog/BUS68030_multi_srs_gen.srr
View File

@ -5,6 +5,6 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:19 2016
# Wed Oct 26 22:26:20 2016
###########################################################]

2
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -35,6 +35,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:19 2016
# Wed Oct 26 22:26:20 2016
###########################################################]

2
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1476568098</data>
<data type="timestamp">1477513579</data>
</info>
</job_info>
</job_run_status>

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>105MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1476568099</data>
<data type="timestamp">1477513580</data>
</info>
</job_info>
</job_run_status>

52
Logic/syntmp/BUS68030_srr.htm
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<html><body><samp><pre>
<!@TC:1476568098>
<!@TC:1477513579>
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
#install: E:\ispLEVER_Classic2_0\synpbase
#OS: Windows 7 6.2
@ -8,30 +8,30 @@
#Implementation: logic
<a name=compilerReport1>$ Start of Compile</a>
#Sat Oct 15 23:48:18 2016
#Wed Oct 26 22:26:19 2016
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1476568098> | Running in 64-bit mode
@N: : <!@TM:1477513579> | Running in 64-bit mode
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1476568098> | Setting time resolution to ns
@N: : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1476568098> | Top entity is set to BUS68030.
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1477513579> | Setting time resolution to ns
@N: : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1477513579> | Top entity is set to BUS68030.
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd changed - recompiling
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1476568098> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1476568098> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1476568098> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1476568098> | Signal clk_out_pre is undriven </font>
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1477513579> | Synthesizing work.bus68030.behavioral
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:70:10:70:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(70)</a><!@TM:1477513579> | Using sequential encoding for type sm_e
@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:87:14:87:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(87)</a><!@TM:1477513579> | Using sequential encoding for type sm_68000
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:128:7:128:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(128)</a><!@TM:1477513579> | Signal clk_out_pre is undriven </font>
Post processing for work.bus68030.behavioral
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1476568098> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1476568098> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1476568098> | Pruning register BGACK_030_INT_PRE_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1476568098> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:126:36:126:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1476568098> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1476568098> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1476568098> | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1476568098> | Trying to extract state machine for register SM_AMIGA
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning register DS_030_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning register nEXP_SPACE_D0_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning register BGACK_030_INT_PRE_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1477513579> | Pruning register CLK_OUT_EXP_INT_1 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:126:36:126:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1477513579> | Pruning register CLK_OUT_PRE_25_3 </font>
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:154:2:154:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(154)</a><!@TM:1477513579> | Pruning register CLK_030_D0_2 </font>
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@W:CL271:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Pruning bits 12 to 5 of CLK_000_D_3(12 downto 0) -- not in use ... </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
000
@ -42,24 +42,24 @@ State machine has 8 reachable states with original encodings of:
101
110
111
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1476568098> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1476568098> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N:CL201:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513579> | Trying to extract state machine for register cpu_est
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:24:1:24:9:@W:CL246:@XP_MSG">68030-68000-bus.vhd(24)</a><!@TM:1477513579> | Input port bits 15 to 2 of a_decode(23 downto 2) are unused </font>
@END
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:18 2016
# Wed Oct 26 22:26:19 2016
###########################################################]
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@N: : <!@TM:1476568099> | Running in 64-bit mode
@N: : <!@TM:1477513580> | Running in 64-bit mode
File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_comp.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:19 2016
# Wed Oct 26 22:26:20 2016
###########################################################]
Map & Optimize Report
@ -67,8 +67,8 @@ Map & Optimize Report
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
Product Version I-2014.03LC
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1476568099> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1476568099> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1477513580> | Running in 64-bit mode.
@N: : <a href="c:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd:131:38:131:41:@N::@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1477513580> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
000 -> 00000000
@ -94,14 +94,14 @@ OR2 22 uses
XOR2 5 uses
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1476568099> | Timing Report not generated for this device, please use place and route tools for timing analysis.
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1477513580> | Timing Report not generated for this device, please use place and route tools for timing analysis.
I-2014.03LC
Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sat Oct 15 23:48:19 2016
# Wed Oct 26 22:26:20 2016
###########################################################]

2
Logic/syntmp/BUS68030_toc.htm
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@ -16,7 +16,7 @@
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
<ul rel="open" >
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\stdout.log" target="srrFrame" title="">Session Log (23:47 15-Oct)</a>
<li><a href="file:///C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\stdout.log" target="srrFrame" title="">Session Log (22:25 26-Oct)</a>
<ul ></ul></li> </ul>
</li>
</ul>

2
Logic/syntmp/run_option.xml
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@ -3,7 +3,7 @@
Synopsys, Inc.
Version I-2014.03LC
Project file C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\syntmp\run_option.xml
Written on Sat Oct 15 23:48:18 2016
Written on Wed Oct 26 22:26:19 2016
-->

6
Logic/syntmp/statusReport.html
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@ -38,7 +38,7 @@
<td>-</td>
<td>0m:00s</td>
<td>-</td>
<td><font size="-1">15.10.2016</font><br/><font size="-2">23:48:18</font></td>
<td><font size="-1">26.10.2016</font><br/><font size="-2">22:26:19</font></td>
</tr>
<tr>
@ -49,12 +49,12 @@
<td>0m:00s</td>
<td>0m:00s</td>
<td>105MB</td>
<td><font size="-1">15.10.2016</font><br/><font size="-2">23:48:19</font></td>
<td><font size="-1">26.10.2016</font><br/><font size="-2">22:26:20</font></td>
</tr>
<tr>
<td class="optionTitle">Multi-srs Generator</td>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">15.10.2016</font><br/><font size="-2">23:48:19</font></td> </tbody>
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">26.10.2016</font><br/><font size="-2">22:26:20</font></td> </tbody>
</table>
</td></tr></table></body>
</html>

2
Logic/synwork/BUS68030_comp.fdep
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@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1476568072
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1477513553
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_comp.fdeporig
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@ -9,7 +9,7 @@
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
#CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1476568072
#CUR:"C:\\users\\matze\\amiga\\hardwarehacks\\68030-tk\\github\\logic\\68030-68000-bus.vhd":1477513553
0 "C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

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Logic/synwork/BUS68030_comp.srs
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Logic/synwork/BUS68030_mult.srs
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Logic/synwork/BUS68030_mult_srs/skeleton.srs
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Logic/synwork/BUS68030_s.srs
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