mirror of
https://github.com/kr239/68030tk.git
synced 2025-03-31 00:29:29 +00:00
Working @50MHz
This commit is contained in:
parent
1f269e383c
commit
f5dffdc49e
@ -174,7 +174,7 @@ begin
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end if;
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--here the clock is selected
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CLK_OUT_PRE <= CLK_OUT_PRE_25;
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CLK_OUT_PRE <= CLK_OUT_PRE_50;
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CLK_OUT_PRE_D <= CLK_OUT_PRE;
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--a negative edge is comming next cycle
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@ -352,7 +352,7 @@ begin
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end if;
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--uds/lds precalculation
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if (DS_030_D0 = '0') then --DS: set udl/lds
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if (DS_030_D0 = '0' AND SM_AMIGA = IDLE_N) then --DS: set udl/lds
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if(A0='0') then
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UDS_000_INT <= '0';
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else
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@ -418,8 +418,8 @@ begin
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SM_AMIGA<=DATA_FETCH_P;
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end if;
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when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
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if( (CLK_000_N_SYNC( 5)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
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(CLK_000_N_SYNC( 6)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
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if( (CLK_000_N_SYNC( 8)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
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(CLK_000_N_SYNC( 9)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
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DSACK1_INT <='0';
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end if;
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--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
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@ -427,7 +427,7 @@ begin
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--end if;
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if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
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--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
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--DSACK1_INT <='0';
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SM_AMIGA<=END_CYCLE_N;
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end if;
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when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
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@ -1,6 +1,6 @@
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[STRATEGY-LIST]
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Normal=True, 1385910337
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[TOUCHED-REPORT]
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Design.tt4File=1405595332
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Design.tt4File=1407940994
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[synthesis-type]
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tool=Synplify
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
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[Revision]
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Parent = m4a5.lci;
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DATE = 07/17/2014;
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TIME = 13:08:52;
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DATE = 08/13/2014;
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TIME = 16:43:14;
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Source_Format = Pure_VHDL;
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Synthesis = Synplify;
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@ -107,6 +107,7 @@ layer = OFF;
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[Power]
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Default = High;
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Low = H, G, F, E, D, C, B, A;
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[Source Constraint Option]
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
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[Revision]
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Parent = m4a5.lci;
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DATE = 07/17/2014;
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TIME = 13:08:52;
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DATE = 08/13/2014;
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TIME = 16:43:14;
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Source_Format = Pure_VHDL;
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Synthesis = Synplify;
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@ -107,6 +107,7 @@ layer = OFF;
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[Power]
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Default = High;
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Low = H, G, F, E, D, C, B, A;
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[Source Constraint Option]
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6658
Logic/68030_TK.tcl
6658
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
@ -1,7 +1,7 @@
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// Signal Name Cross Reference File
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// ispLEVER Classic 1.7.00.05.28.13
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// Design '68030_tk' created Tue Aug 12 21:21:14 2014
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// Design '68030_tk' created Tue Aug 26 20:07:15 2014
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// LEGEND: '>' Functional Block Port Separator
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25
Logic/68030_tk.grp
Normal file
25
Logic/68030_tk.grp
Normal file
@ -0,0 +1,25 @@
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GROUP MACH_SEG_A DS_030 RN_DS_030 inst_LDS_000_INT inst_UDS_000_INT AVEC
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CLK_000_P_SYNC_4_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_2_
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GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
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RN_IPL_030_2_ RESET CLK_EXP CIIN_0 inst_CLK_000_NE CLK_000_P_SYNC_5_
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CLK_000_P_SYNC_7_ CLK_000_N_SYNC_4_ CLK_OUT_PRE_Dreg inst_CLK_OUT_PRE
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inst_CLK_000_NE_D0
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GROUP MACH_SEG_C SM_AMIGA_3_ SM_AMIGA_2_ inst_DS_000_ENABLE inst_DS_030_D0
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inst_VPA_D AMIGA_BUS_ENABLE_LOW state_machine_un15_clk_000_ne_i_n
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cpu_est_2_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_3_ CLK_000_N_SYNC_1_
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CLK_000_N_SYNC_3_
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GROUP MACH_SEG_D AMIGA_ADDR_ENABLE RN_AMIGA_ADDR_ENABLE VMA RN_VMA BG_000
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RN_BG_000 DTACK LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH cpu_est_1_
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cpu_est_0_ CLK_000_P_SYNC_0_ CLK_000_N_SYNC_11_ inst_CLK_000_D1
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GROUP MACH_SEG_E AS_000 RN_AS_000 inst_AS_030_D0 inst_BGACK_030_INT_D CIIN
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BERR AMIGA_BUS_DATA_DIR un14_ciin_0
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GROUP MACH_SEG_F SM_AMIGA_7_ inst_AS_030_000_SYNC SM_AMIGA_6_ SM_AMIGA_4_
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SM_AMIGA_0_ SM_AMIGA_1_ SM_AMIGA_5_ CLK_000_N_SYNC_0_ inst_CLK_000_D0
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CLK_000_P_SYNC_9_
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GROUP MACH_SEG_G RW RN_RW A0 SIZE_0_ inst_CLK_030_H inst_DTACK_D0 E RN_E
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CLK_DIV_OUT inst_CLK_000_PE CLK_000_P_SYNC_6_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_
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CLK_000_N_SYNC_8_ inst_CLK_OUT_PRE_50
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GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 AS_030 RN_AS_030 SIZE_1_
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BGACK_030 RN_BGACK_030 FPU_CS CLK_000_P_SYNC_2_ CLK_000_N_SYNC_5_
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CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_
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@ -1 +1 @@
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<LATTICE_ENCRYPTED_BLIF>46023=1P<d{ #
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<LATTICE_ENCRYPTED_BLIF>526535?).6 ;Pd]
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File diff suppressed because it is too large
Load Diff
238
Logic/68030_tk.lco
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238
Logic/68030_tk.lco
Normal file
@ -0,0 +1,238 @@
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[DEVICE]
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Family = M4A5;
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PartType = M4A5-128/64;
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Package = 100TQFP;
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PartNumber = M4A5-128/64-10VC;
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Speed = -10;
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Operating_condition = COM;
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EN_Segment = No;
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Pin_MC_1to1 = No;
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EN_PinReserve_IO = Yes;
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EN_PinReserve_BIDIR = Yes;
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Voltage = 5.0;
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[REVISION]
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RCS = "$Revision: 1.2 $";
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Parent = m4a5.lci;
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SDS_File = m4a5.sds;
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Design = 68030_tk.tt4;
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DATE = 8/26/14;
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TIME = 20:07:19;
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Source_Format = Pure_VHDL;
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Type = TT2;
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Pre_Fit_Time = 1;
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[IGNORE ASSIGNMENTS]
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Pin_Assignments = No;
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Pin_Keep_Block = No;
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Pin_Keep_Segment = No;
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Group_Assignments = No;
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Macrocell_Assignments = No;
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Macrocell_Keep_Block = No;
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Macrocell_Keep_Segment = No;
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Pin_Reservation = No;
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Block_Reservation = No;
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Segment_Reservation = No;
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Timing_Constraints = No;
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[CLEAR ASSIGNMENTS]
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Pin_Assignments = No;
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Pin_Keep_Block = No;
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Pin_Keep_Segment = No;
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Group_Assignments = No;
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Macrocell_Assignments = No;
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Macrocell_Keep_Block = No;
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Macrocell_Keep_Segment = No;
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Pin_Reservation = No;
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Block_Reservation = No;
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Segment_Reservation = No;
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Timing_Constraints = No;
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[BACKANNOTATE ASSIGNMENTS]
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Pin_Block = No;
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Pin_Macrocell_Block = No;
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Routing = No;
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[GLOBAL CONSTRAINTS]
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Max_PTerm_Split = 16;
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Max_PTerm_Collapse = 16;
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Max_Pin_Percent = 100;
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Max_Macrocell_Percent = 100;
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Max_GLB_Input_Percent = 100;
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Max_Seg_In_Percent = 100;
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Logic_Reduction = Yes;
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XOR_Synthesis = Yes;
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DT_Synthesis = Yes;
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Node_Collapse = Yes;
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Run_Time = 0;
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Set_Reset_Dont_Care = Yes;
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Clock_Optimize = No;
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In_Reg_Optimize = Yes;
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Balanced_Partitioning = Yes;
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Device_max_fanin = 33;
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Device_max_pterms = 20;
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Usercode = 0;
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Usercode_Format = Hex;
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[LOCATION ASSIGNMENTS]
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Layer = OFF;
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A_29_ = pin,6,-,B,-;
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A_28_ = pin,15,-,C,-;
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A_27_ = pin,16,-,C,-;
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A_26_ = pin,17,-,C,-;
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A_31_ = pin,4,-,B,-;
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A_25_ = pin,18,-,C,-;
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A_24_ = pin,19,-,C,-;
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A_23_ = pin,85,-,H,-;
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A_22_ = pin,84,-,H,-;
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IPL_2_ = pin,68,-,G,-;
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A_21_ = pin,94,-,A,-;
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A_20_ = pin,93,-,A,-;
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FC_1_ = pin,58,-,F,-;
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A_19_ = pin,97,-,A,-;
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A_18_ = pin,95,-,A,-;
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A_17_ = pin,59,-,F,-;
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A_16_ = pin,96,-,A,-;
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UDS_000 = pin,32,-,D,-;
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LDS_000 = pin,31,-,D,-;
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IPL_1_ = pin,56,-,F,-;
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IPL_0_ = pin,67,-,G,-;
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nEXP_SPACE = pin,14,-,-,-;
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FC_0_ = pin,57,-,F,-;
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BERR = pin,41,-,E,-;
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BG_030 = pin,21,-,C,-;
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BGACK_000 = pin,28,-,D,-;
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CLK_030 = pin,64,-,-,-;
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CLK_000 = pin,11,-,-,-;
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CLK_OSZI = pin,61,-,-,-;
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CLK_DIV_OUT = pin,65,-,G,-;
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CLK_EXP = pin,10,-,B,-;
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FPU_CS = pin,78,-,H,-;
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FPU_SENSE = pin,91,-,A,-;
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DTACK = pin,30,-,D,-;
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AVEC = pin,92,-,A,-;
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VPA = pin,36,-,-,-;
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RST = pin,86,-,-,-;
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AMIGA_ADDR_ENABLE = pin,33,-,D,-;
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AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
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AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
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AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
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CIIN = pin,47,-,E,-;
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A_30_ = pin,5,-,B,-;
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SIZE_1_ = pin,79,-,H,-;
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IPL_030_2_ = pin,9,-,B,-;
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AS_030 = pin,82,-,H,-;
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AS_000 = pin,42,-,E,-;
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RW_000 = pin,80,-,H,-;
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DS_030 = pin,98,-,A,-;
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IPL_030_1_ = pin,7,-,B,-;
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IPL_030_0_ = pin,8,-,B,-;
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A0 = pin,69,-,G,-;
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BG_000 = pin,29,-,D,-;
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BGACK_030 = pin,83,-,H,-;
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DSACK1 = pin,81,-,H,-;
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E = pin,66,-,G,-;
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VMA = pin,35,-,D,-;
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RESET = pin,3,-,B,-;
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RW = pin,71,-,G,-;
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SIZE_0_ = pin,70,-,G,-;
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cpu_est_0_ = node,-,-,D,2;
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cpu_est_1_ = node,-,-,D,9;
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inst_AS_030_D0 = node,-,-,E,8;
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inst_DS_030_D0 = node,-,-,C,14;
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inst_AS_030_000_SYNC = node,-,-,F,8;
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inst_BGACK_030_INT_D = node,-,-,E,9;
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inst_VPA_D = node,-,-,C,5;
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inst_DTACK_D0 = node,-,-,G,3;
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inst_CLK_OUT_PRE_50 = node,-,-,G,13;
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inst_CLK_000_D1 = node,-,-,D,6;
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inst_CLK_000_D0 = node,-,-,F,9;
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SM_AMIGA_7_ = node,-,-,F,4;
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inst_CLK_OUT_PRE = node,-,-,B,3;
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inst_CLK_000_PE = node,-,-,G,5;
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CLK_000_P_SYNC_9_ = node,-,-,F,6;
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inst_CLK_000_NE = node,-,-,B,5;
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CLK_000_N_SYNC_11_ = node,-,-,D,14;
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cpu_est_2_ = node,-,-,C,4;
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inst_CLK_000_NE_D0 = node,-,-,B,13;
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SM_AMIGA_6_ = node,-,-,F,0;
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SM_AMIGA_4_ = node,-,-,F,5;
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SM_AMIGA_0_ = node,-,-,F,1;
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inst_CLK_030_H = node,-,-,G,9;
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inst_LDS_000_INT = node,-,-,A,12;
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inst_DS_000_ENABLE = node,-,-,C,1;
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inst_UDS_000_INT = node,-,-,A,8;
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CLK_000_P_SYNC_0_ = node,-,-,D,10;
|
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CLK_000_P_SYNC_1_ = node,-,-,C,10;
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CLK_000_P_SYNC_2_ = node,-,-,H,6;
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CLK_000_P_SYNC_3_ = node,-,-,C,6;
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CLK_000_P_SYNC_4_ = node,-,-,A,9;
|
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CLK_000_P_SYNC_5_ = node,-,-,B,14;
|
||||
CLK_000_P_SYNC_6_ = node,-,-,G,14;
|
||||
CLK_000_P_SYNC_7_ = node,-,-,B,10;
|
||||
CLK_000_P_SYNC_8_ = node,-,-,A,5;
|
||||
CLK_000_N_SYNC_0_ = node,-,-,F,2;
|
||||
CLK_000_N_SYNC_1_ = node,-,-,C,2;
|
||||
CLK_000_N_SYNC_2_ = node,-,-,A,1;
|
||||
CLK_000_N_SYNC_3_ = node,-,-,C,13;
|
||||
CLK_000_N_SYNC_4_ = node,-,-,B,6;
|
||||
CLK_000_N_SYNC_5_ = node,-,-,H,2;
|
||||
CLK_000_N_SYNC_6_ = node,-,-,G,10;
|
||||
CLK_000_N_SYNC_7_ = node,-,-,G,6;
|
||||
CLK_000_N_SYNC_8_ = node,-,-,G,2;
|
||||
CLK_000_N_SYNC_9_ = node,-,-,H,13;
|
||||
CLK_000_N_SYNC_10_ = node,-,-,H,9;
|
||||
CLK_OUT_PRE_Dreg = node,-,-,B,9;
|
||||
SM_AMIGA_1_ = node,-,-,F,12;
|
||||
SM_AMIGA_5_ = node,-,-,F,13;
|
||||
SM_AMIGA_3_ = node,-,-,C,8;
|
||||
SM_AMIGA_2_ = node,-,-,C,12;
|
||||
un14_ciin_0 = node,-,-,E,5;
|
||||
state_machine_un15_clk_000_ne_i_n = node,-,-,C,9;
|
||||
CIIN_0 = node,-,-,B,2;
|
||||
|
||||
[GROUP ASSIGNMENTS]
|
||||
Layer = OFF;
|
||||
|
||||
[RESOURCE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[SLEWRATE]
|
||||
Default = SLOW;
|
||||
|
||||
[PULLUP]
|
||||
Default = Up;
|
||||
|
||||
[NETLIST/DELAY FORMAT]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
|
||||
[OSM BYPASS]
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Prefit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
150
Logic/68030_tk.plc
Normal file
150
Logic/68030_tk.plc
Normal file
@ -0,0 +1,150 @@
|
||||
|--------------------------------------------|
|
||||
|- ispLEVER Fitter Report File -|
|
||||
|- Version 1.7.00.05.28.13 -|
|
||||
|- (c)Copyright, Lattice Semiconductor 2002 -|
|
||||
|--------------------------------------------|
|
||||
|
||||
|
||||
; Source file 68030_tk.tt4
|
||||
; FITTER-generated Placements.
|
||||
; DEVICE mach447a
|
||||
; DATE Tue Aug 26 20:07:19 2014
|
||||
|
||||
|
||||
Pin 6 A_29_
|
||||
Pin 15 A_28_
|
||||
Pin 16 A_27_
|
||||
Pin 17 A_26_
|
||||
Pin 4 A_31_
|
||||
Pin 18 A_25_
|
||||
Pin 19 A_24_
|
||||
Pin 85 A_23_
|
||||
Pin 84 A_22_
|
||||
Pin 68 IPL_2_
|
||||
Pin 94 A_21_
|
||||
Pin 93 A_20_
|
||||
Pin 58 FC_1_
|
||||
Pin 97 A_19_
|
||||
Pin 95 A_18_
|
||||
Pin 59 A_17_
|
||||
Pin 96 A_16_
|
||||
Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185
|
||||
Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191
|
||||
Pin 56 IPL_1_
|
||||
Pin 67 IPL_0_
|
||||
Pin 14 nEXP_SPACE
|
||||
Pin 57 FC_0_
|
||||
Pin 41 BERR Comb ; S6=1 S9=1 Pair 197
|
||||
Pin 21 BG_030
|
||||
Pin 28 BGACK_000
|
||||
Pin 64 CLK_030
|
||||
Pin 11 CLK_000
|
||||
Pin 61 CLK_OSZI
|
||||
Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247
|
||||
Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 125
|
||||
Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 277
|
||||
Pin 91 FPU_SENSE
|
||||
Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173
|
||||
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
|
||||
Pin 36 VPA
|
||||
Pin 86 RST
|
||||
Pin 33 AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1 Pair 179
|
||||
Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199
|
||||
Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149
|
||||
Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 181
|
||||
Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215
|
||||
Pin 5 A_30_
|
||||
Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 271
|
||||
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
|
||||
Pin 82 AS_030 Reg ; S6=1 S9=1 Pair 281
|
||||
Pin 42 AS_000 Reg ; S6=1 S9=1 Pair 203
|
||||
Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269
|
||||
Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 101
|
||||
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143
|
||||
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137
|
||||
Pin 69 A0 Reg ; S6=1 S9=1 Pair 257
|
||||
Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 193
|
||||
Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
|
||||
Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 287
|
||||
Pin 66 E Reg ; S6=1 S9=1 Pair 251
|
||||
Pin 35 VMA Reg ; S6=1 S9=1 Pair 175
|
||||
Pin 3 RESET Reg ; S6=0 S9=1 Pair 127
|
||||
Pin 71 RW Reg ; S6=1 S9=1 Pair 245
|
||||
Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263
|
||||
Node 185 RN_UDS_000 Comb ; S6=1 S9=1
|
||||
Node 191 RN_LDS_000 Comb ; S6=1 S9=1
|
||||
Node 197 RN_BERR Comb ; S6=1 S9=1
|
||||
Node 173 RN_DTACK Comb ; S6=1 S9=1
|
||||
Node 179 RN_AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1
|
||||
Node 271 RN_SIZE_1_ Reg ; S6=1 S9=1
|
||||
Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1
|
||||
Node 281 RN_AS_030 Reg ; S6=1 S9=1
|
||||
Node 203 RN_AS_000 Reg ; S6=1 S9=1
|
||||
Node 269 RN_RW_000 Reg ; S6=1 S9=1
|
||||
Node 101 RN_DS_030 Reg ; S6=1 S9=1
|
||||
Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1
|
||||
Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1
|
||||
Node 257 RN_A0 Reg ; S6=1 S9=1
|
||||
Node 193 RN_BG_000 Reg ; S6=1 S9=1
|
||||
Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
|
||||
Node 287 RN_DSACK1 Reg ; S6=1 S9=1
|
||||
Node 251 RN_E Reg ; S6=1 S9=1
|
||||
Node 175 RN_VMA Reg ; S6=1 S9=1
|
||||
Node 245 RN_RW Reg ; S6=1 S9=1
|
||||
Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1
|
||||
Node 176 cpu_est_0_ Reg ; S6=1 S9=1
|
||||
Node 187 cpu_est_1_ Reg ; S6=1 S9=1
|
||||
Node 209 inst_AS_030_D0 Reg ; S6=1 S9=1
|
||||
Node 170 inst_DS_030_D0 Reg ; S6=0 S9=1
|
||||
Node 233 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
|
||||
Node 211 inst_BGACK_030_INT_D Reg ; S6=1 S9=1
|
||||
Node 157 inst_VPA_D Reg ; S6=0 S9=1
|
||||
Node 250 inst_DTACK_D0 Reg ; S6=1 S9=1
|
||||
Node 265 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1
|
||||
Node 182 inst_CLK_000_D1 Reg ; S6=1 S9=1
|
||||
Node 235 inst_CLK_000_D0 Reg ; S6=1 S9=1
|
||||
Node 227 SM_AMIGA_7_ Reg ; S6=1 S9=1
|
||||
Node 130 inst_CLK_OUT_PRE Reg ; S6=1 S9=1
|
||||
Node 253 inst_CLK_000_PE Reg ; S6=1 S9=1
|
||||
Node 230 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 133 inst_CLK_000_NE Reg ; S6=1 S9=1
|
||||
Node 194 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1
|
||||
Node 155 cpu_est_2_ Reg ; S6=1 S9=1
|
||||
Node 145 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1
|
||||
Node 221 SM_AMIGA_6_ Reg ; S6=0 S9=1
|
||||
Node 229 SM_AMIGA_4_ Reg ; S6=0 S9=1
|
||||
Node 223 SM_AMIGA_0_ Reg ; S6=0 S9=1
|
||||
Node 259 inst_CLK_030_H Reg ; S6=0 S9=1
|
||||
Node 119 inst_LDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 151 inst_DS_000_ENABLE Reg ; S6=1 S9=1
|
||||
Node 113 inst_UDS_000_INT Reg ; S6=1 S9=1
|
||||
Node 188 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 164 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 278 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 158 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 115 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 146 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 266 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 140 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 109 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 224 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1
|
||||
Node 152 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1
|
||||
Node 103 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1
|
||||
Node 169 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1
|
||||
Node 134 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1
|
||||
Node 272 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1
|
||||
Node 260 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1
|
||||
Node 254 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1
|
||||
Node 248 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1
|
||||
Node 289 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1
|
||||
Node 283 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1
|
||||
Node 139 CLK_OUT_PRE_Dreg Reg ; S6=1 S9=1
|
||||
Node 239 SM_AMIGA_1_ Reg ; S6=0 S9=1
|
||||
Node 241 SM_AMIGA_5_ Reg ; S6=0 S9=1
|
||||
Node 161 SM_AMIGA_3_ Reg ; S6=1 S9=1
|
||||
Node 167 SM_AMIGA_2_ Reg ; S6=1 S9=1
|
||||
Node 205 un14_ciin_0 Comb ; S6=1 S9=1
|
||||
Node 163 state_machine_un15_clk_000_ne_i_n Comb ; S6=1 S9=1
|
||||
Node 128 CIIN_0 Comb ; S6=1 S9=1
|
||||
; Unused Pins & Nodes
|
||||
; -> None Found.
|
1970
Logic/68030_tk.prd
Normal file
1970
Logic/68030_tk.prd
Normal file
File diff suppressed because it is too large
Load Diff
1766
Logic/68030_tk.rpt
Normal file
1766
Logic/68030_tk.rpt
Normal file
File diff suppressed because it is too large
Load Diff
2
Logic/68030_tk.svl
Normal file
2
Logic/68030_tk.svl
Normal file
@ -0,0 +1,2 @@
|
||||
Part Number: M4A5-128/64-10VC
|
||||
Need not generate svf file according to the constraints, exit
|
122
Logic/68030_tk.tal
Normal file
122
Logic/68030_tk.tal
Normal file
@ -0,0 +1,122 @@
|
||||
|
||||
|
||||
Design Name = 68030_tk.tt4
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
||||
*******************
|
||||
* TIMING ANALYSIS *
|
||||
*******************
|
||||
|
||||
Timing Analysis KEY:
|
||||
One unit of delay time is equivalent to one pass
|
||||
through the Central Switch Matrix.
|
||||
.. Delay ( in this column ) not applicable to the indicated signal.
|
||||
TSU, Set-Up Time ( 0 for input-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and a register setup before clock.
|
||||
TSU is reported on the register.
|
||||
TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and an output pin.
|
||||
TCO is reported on the register.
|
||||
TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
|
||||
represents the number of switch matrix passes between
|
||||
an input pin and an output pin.
|
||||
TPD is reported on the output pin.
|
||||
TCR, Clocked Output-to-Register Time,
|
||||
represents the number of switch matrix passes between
|
||||
a clocked register and the register it drives ( before clock ).
|
||||
TCR is reported on the driving register.
|
||||
|
||||
TSU TCO TPD TCR
|
||||
#passes #passes #passes #passes
|
||||
SIGNAL NAME min max min max min max min max
|
||||
E .. .. 0 0 .. .. 1 2
|
||||
RN_E .. .. 0 0 .. .. 1 2
|
||||
VMA .. .. 0 0 .. .. 1 2
|
||||
RN_VMA .. .. 0 0 .. .. 1 2
|
||||
cpu_est_0_ .. .. .. .. .. .. 1 2
|
||||
cpu_est_1_ .. .. .. .. .. .. 1 2
|
||||
inst_VPA_D 1 1 .. .. .. .. 1 2
|
||||
inst_DTACK_D0 1 2 .. .. .. .. 1 2
|
||||
cpu_est_2_ .. .. .. .. .. .. 1 2
|
||||
inst_LDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2
|
||||
inst_UDS_000_INT 1 1 1 1 .. .. 2 2
|
||||
CIIN_0 .. .. .. .. 1 2 .. ..
|
||||
FPU_CS .. .. .. .. 1 1 .. ..
|
||||
DTACK .. .. .. .. 1 1 .. ..
|
||||
AMIGA_ADDR_ENABLE 1 1 0 1 .. .. 1 1
|
||||
RN_AMIGA_ADDR_ENABLE 1 1 0 1 .. .. 1 1
|
||||
AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. ..
|
||||
CIIN .. .. .. .. 1 1 .. ..
|
||||
SIZE_1_ 1 1 0 0 .. .. .. ..
|
||||
IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_2_ 1 1 0 0 .. .. 1 1
|
||||
AS_030 1 1 0 0 .. .. 1 1
|
||||
RN_AS_030 1 1 0 0 .. .. 1 1
|
||||
AS_000 1 1 0 0 .. .. 1 1
|
||||
RN_AS_000 1 1 0 0 .. .. 1 1
|
||||
RW_000 1 1 0 0 .. .. 1 1
|
||||
RN_RW_000 1 1 0 0 .. .. 1 1
|
||||
DS_030 1 1 0 0 .. .. 1 1
|
||||
RN_DS_030 1 1 0 0 .. .. 1 1
|
||||
IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
|
||||
IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
|
||||
A0 1 1 0 0 .. .. .. ..
|
||||
BG_000 1 1 0 0 .. .. 1 1
|
||||
RN_BG_000 1 1 0 0 .. .. 1 1
|
||||
BGACK_030 1 1 0 1 .. .. 1 1
|
||||
RN_BGACK_030 1 1 0 1 .. .. 1 1
|
||||
DSACK1 1 1 0 0 .. .. 1 1
|
||||
RN_DSACK1 1 1 0 0 .. .. 1 1
|
||||
RW 1 1 0 0 .. .. 1 1
|
||||
RN_RW 1 1 0 0 .. .. 1 1
|
||||
SIZE_0_ 1 1 0 0 .. .. .. ..
|
||||
inst_AS_030_D0 1 1 1 1 .. .. 1 1
|
||||
inst_DS_030_D0 1 1 .. .. .. .. 1 1
|
||||
inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1
|
||||
inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_D1 .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_D0 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_7_ 1 1 .. .. .. .. 1 1
|
||||
inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_PE .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_NE .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1
|
||||
inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1
|
||||
SM_AMIGA_6_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_4_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_0_ 1 1 .. .. .. .. 1 1
|
||||
inst_CLK_030_H 1 1 .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1
|
||||
CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1
|
||||
CLK_OUT_PRE_Dreg .. .. 1 1 .. .. 1 1
|
||||
SM_AMIGA_1_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_5_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_3_ 1 1 .. .. .. .. 1 1
|
||||
SM_AMIGA_2_ 1 1 .. .. .. .. 1 1
|
||||
un14_ciin_0 .. .. .. .. 1 1 .. ..
|
251
Logic/68030_tk.vco
Normal file
251
Logic/68030_tk.vco
Normal file
@ -0,0 +1,251 @@
|
||||
[DEVICE]
|
||||
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = NO;
|
||||
Pin_MC_1to1 = NO;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_file = m4a5.sds;
|
||||
Design = 68030_tk.tt4;
|
||||
Rev = 0.01;
|
||||
DATE = 8/26/14;
|
||||
TIME = 20:07:19;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
Source_Format = Pure_VHDL;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
|
||||
Pin_Assignments = NO;
|
||||
Pin_Keep_Block = NO;
|
||||
Pin_Keep_Segment = NO;
|
||||
Group_Assignments = NO;
|
||||
Macrocell_Assignments = NO;
|
||||
Macrocell_Keep_Block = NO;
|
||||
Macrocell_Keep_Segment = NO;
|
||||
Pin_Reservation = NO;
|
||||
Timing_Constraints = NO;
|
||||
Block_Reservation = NO;
|
||||
Segment_Reservation = NO;
|
||||
Ignore_Source_Location = NO;
|
||||
Ignore_Source_Optimization = NO;
|
||||
Ignore_Source_Timing = NO;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
|
||||
Netlist = VHDL;
|
||||
Delay_File = SDF;
|
||||
Generic_VCC = ;
|
||||
Generic_GND = ;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
|
||||
Pin_Assignment = NO;
|
||||
Pin_Block = NO;
|
||||
Pin_Macrocell_Block = NO;
|
||||
Routing = NO;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
|
||||
Balanced_Partitioning = YES;
|
||||
Spread_Placement = YES;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Inter_Seg_Percent = 100;
|
||||
Max_Seg_In_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
|
||||
Fitter_Options = YES;
|
||||
Pinout_Diagram = NO;
|
||||
Pinout_Listing = YES;
|
||||
Detailed_Block_Segment_Summary = YES;
|
||||
Input_Signal_List = YES;
|
||||
Output_Signal_List = YES;
|
||||
Bidir_Signal_List = YES;
|
||||
Node_Signal_List = YES;
|
||||
Signal_Fanout_List = YES;
|
||||
Block_Segment_Fanin_List = YES;
|
||||
Prefit_Eqn = YES;
|
||||
Postfit_Eqn = YES;
|
||||
Page_Break = YES;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
|
||||
Logic_Reduction = YES;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = YES;
|
||||
Node_Collapse = Yes;
|
||||
DT_Synthesis = Yes;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = YES;
|
||||
In_Reg_Optimize = YES;
|
||||
Clock_Optimize = NO;
|
||||
Conf_Unused_IOs = OUT_LOW;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low, High;
|
||||
Default = High;
|
||||
Low = 8, H, G, F, E, D, C, B, A;
|
||||
Type = GLB;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW, FAST, 0;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
|
||||
Layer = OFF;
|
||||
A_29_ = INPUT,6, B,-;
|
||||
A_28_ = INPUT,15, C,-;
|
||||
A_27_ = INPUT,16, C,-;
|
||||
A_26_ = INPUT,17, C,-;
|
||||
A_31_ = INPUT,4, B,-;
|
||||
A_25_ = INPUT,18, C,-;
|
||||
A_24_ = INPUT,19, C,-;
|
||||
A_23_ = INPUT,85, H,-;
|
||||
A_22_ = INPUT,84, H,-;
|
||||
IPL_2_ = INPUT,68, G,-;
|
||||
A_21_ = INPUT,94, A,-;
|
||||
A_20_ = INPUT,93, A,-;
|
||||
FC_1_ = INPUT,58, F,-;
|
||||
A_19_ = INPUT,97, A,-;
|
||||
A_18_ = INPUT,95, A,-;
|
||||
A_17_ = INPUT,59, F,-;
|
||||
A_16_ = INPUT,96, A,-;
|
||||
UDS_000 = BIDIR,32, D,-;
|
||||
LDS_000 = BIDIR,31, D,-;
|
||||
IPL_1_ = INPUT,56, F,-;
|
||||
IPL_0_ = INPUT,67, G,-;
|
||||
nEXP_SPACE = INPUT,14,-,-;
|
||||
FC_0_ = INPUT,57, F,-;
|
||||
BERR = BIDIR,41, E,-;
|
||||
BG_030 = INPUT,21, C,-;
|
||||
BGACK_000 = INPUT,28, D,-;
|
||||
CLK_030 = INPUT,64,-,-;
|
||||
CLK_000 = INPUT,11,-,-;
|
||||
CLK_OSZI = INPUT,61,-,-;
|
||||
CLK_DIV_OUT = OUTPUT,65, G,-;
|
||||
CLK_EXP = OUTPUT,10, B,-;
|
||||
FPU_CS = OUTPUT,78, H,-;
|
||||
FPU_SENSE = INPUT,91, A,-;
|
||||
DTACK = BIDIR,30, D,-;
|
||||
AVEC = OUTPUT,92, A,-;
|
||||
VPA = INPUT,36,-,-;
|
||||
RST = INPUT,86,-,-;
|
||||
AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
|
||||
AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
|
||||
CIIN = OUTPUT,47, E,-;
|
||||
A_30_ = INPUT,5, B,-;
|
||||
SIZE_1_ = BIDIR,79, H,-;
|
||||
IPL_030_2_ = OUTPUT,9, B,-;
|
||||
AS_030 = BIDIR,82, H,-;
|
||||
AS_000 = BIDIR,42, E,-;
|
||||
RW_000 = BIDIR,80, H,-;
|
||||
DS_030 = BIDIR,98, A,-;
|
||||
IPL_030_1_ = OUTPUT,7, B,-;
|
||||
IPL_030_0_ = OUTPUT,8, B,-;
|
||||
A0 = BIDIR,69, G,-;
|
||||
BG_000 = OUTPUT,29, D,-;
|
||||
BGACK_030 = OUTPUT,83, H,-;
|
||||
DSACK1 = BIDIR,81, H,-;
|
||||
E = OUTPUT,66, G,-;
|
||||
VMA = OUTPUT,35, D,-;
|
||||
RESET = OUTPUT,3, B,-;
|
||||
RW = BIDIR,71, G,-;
|
||||
SIZE_0_ = BIDIR,70, G,-;
|
||||
cpu_est_0_ = NODE,2, D,-;
|
||||
cpu_est_1_ = NODE,9, D,-;
|
||||
inst_AS_030_D0 = NODE,8, E,-;
|
||||
inst_DS_030_D0 = NODE,14, C,-;
|
||||
inst_AS_030_000_SYNC = NODE,8, F,-;
|
||||
inst_BGACK_030_INT_D = NODE,9, E,-;
|
||||
inst_VPA_D = NODE,5, C,-;
|
||||
inst_DTACK_D0 = NODE,3, G,-;
|
||||
inst_CLK_OUT_PRE_50 = NODE,13, G,-;
|
||||
inst_CLK_000_D1 = NODE,6, D,-;
|
||||
inst_CLK_000_D0 = NODE,9, F,-;
|
||||
SM_AMIGA_7_ = NODE,4, F,-;
|
||||
inst_CLK_OUT_PRE = NODE,3, B,-;
|
||||
inst_CLK_000_PE = NODE,5, G,-;
|
||||
CLK_000_P_SYNC_9_ = NODE,6, F,-;
|
||||
inst_CLK_000_NE = NODE,5, B,-;
|
||||
CLK_000_N_SYNC_11_ = NODE,14, D,-;
|
||||
cpu_est_2_ = NODE,4, C,-;
|
||||
inst_CLK_000_NE_D0 = NODE,13, B,-;
|
||||
SM_AMIGA_6_ = NODE,0, F,-;
|
||||
SM_AMIGA_4_ = NODE,5, F,-;
|
||||
SM_AMIGA_0_ = NODE,1, F,-;
|
||||
inst_CLK_030_H = NODE,9, G,-;
|
||||
inst_LDS_000_INT = NODE,12, A,-;
|
||||
inst_DS_000_ENABLE = NODE,1, C,-;
|
||||
inst_UDS_000_INT = NODE,8, A,-;
|
||||
CLK_000_P_SYNC_0_ = NODE,10, D,-;
|
||||
CLK_000_P_SYNC_1_ = NODE,10, C,-;
|
||||
CLK_000_P_SYNC_2_ = NODE,6, H,-;
|
||||
CLK_000_P_SYNC_3_ = NODE,6, C,-;
|
||||
CLK_000_P_SYNC_4_ = NODE,9, A,-;
|
||||
CLK_000_P_SYNC_5_ = NODE,14, B,-;
|
||||
CLK_000_P_SYNC_6_ = NODE,14, G,-;
|
||||
CLK_000_P_SYNC_7_ = NODE,10, B,-;
|
||||
CLK_000_P_SYNC_8_ = NODE,5, A,-;
|
||||
CLK_000_N_SYNC_0_ = NODE,2, F,-;
|
||||
CLK_000_N_SYNC_1_ = NODE,2, C,-;
|
||||
CLK_000_N_SYNC_2_ = NODE,1, A,-;
|
||||
CLK_000_N_SYNC_3_ = NODE,13, C,-;
|
||||
CLK_000_N_SYNC_4_ = NODE,6, B,-;
|
||||
CLK_000_N_SYNC_5_ = NODE,2, H,-;
|
||||
CLK_000_N_SYNC_6_ = NODE,10, G,-;
|
||||
CLK_000_N_SYNC_7_ = NODE,6, G,-;
|
||||
CLK_000_N_SYNC_8_ = NODE,2, G,-;
|
||||
CLK_000_N_SYNC_9_ = NODE,13, H,-;
|
||||
CLK_000_N_SYNC_10_ = NODE,9, H,-;
|
||||
CLK_OUT_PRE_Dreg = NODE,9, B,-;
|
||||
SM_AMIGA_1_ = NODE,12, F,-;
|
||||
SM_AMIGA_5_ = NODE,13, F,-;
|
||||
SM_AMIGA_3_ = NODE,8, C,-;
|
||||
SM_AMIGA_2_ = NODE,12, C,-;
|
||||
un14_ciin_0 = NODE,5, E,-;
|
||||
state_machine_un15_clk_000_ne_i_n = NODE,9, C,-;
|
||||
CIIN_0 = NODE,2, B,-;
|
218
Logic/68030_tk.vct
Normal file
218
Logic/68030_tk.vct
Normal file
@ -0,0 +1,218 @@
|
||||
[DEVICE]
|
||||
Family = M4A5;
|
||||
PartType = M4A5-128/64;
|
||||
Package = 100TQFP;
|
||||
PartNumber = M4A5-128/64-10VC;
|
||||
Speed = -10;
|
||||
Operating_condition = COM;
|
||||
EN_Segment = No;
|
||||
Pin_MC_1to1 = No;
|
||||
EN_PinReserve_IO = Yes;
|
||||
EN_PinReserve_BIDIR = Yes;
|
||||
Voltage = 5.0;
|
||||
|
||||
[REVISION]
|
||||
RCS = "$Revision: 1.2 $";
|
||||
Parent = m4a5.lci;
|
||||
SDS_File = m4a5.sds;
|
||||
DATE = 08/13/2014;
|
||||
TIME = 16:43:14;
|
||||
Source_Format = Pure_VHDL;
|
||||
Type = TT2;
|
||||
Pre_Fit_Time = 1;
|
||||
|
||||
[IGNORE ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[CLEAR ASSIGNMENTS]
|
||||
Pin_Assignments = No;
|
||||
Pin_Keep_Block = No;
|
||||
Pin_Keep_Segment = No;
|
||||
Group_Assignments = No;
|
||||
Macrocell_Assignments = No;
|
||||
Macrocell_Keep_Block = No;
|
||||
Macrocell_Keep_Segment = No;
|
||||
Pin_Reservation = No;
|
||||
Block_Reservation = No;
|
||||
Segment_Reservation = No;
|
||||
Timing_Constraints = No;
|
||||
|
||||
[BACKANNOTATE ASSIGNMENTS]
|
||||
Pin_Block = No;
|
||||
Pin_Macrocell_Block = No;
|
||||
Routing = No;
|
||||
|
||||
[GLOBAL PROJECT OPTIMIZATION]
|
||||
Balanced_Partitioning = Yes;
|
||||
Spread_Placement = Yes;
|
||||
Max_Pin_Percent = 100;
|
||||
Max_Macrocell_Percent = 100;
|
||||
Max_Blk_In_Percent = 100;
|
||||
|
||||
[OPTIMIZATION OPTIONS]
|
||||
Logic_Reduction = Yes;
|
||||
Max_PTerm_Split = 16;
|
||||
Max_PTerm_Collapse = 16;
|
||||
XOR_Synthesis = Yes;
|
||||
EN_XOR_Synthesis = Yes;
|
||||
XOR_Gate = Yes;
|
||||
Node_Collapse = Yes;
|
||||
Keep_XOR = Yes;
|
||||
DT_Synthesis = Yes;
|
||||
Clock_PTerm = Min;
|
||||
Reset_PTerm = On;
|
||||
Preset_PTerm = On;
|
||||
Clock_Enable_PTerm = On;
|
||||
Output_Enable_PTerm = On;
|
||||
EN_DT_Synthesis = Yes;
|
||||
Cluster_PTerm = 5;
|
||||
FF_inv = No;
|
||||
EN_Use_CE = No;
|
||||
Use_CE = No;
|
||||
Use_Internal_COM_FB = Yes;
|
||||
EN_use_Internal_COM_FB = Yes;
|
||||
Set_Reset_Swap = No;
|
||||
EN_Set_Reset_Swap = No;
|
||||
Density = No;
|
||||
DeMorgan = Yes;
|
||||
T_FF = Yes;
|
||||
Max_Symbols = 32;
|
||||
|
||||
[FITTER GLOBAL OPTIONS]
|
||||
Run_Time = 0;
|
||||
Set_Reset_Dont_Care = Yes;
|
||||
EN_Set_Reset_Dont_Care = Yes;
|
||||
In_Reg_Optimize = Yes;
|
||||
EN_In_Reg_Optimize = No;
|
||||
Clock_Optimize = No;
|
||||
Global_Clock_As_Pterm = No;
|
||||
Show_Iterations = No;
|
||||
Routing_Attempts = 2;
|
||||
Conf_Unused_IOs = Out_Low;
|
||||
|
||||
[HARDWARE DEVICE OPTIONS]
|
||||
Zero_Hold_Time = Yes;
|
||||
Signature_Word = 0;
|
||||
Pull_up = Yes;
|
||||
Out_Slew_Rate = SLOW,FAST,0;
|
||||
Device_max_fanin = 33;
|
||||
Device_max_pterms = 20;
|
||||
Usercode_Format = Hex;
|
||||
|
||||
[PIN RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[LOCATION ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
AS_030 = input,82,H,-;
|
||||
A_16_ = input,96,A,-;
|
||||
A_17_ = input,59,F,-;
|
||||
A_18_ = input,95,A,-;
|
||||
A_19_ = input,97,A,-;
|
||||
BGACK_000 = input,28,D,-;
|
||||
BG_030 = input,21,C,-;
|
||||
CLK_000 = input,11,-,-;
|
||||
CLK_030 = input,64,-,-;
|
||||
CLK_OSZI = input,61,-,-;
|
||||
FC_0_ = input,57,F,-;
|
||||
FC_1_ = input,58,F,-;
|
||||
IPL_0_ = input,67,G,-;
|
||||
IPL_1_ = input,56,F,-;
|
||||
IPL_2_ = input,68,G,-;
|
||||
RST = input,86,-,-;
|
||||
RW = input,71,G,-;
|
||||
SIZE_1_ = input,79,H,-;
|
||||
SIZE_0_ = input,70,G,-;
|
||||
VPA = input,36,-,-;
|
||||
AVEC = input,92,A,-;
|
||||
BGACK_030 = input,83,H,-;
|
||||
BG_000 = input,29,D,-;
|
||||
CLK_DIV_OUT = input,65,G,-;
|
||||
CLK_EXP = input,10,B,-;
|
||||
E = input,66,G,-;
|
||||
FPU_CS = input,78,H,-;
|
||||
IPL_030_0_ = input,8,B,-;
|
||||
IPL_030_1_ = input,7,B,-;
|
||||
IPL_030_2_ = input,9,B,-;
|
||||
LDS_000 = input,31,D,-;
|
||||
UDS_000 = input,32,D,-;
|
||||
VMA = input,35,D,-;
|
||||
DTACK = input,30,D,-;
|
||||
RESET = input,3,B,-;
|
||||
AMIGA_BUS_DATA_DIR = input,48,E,-;
|
||||
AMIGA_BUS_ENABLE_LOW = input,20,C,-;
|
||||
CIIN = input,47,E,-;
|
||||
A_20_ = input,93,A,-;
|
||||
A_21_ = input,94,A,-;
|
||||
A_22_ = input,84,H,-;
|
||||
A_24_ = input,19,C,-;
|
||||
A_25_ = input,18,C,-;
|
||||
A_26_ = input,17,C,-;
|
||||
A_27_ = input,16,C,-;
|
||||
A_28_ = input,15,C,-;
|
||||
A_29_ = input,6,B,-;
|
||||
A_30_ = input,5,B,-;
|
||||
A_31_ = input,4,B,-;
|
||||
DS_030 = input,98,A,-;
|
||||
BERR = input,41,E,-;
|
||||
nEXP_SPACE = input,14,-,-;
|
||||
A0 = input,69,G,-;
|
||||
DSACK1 = input,81,H,-;
|
||||
RW_000 = input,80,H,-;
|
||||
AS_000 = input,42,E,-;
|
||||
AMIGA_ADDR_ENABLE = input,33,D,-;
|
||||
AMIGA_BUS_ENABLE_HIGH = input,34,D,-;
|
||||
A_23_ = input,85,H,-;
|
||||
FPU_SENSE = input,91,A,-;
|
||||
|
||||
[GROUP ASSIGNMENT]
|
||||
Layer = OFF;
|
||||
|
||||
[SPACE RESERVATIONS]
|
||||
Layer = OFF;
|
||||
|
||||
[BACKANNOTATE NETLIST]
|
||||
Delay_File = SDF;
|
||||
Netlist = VHDL;
|
||||
VCC_GND = Cell;
|
||||
|
||||
[FITTER REPORT FORMAT]
|
||||
Fitter_Options = Yes;
|
||||
Pinout_Diagram = No;
|
||||
Pinout_Listing = Yes;
|
||||
Detailed_Block_Segment_Summary = Yes;
|
||||
Input_Signal_List = Yes;
|
||||
Output_Signal_List = Yes;
|
||||
Bidir_Signal_List = Yes;
|
||||
Node_Signal_List = Yes;
|
||||
Signal_Fanout_List = Yes;
|
||||
Block_Segment_Fanin_List = Yes;
|
||||
Postfit_Eqn = Yes;
|
||||
Page_Break = Yes;
|
||||
|
||||
[POWER]
|
||||
Powerlevel = Low,High;
|
||||
Default = High;
|
||||
Low = 8,H,G,F,E,D,C,B,A;
|
||||
Type = GLB;
|
||||
|
||||
[SOURCE CONSTRAINT OPTION]
|
||||
Import_source_constraint = Yes;
|
||||
Disable_warning_message = No;
|
||||
|
||||
[TIMING ANALYZER]
|
||||
Last_source=;
|
||||
Last_source_type=Fmax;
|
||||
|
||||
[INPUT REGISTERS]
|
||||
|
16
Logic/68030_tk.xrf
Normal file
16
Logic/68030_tk.xrf
Normal file
@ -0,0 +1,16 @@
|
||||
Signal Name Cross Reference File
|
||||
|
||||
ispLEVER Classic 1.7.00.05.28.13
|
||||
|
||||
Design '68030_tk' created Tue Aug 26 20:07:15 2014
|
||||
|
||||
|
||||
LEGEND: '>' Functional Block Port Separator
|
||||
'/' Hierarchy Path Separator
|
||||
'@' Automatically Generated Node
|
||||
|
||||
|
||||
Short Name Hierarchical Name
|
||||
---------- -----------------
|
||||
|
||||
*** Shortened names not required for this design. ***
|
3386
Logic/BUS68030.edi
Normal file
3386
Logic/BUS68030.edi
Normal file
File diff suppressed because it is too large
Load Diff
60
Logic/BUS68030.naf
Normal file
60
Logic/BUS68030.naf
Normal file
@ -0,0 +1,60 @@
|
||||
AS_030 b
|
||||
AS_000 b
|
||||
RW_000 b
|
||||
DS_030 b
|
||||
UDS_000 b
|
||||
LDS_000 b
|
||||
SIZE[1] b
|
||||
SIZE[0] b
|
||||
A[31] i
|
||||
A[30] i
|
||||
A[29] i
|
||||
A[28] i
|
||||
A[27] i
|
||||
A[26] i
|
||||
A[25] i
|
||||
A[24] i
|
||||
A[23] i
|
||||
A[22] i
|
||||
A[21] i
|
||||
A[20] i
|
||||
A[19] i
|
||||
A[18] i
|
||||
A[17] i
|
||||
A[16] i
|
||||
A0 b
|
||||
nEXP_SPACE i
|
||||
BERR b
|
||||
BG_030 i
|
||||
BG_000 o
|
||||
BGACK_030 o
|
||||
BGACK_000 i
|
||||
CLK_030 i
|
||||
CLK_000 i
|
||||
CLK_OSZI i
|
||||
CLK_DIV_OUT o
|
||||
CLK_EXP o
|
||||
FPU_CS o
|
||||
FPU_SENSE i
|
||||
IPL_030[2] o
|
||||
IPL_030[1] o
|
||||
IPL_030[0] o
|
||||
IPL[2] i
|
||||
IPL[1] i
|
||||
IPL[0] i
|
||||
DSACK1 b
|
||||
DTACK b
|
||||
AVEC o
|
||||
E o
|
||||
VPA i
|
||||
VMA o
|
||||
RST i
|
||||
RESET o
|
||||
RW b
|
||||
FC[1] i
|
||||
FC[0] i
|
||||
AMIGA_ADDR_ENABLE o
|
||||
AMIGA_BUS_DATA_DIR o
|
||||
AMIGA_BUS_ENABLE_LOW o
|
||||
AMIGA_BUS_ENABLE_HIGH o
|
||||
CIIN o
|
@ -1,6 +1,6 @@
|
||||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Tue Aug 12 21:21:07 2014
|
||||
#-- Written on Tue Aug 26 20:07:08 2014
|
||||
|
||||
|
||||
#device options
|
||||
|
1268
Logic/M4A5_128_64_XXVC.bsd
Normal file
1268
Logic/M4A5_128_64_XXVC.bsd
Normal file
File diff suppressed because it is too large
Load Diff
1265
Logic/M4A5_128_64_XXYC.bsd
Normal file
1265
Logic/M4A5_128_64_XXYC.bsd
Normal file
File diff suppressed because it is too large
Load Diff
@ -19,8 +19,8 @@
|
||||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
|
||||
<FileTime>08/12/14 21:21:19</FileTime>
|
||||
<JedecChecksum>0xC574</JedecChecksum>
|
||||
<FileTime>08/26/14 20:07:19</FileTime>
|
||||
<JedecChecksum>0x434A</JedecChecksum>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
|
@ -6,7 +6,7 @@
|
||||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Tue Aug 12 21:21:07 2014
|
||||
#Tue Aug 26 20:07:08 2014
|
||||
|
||||
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
||||
@N|Running in 64-bit mode
|
||||
@ -27,7 +27,9 @@ Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_OUT_PRE_25
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_CNT_P(1 downto 0)
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:36:120:38|Pruning register CLK_OUT_PRE_50_D
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
@ -45,7 +47,7 @@ State machine has 8 reachable states with original encodings of:
|
||||
111
|
||||
@END
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Tue Aug 12 21:21:07 2014
|
||||
# Tue Aug 26 20:07:08 2014
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
@ -71,24 +73,24 @@ Resource Usage Report
|
||||
Simple gate primitives:
|
||||
DFFSH 25 uses
|
||||
DFFRH 10 uses
|
||||
DFF 36 uses
|
||||
DFF 34 uses
|
||||
BI_DIR 13 uses
|
||||
IBUF 30 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 1 use
|
||||
AND2 214 uses
|
||||
AND2 211 uses
|
||||
INV 165 uses
|
||||
OR2 21 uses
|
||||
XOR2 2 uses
|
||||
XOR2 1 use
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
G-2012.09LC-SP1
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Tue Aug 12 21:21:09 2014
|
||||
# Tue Aug 26 20:07:10 2014
|
||||
|
||||
###########################################################]
|
||||
|
24
Logic/m4a5.bsd
Normal file
24
Logic/m4a5.bsd
Normal file
@ -0,0 +1,24 @@
|
||||
entity generated_m4a5 is
|
||||
|
||||
generic (PHYSICAL_PIN_MAP : string := "X_PACKAGE");
|
||||
|
||||
port (TCK: in bit; TDI: in bit; TDO: out bit; TMS: in bit);
|
||||
|
||||
use STD_1149_1_2001.all;
|
||||
attribute Component_Conformance of m4a5 : entity is "STD_1149_1_2001";
|
||||
|
||||
attribute PIN_MAP of m4a5 : entity is PHYSICAL_PIN_MAP;
|
||||
|
||||
constant X_PACKAGE:PIN_MAP_STRING := "TCK : 1," & "TDI : 2," & "TDO : 3," & "TMS : 4";
|
||||
attribute Tap_Scan_In of TDI: signal is true;
|
||||
attribute Tap_Scan_Mode of TMS: signal is true;
|
||||
attribute Tap_Scan_Out of TDO: signal is true;
|
||||
attribute Tap_Scan_Clock of TCK: signal is (6.0e06, BOTH);
|
||||
|
||||
attribute Instruction_Length of m4a5: entity is 6;
|
||||
attribute Instruction_Opcode of m4a5: entity is "BYPASS (111111)";
|
||||
attribute Instruction_Capture of m4a5: entity is "XXXX01";
|
||||
attribute Boundary_Length of m4a5: entity is 1;
|
||||
attribute Boundary_Register of m4a5: entity is "0 (BC_1, *, control, 0)";
|
||||
|
||||
end m4a5;
|
@ -1,7 +1,7 @@
|
||||
#-- Synopsys, Inc.
|
||||
#-- Version G-2012.09LC-SP1
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Tue Aug 12 21:21:07 2014
|
||||
#-- Written on Tue Aug 26 20:07:08 2014
|
||||
|
||||
|
||||
#project files
|
||||
|
39
Logic/syndos.env
Normal file
39
Logic/syndos.env
Normal file
@ -0,0 +1,39 @@
|
||||
ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||
DIOEDA_ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5
|
||||
DIOEDA_ActiveHDL=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||
DIOEDA_ActiveHDLPath=C:\Program Files (x86)\ispLever\active-hdl\BIN
|
||||
DIOEDA_AppNotes=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Bin=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Config=C:\Program Files (x86)\ispLever\ispcpld\config
|
||||
DIOEDA_CONTEXT=ispLEVER CLASSIC
|
||||
DIOEDA_DSPPATH=C:\Program Files (x86)\ispLever\ispLeverDSP
|
||||
DIOEDA_EPICPATH=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_Examples=C:\Program Files (x86)\ispLever\examples
|
||||
DIOEDA_FPGABinPath=C:\Program Files (x86)\ispLever\ispfpga\bin\nt
|
||||
DIOEDA_FPGAPath=C:\Program Files (x86)\ispLever\ispfpga
|
||||
DIOEDA_HDLExplorer=C:\Program Files (x86)\ispLever\hdle\win32
|
||||
DIOEDA_INI=C:\lsc_env
|
||||
DIOEDA_ispVM=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||
DIOEDA_ispVMSystem=C:\Program Files (x86)\ispLever\ispvmsystem
|
||||
DIOEDA_License=C:\Program Files (x86)\ispLever\license
|
||||
DIOEDA_MachPath=C:\Program Files (x86)\ispLever\ispcpld\bin
|
||||
DIOEDA_Manuals=C:\Program Files (x86)\ispLever\ispcpld\manuals
|
||||
DIOEDA_ModelSim=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||
DIOEDA_ModelsimPath=C:\Program Files (x86)\ispLever\modelsim\win32loem
|
||||
DIOEDA_PDSPath=C:\Program Files (x86)\ispLever\ispcomp
|
||||
DIOEDA_Precision=C:\isptools\precision
|
||||
DIOEDA_PrecisionPath=C:\isptools\precision
|
||||
DIOEDA_ProductName=ispLEVER
|
||||
DIOEDA_ProductPrefix=SYN
|
||||
DIOEDA_ProductTitle=ispLEVER
|
||||
DIOEDA_ProductType=1.7.00.05.28.13_LS_HDL_BASE_PC_N
|
||||
DIOEDA_ProductVersion=1.7.00.05
|
||||
DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.7
|
||||
DIOEDA_Root=C:\Program Files (x86)\ispLever\ispcpld
|
||||
DIOEDA_Spectrum=C:\isptools\spectrum
|
||||
DIOEDA_SpectrumPath=C:\isptools\spectrum
|
||||
DIOEDA_Synplify=C:\Program Files (x86)\ispLever\synpbase
|
||||
DIOEDA_SynplifyPath=C:\Program Files (x86)\ispLever\synpbase
|
||||
DIOEDA_Tutorial=C:\Program Files (x86)\ispLever\ispcpld\tutorial
|
||||
DIOPRODUCT=ispLEVER
|
||||
PATH=C:\Program Files (x86)\ispLever\ispcpld\bin
|
@ -19,24 +19,24 @@ Resource Usage Report
|
||||
Simple gate primitives:
|
||||
DFFSH 25 uses
|
||||
DFFRH 10 uses
|
||||
DFF 36 uses
|
||||
DFF 34 uses
|
||||
BI_DIR 13 uses
|
||||
IBUF 30 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 1 use
|
||||
AND2 214 uses
|
||||
AND2 211 uses
|
||||
INV 165 uses
|
||||
OR2 21 uses
|
||||
XOR2 2 uses
|
||||
XOR2 1 use
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
G-2012.09LC-SP1
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Tue Aug 12 21:21:09 2014
|
||||
# Tue Aug 26 20:07:10 2014
|
||||
|
||||
###########################################################]
|
||||
|
@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>12</data>
|
||||
<data>14</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
|
||||
<data>-</data>
|
||||
</info>
|
||||
<info name="Real Time">
|
||||
<data>0h:00m:00s</data>
|
||||
<data>0h:00m:01s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1407871267</data>
|
||||
<data type="timestamp">1409076428</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
@ -6,7 +6,9 @@
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_OUT_PRE_25
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_CNT_P(1 downto 0)
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:36:120:38|Pruning register CLK_OUT_PRE_50_D
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
|
@ -36,10 +36,10 @@ The file contains the job information from mapper to be displayed as part of the
|
||||
<data>0h:00m:00s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>96MB</data>
|
||||
<data>95MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1407871269</data>
|
||||
<data type="timestamp">1409076430</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
@ -3,7 +3,7 @@
|
||||
Synopsys, Inc.
|
||||
Version G-2012.09LC-SP1
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Tue Aug 12 21:21:07 2014
|
||||
Written on Tue Aug 26 20:07:08 2014
|
||||
|
||||
|
||||
-->
|
||||
|
@ -10,7 +10,7 @@
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407871262
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1409076416
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
@ -10,7 +10,7 @@
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1407871262
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1409076416
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
Binary file not shown.
@ -8,7 +8,9 @@ Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_NE
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_OUT_PRE_25
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":121:38:121:40|Pruning register CLK_CNT_P(1 downto 0)
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:36:120:38|Pruning register CLK_OUT_PRE_50_D
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_N(1 downto 0)
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:61:136:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
|
Loading…
x
Reference in New Issue
Block a user