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Adress bus on permanently

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The adress bus is now on permanently. This is neccessary because some
GARY-Adapters decode the address before AS
This commit is contained in:
MHeinrichs 2015-02-19 21:34:28 +01:00
parent e60f9456e7
commit f63a9b8ddf
18 changed files with 1657 additions and 1665 deletions
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14
Logic/68030-68000-bus.vhd
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@ -351,7 +351,8 @@ begin
RW_000_INT <= '1';
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
AS_030_D0 = '0' AND --as set
BGACK_000='1' AND --no dma -cycle
BGACK_030_INT='1' AND
BGACK_030_INT_D='1' AND --no dma -cycle
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
SM_AMIGA = IDLE_P --last amiga cycle terminated
@ -392,13 +393,12 @@ begin
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
RW_000_INT <= '1';
AMIGA_BUS_ENABLE_INT <= CLK_000_D1;
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
SM_AMIGA<=IDLE_N; --go to s1
else
AMIGA_BUS_ENABLE_INT <= '1';
end if;
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
if(CLK_000_PE='1')then --go to s2
--if(CLK_000_D0='1')then --go to s2
SM_AMIGA <= AS_SET_P; --as for amiga set!
@ -451,7 +451,8 @@ begin
if(CLK_000_PE='1')then --go to s0
--if(CLK_000_D0='1')then --go to s0
SM_AMIGA<=IDLE_P;
RW_000_INT <= '1';
RW_000_INT <= '1';
--AMIGA_BUS_ENABLE_INT <= '1';
end if;
end case;
@ -537,7 +538,8 @@ begin
RESET <= RESET_OUT;
-- bus drivers
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
--AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
AMIGA_ADDR_ENABLE <= '0';
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
'1';

1098
Logic/68030_TK.tcl
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File diff suppressed because it is too large Load Diff

1051
Logic/68030_tk - DMA-Working@50MHz.jed
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File diff suppressed because it is too large Load Diff

1114
Logic/68030_tk - Workin50MHz.jed
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File diff suppressed because it is too large Load Diff

2
Logic/68030_tk.crf
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@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Fri Feb 13 14:39:16 2015
// Design '68030_tk' created Thu Feb 19 14:38:45 2015
// LEGEND: '>' Functional Block Port Separator

3
Logic/68030_tk.ipr
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@ -1 +1,2 @@
<LATTICE_ENCRYPTED_BLIF>64577=5 8C0oHM
<LATTICE_ENCRYPTED_BLIF>6330162ñ
a*hO:!

2
Logic/BUS68030.prj
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@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Fri Feb 13 14:39:09 2015
#-- Written on Thu Feb 19 14:38:38 2015
#device options

14
Logic/bus68030.srf
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@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Fri Feb 13 14:39:10 2015
#Thu Feb 19 14:38:39 2015
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -16,6 +16,7 @@ Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentatio
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_25 is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:20|Signal clk_out_pre_33 is undriven
@ -25,6 +26,7 @@ VHDL syntax check successful!
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
@ -48,7 +50,7 @@ State machine has 8 reachable states with original encodings of:
111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Feb 13 14:39:10 2015
# Thu Feb 19 14:38:39 2015
###########################################################]
Map & Optimize Report
@ -74,15 +76,15 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFFSH 27 uses
DFFRH 17 uses
DFF 33 uses
DFFSH 28 uses
BI_DIR 11 uses
IBUF 32 uses
OBUF 16 uses
BUFTH 2 uses
AND2 241 uses
INV 181 uses
AND2 237 uses
INV 187 uses
DLATRH 1 use
XOR2 10 uses
OR2 28 uses
@ -95,6 +97,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Feb 13 14:39:11 2015
# Thu Feb 19 14:38:41 2015
###########################################################]

2
Logic/run_options.txt
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@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Fri Feb 13 14:39:10 2015
#-- Written on Thu Feb 19 14:38:39 2015
#project files

8
Logic/synlog/bus68030_fpga_mapper.srr
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@ -19,15 +19,15 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFFSH 27 uses
DFFRH 17 uses
DFF 33 uses
DFFSH 28 uses
BI_DIR 11 uses
IBUF 32 uses
OBUF 16 uses
BUFTH 2 uses
AND2 241 uses
INV 181 uses
AND2 237 uses
INV 187 uses
DLATRH 1 use
XOR2 10 uses
OR2 28 uses
@ -40,6 +40,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Feb 13 14:39:11 2015
# Thu Feb 19 14:38:41 2015
###########################################################]

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
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@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>16</data>
<data>17</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1423834750</data>
<data type="timestamp">1424353119</data>
</info>
</job_info>
</job_run_status>

1
Logic/synlog/report/BUS68030_compiler_warnings.txt
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@ -5,6 +5,7 @@
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
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@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>96MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1423834751</data>
<data type="timestamp">1424353121</data>
</info>
</job_info>
</job_run_status>

2
Logic/syntmp/run_option.xml
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@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Fri Feb 13 14:39:10 2015
Written on Thu Feb 19 14:38:39 2015
-->

2
Logic/synwork/BUS68030_compiler.fdep
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@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1423834746
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1424353112
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_compiler.fdeporig
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@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1423834746
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1424353112
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_compiler.srs
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Binary file not shown.

1
Logic/synwork/BUS68030_compiler.tlg
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@ -7,6 +7,7 @@
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3