mirror of https://github.com/kr239/68030tk.git
Adress bus on permanently
The adress bus is now on permanently. This is neccessary because some GARY-Adapters decode the address before AS
This commit is contained in:
parent
e60f9456e7
commit
f63a9b8ddf
|
@ -351,7 +351,8 @@ begin
|
||||||
RW_000_INT <= '1';
|
RW_000_INT <= '1';
|
||||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||||
AS_030_D0 = '0' AND --as set
|
AS_030_D0 = '0' AND --as set
|
||||||
BGACK_000='1' AND --no dma -cycle
|
BGACK_030_INT='1' AND
|
||||||
|
BGACK_030_INT_D='1' AND --no dma -cycle
|
||||||
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
||||||
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
|
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
|
||||||
SM_AMIGA = IDLE_P --last amiga cycle terminated
|
SM_AMIGA = IDLE_P --last amiga cycle terminated
|
||||||
|
@ -392,13 +393,12 @@ begin
|
||||||
case (SM_AMIGA) is
|
case (SM_AMIGA) is
|
||||||
when IDLE_P => --68000:S0 wait for a falling edge
|
when IDLE_P => --68000:S0 wait for a falling edge
|
||||||
RW_000_INT <= '1';
|
RW_000_INT <= '1';
|
||||||
|
AMIGA_BUS_ENABLE_INT <= CLK_000_D1;
|
||||||
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
||||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
|
||||||
SM_AMIGA<=IDLE_N; --go to s1
|
SM_AMIGA<=IDLE_N; --go to s1
|
||||||
else
|
|
||||||
AMIGA_BUS_ENABLE_INT <= '1';
|
|
||||||
end if;
|
end if;
|
||||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||||
|
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||||
if(CLK_000_PE='1')then --go to s2
|
if(CLK_000_PE='1')then --go to s2
|
||||||
--if(CLK_000_D0='1')then --go to s2
|
--if(CLK_000_D0='1')then --go to s2
|
||||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||||
|
@ -451,7 +451,8 @@ begin
|
||||||
if(CLK_000_PE='1')then --go to s0
|
if(CLK_000_PE='1')then --go to s0
|
||||||
--if(CLK_000_D0='1')then --go to s0
|
--if(CLK_000_D0='1')then --go to s0
|
||||||
SM_AMIGA<=IDLE_P;
|
SM_AMIGA<=IDLE_P;
|
||||||
RW_000_INT <= '1';
|
RW_000_INT <= '1';
|
||||||
|
--AMIGA_BUS_ENABLE_INT <= '1';
|
||||||
end if;
|
end if;
|
||||||
end case;
|
end case;
|
||||||
|
|
||||||
|
@ -537,7 +538,8 @@ begin
|
||||||
RESET <= RESET_OUT;
|
RESET <= RESET_OUT;
|
||||||
|
|
||||||
-- bus drivers
|
-- bus drivers
|
||||||
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
--AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||||
|
AMIGA_ADDR_ENABLE <= '0';
|
||||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE
|
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE
|
||||||
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
||||||
'1';
|
'1';
|
||||||
|
|
1098
Logic/68030_TK.tcl
1098
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -1,7 +1,7 @@
|
||||||
// Signal Name Cross Reference File
|
// Signal Name Cross Reference File
|
||||||
// ispLEVER Classic 1.7.00.05.28.13
|
// ispLEVER Classic 1.7.00.05.28.13
|
||||||
|
|
||||||
// Design '68030_tk' created Fri Feb 13 14:39:16 2015
|
// Design '68030_tk' created Thu Feb 19 14:38:45 2015
|
||||||
|
|
||||||
|
|
||||||
// LEGEND: '>' Functional Block Port Separator
|
// LEGEND: '>' Functional Block Port Separator
|
||||||
|
|
|
@ -1 +1,2 @@
|
||||||
<LATTICE_ENCRYPTED_BLIF>64577=5 8C0oHM
|
<LATTICE_ENCRYPTED_BLIF>6330162ñ
|
||||||
|
a*hO:!
|
|
@ -1,6 +1,6 @@
|
||||||
#-- Lattice Semiconductor Corporation Ltd.
|
#-- Lattice Semiconductor Corporation Ltd.
|
||||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||||
#-- Written on Fri Feb 13 14:39:09 2015
|
#-- Written on Thu Feb 19 14:38:38 2015
|
||||||
|
|
||||||
|
|
||||||
#device options
|
#device options
|
||||||
|
|
|
@ -6,7 +6,7 @@
|
||||||
#Implementation: logic
|
#Implementation: logic
|
||||||
|
|
||||||
$ Start of Compile
|
$ Start of Compile
|
||||||
#Fri Feb 13 14:39:10 2015
|
#Thu Feb 19 14:38:39 2015
|
||||||
|
|
||||||
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
||||||
@N|Running in 64-bit mode
|
@N|Running in 64-bit mode
|
||||||
|
@ -16,6 +16,7 @@ Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentatio
|
||||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
VHDL syntax check successful!
|
VHDL syntax check successful!
|
||||||
|
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_25 is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_25 is undriven
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:20|Signal clk_out_pre_33 is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:20|Signal clk_out_pre_33 is undriven
|
||||||
|
@ -25,6 +26,7 @@ VHDL syntax check successful!
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
||||||
Post processing for work.bus68030.behavioral
|
Post processing for work.bus68030.behavioral
|
||||||
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
||||||
|
@ -48,7 +50,7 @@ State machine has 8 reachable states with original encodings of:
|
||||||
111
|
111
|
||||||
@END
|
@END
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Fri Feb 13 14:39:10 2015
|
# Thu Feb 19 14:38:39 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
Map & Optimize Report
|
Map & Optimize Report
|
||||||
|
@ -74,15 +76,15 @@ original code -> new code
|
||||||
Resource Usage Report
|
Resource Usage Report
|
||||||
|
|
||||||
Simple gate primitives:
|
Simple gate primitives:
|
||||||
|
DFFSH 27 uses
|
||||||
DFFRH 17 uses
|
DFFRH 17 uses
|
||||||
DFF 33 uses
|
DFF 33 uses
|
||||||
DFFSH 28 uses
|
|
||||||
BI_DIR 11 uses
|
BI_DIR 11 uses
|
||||||
IBUF 32 uses
|
IBUF 32 uses
|
||||||
OBUF 16 uses
|
OBUF 16 uses
|
||||||
BUFTH 2 uses
|
BUFTH 2 uses
|
||||||
AND2 241 uses
|
AND2 237 uses
|
||||||
INV 181 uses
|
INV 187 uses
|
||||||
DLATRH 1 use
|
DLATRH 1 use
|
||||||
XOR2 10 uses
|
XOR2 10 uses
|
||||||
OR2 28 uses
|
OR2 28 uses
|
||||||
|
@ -95,6 +97,6 @@ Mapper successful!
|
||||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||||
|
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Fri Feb 13 14:39:11 2015
|
# Thu Feb 19 14:38:41 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
#-- Synopsys, Inc.
|
#-- Synopsys, Inc.
|
||||||
#-- Version G-2012.09LC-SP1
|
#-- Version G-2012.09LC-SP1
|
||||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||||
#-- Written on Fri Feb 13 14:39:10 2015
|
#-- Written on Thu Feb 19 14:38:39 2015
|
||||||
|
|
||||||
|
|
||||||
#project files
|
#project files
|
||||||
|
|
|
@ -19,15 +19,15 @@ original code -> new code
|
||||||
Resource Usage Report
|
Resource Usage Report
|
||||||
|
|
||||||
Simple gate primitives:
|
Simple gate primitives:
|
||||||
|
DFFSH 27 uses
|
||||||
DFFRH 17 uses
|
DFFRH 17 uses
|
||||||
DFF 33 uses
|
DFF 33 uses
|
||||||
DFFSH 28 uses
|
|
||||||
BI_DIR 11 uses
|
BI_DIR 11 uses
|
||||||
IBUF 32 uses
|
IBUF 32 uses
|
||||||
OBUF 16 uses
|
OBUF 16 uses
|
||||||
BUFTH 2 uses
|
BUFTH 2 uses
|
||||||
AND2 241 uses
|
AND2 237 uses
|
||||||
INV 181 uses
|
INV 187 uses
|
||||||
DLATRH 1 use
|
DLATRH 1 use
|
||||||
XOR2 10 uses
|
XOR2 10 uses
|
||||||
OR2 28 uses
|
OR2 28 uses
|
||||||
|
@ -40,6 +40,6 @@ Mapper successful!
|
||||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||||
|
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Fri Feb 13 14:39:11 2015
|
# Thu Feb 19 14:38:41 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
|
|
|
@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
|
||||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||||
</info>
|
</info>
|
||||||
<info name="Warnings">
|
<info name="Warnings">
|
||||||
<data>16</data>
|
<data>17</data>
|
||||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||||
</info>
|
</info>
|
||||||
<info name="Errors">
|
<info name="Errors">
|
||||||
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
||||||
<data>-</data>
|
<data>-</data>
|
||||||
</info>
|
</info>
|
||||||
<info name="Date &Time">
|
<info name="Date &Time">
|
||||||
<data type="timestamp">1423834750</data>
|
<data type="timestamp">1424353119</data>
|
||||||
</info>
|
</info>
|
||||||
</job_info>
|
</job_info>
|
||||||
</job_run_status>
|
</job_run_status>
|
|
@ -5,6 +5,7 @@
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
||||||
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
||||||
|
|
|
@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
|
||||||
<data>96MB</data>
|
<data>96MB</data>
|
||||||
</info>
|
</info>
|
||||||
<info name="Date & Time">
|
<info name="Date & Time">
|
||||||
<data type="timestamp">1423834751</data>
|
<data type="timestamp">1424353121</data>
|
||||||
</info>
|
</info>
|
||||||
</job_info>
|
</job_info>
|
||||||
</job_run_status>
|
</job_run_status>
|
||||||
|
|
|
@ -3,7 +3,7 @@
|
||||||
Synopsys, Inc.
|
Synopsys, Inc.
|
||||||
Version G-2012.09LC-SP1
|
Version G-2012.09LC-SP1
|
||||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||||
Written on Fri Feb 13 14:39:10 2015
|
Written on Thu Feb 19 14:38:39 2015
|
||||||
|
|
||||||
|
|
||||||
-->
|
-->
|
||||||
|
|
|
@ -10,7 +10,7 @@
|
||||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
||||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
||||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
||||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1423834746
|
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1424353112
|
||||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||||
|
|
||||||
# Dependency Lists (Uses list)
|
# Dependency Lists (Uses list)
|
||||||
|
|
|
@ -10,7 +10,7 @@
|
||||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
||||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
||||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
||||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1423834746
|
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1424353112
|
||||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||||
|
|
||||||
# Dependency Lists (Uses list)
|
# Dependency Lists (Uses list)
|
||||||
|
|
Binary file not shown.
|
@ -7,6 +7,7 @@
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
||||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
||||||
Post processing for work.bus68030.behavioral
|
Post processing for work.bus68030.behavioral
|
||||||
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
||||||
|
|
Loading…
Reference in New Issue