mirror of
https://github.com/kr239/68030tk.git
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Sources for GBA-TK060
This commit is contained in:
parent
aa7f8b7632
commit
fa0999c496
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@ -14,7 +14,7 @@ C3 100nF C0603K rcl (1503 1783) R0
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C4 100nF C0603K rcl (1209 1281) R180
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C4 100nF C0603K rcl (1209 1281) R180
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C5 100nF C0603K rcl (1873 2136) R90
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C5 100nF C0603K rcl (1873 2136) R90
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C6 100nF C0603K rcl (1708 2239) R0
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C6 100nF C0603K rcl (1708 2239) R0
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C7 15pF C0805K rcl (1187 3787) R0
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C7 n.b. C0805K rcl (1187 3787) R0
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C8 10オF C1210 rcl (432 1410) R270
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C8 10オF C1210 rcl (432 1410) R270
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C9 100nF C0603K rcl (374 3344) R0
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C9 100nF C0603K rcl (374 3344) R0
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C10 100nF C0603K rcl (1270 3416) R180
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C10 100nF C0603K rcl (1270 3416) R180
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@ -46,24 +46,24 @@ IC8 74HCT245DW SO20W 74xx-eu (402 2418) R90
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IC9 74HCT245DW SO20W 74xx-eu (402 1830) R90
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IC9 74HCT245DW SO20W 74xx-eu (402 1830) R90
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IC10 74HCT245DW SO20W 74xx-eu (408 972) R90
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IC10 74HCT245DW SO20W 74xx-eu (408 972) R90
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IC11 74HCT245DW SO20W 74xx-eu (414 360) R90
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IC11 74HCT245DW SO20W 74xx-eu (414 360) R90
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L1 R0805 rcl (234 3332) R0
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L1 4.7 R0805 rcl (234 3332) R0
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QG1 DIL14S crystal (544 3636) R0
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QG1 100MHz DIL14S crystal (544 3636) R0
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R1 10 R0805 rcl (1039 3787) R0
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R1 47 R0805 rcl (1039 3787) R0
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R2 4,7k R0603 rcl (2922 2070) R180
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R2 4,7k R0603 rcl (2922 2070) R180
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R3 4,7k R0603 rcl (3132 2430) R0
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R3 4,7k R0603 rcl (3132 2430) R0
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R4 4,7k R0603 rcl (2749 3524) R270
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R4 4,7k R0603 rcl (2749 3524) R270
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R5 4,7k R0603 rcl (2071 3770) R90
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R5 4,7k R0603 rcl (2071 3770) R90
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R6 4,7k R0603 rcl (2151 3770) R90
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R6 4,7k R0603 rcl (2151 3770) R90
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R7 10 R0603 rcl (2829 3524) R270
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R7 47 R0603 rcl (2829 3524) R270
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R8 4,7k R0603 rcl (1434 2930) R270
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R8 4,7k R0603 rcl (1434 2930) R270
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R9 4,7k R0603 rcl (3132 2544) R0
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R9 4,7k R0603 rcl (3132 2544) R0
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R10 R0603 rcl (1240 3103) R270
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R10 68 R0603 rcl (1240 3103) R270
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R11 R0603 rcl (1208 3221) R270
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R11 68 R0603 rcl (1208 3221) R270
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R12 4,7k R0603 rcl (2526 2082) R0
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R12 4,7k R0603 rcl (2526 2082) R0
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R13 4,7k R0603 rcl (3114 1302) R90
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R13 4,7k R0603 rcl (3114 1302) R90
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R14 R0603 rcl (2310 3372) R180
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R14 68 R0603 rcl (2310 3372) R180
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R15 4,7k R0603 rcl (2706 1974) R270
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R15 4,7k R0603 rcl (2706 1974) R270
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R16 R0603 rcl (1002 3516) R90
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R16 47 R0603 rcl (1002 3516) R90
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R17 4,7k R0603 rcl (3144 1482) R90
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R17 4,7k R0603 rcl (3144 1482) R90
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R18 4,7k R0603 rcl (606 1386) R90
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R18 4,7k R0603 rcl (606 1386) R90
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R19 4,7k R0603 rcl (2834 2176) R90
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R19 4,7k R0603 rcl (2834 2176) R90
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@ -20,7 +20,7 @@ port(
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UDS_000: inout std_logic;
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UDS_000: inout std_logic;
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LDS_000: inout std_logic;
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LDS_000: inout std_logic;
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SIZE: inout std_logic_vector ( 1 downto 0 );
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SIZE: inout std_logic_vector ( 1 downto 0 );
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A: in std_logic_vector ( 31 downto 16 );
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A: in std_logic_vector ( 31 downto 2 );
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A0: inout std_logic;
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A0: inout std_logic;
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A1: in std_logic;
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A1: in std_logic;
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nEXP_SPACE: in std_logic ;
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nEXP_SPACE: in std_logic ;
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@ -241,6 +241,7 @@ begin
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else
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else
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RESET_OUT <= '1';
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RESET_OUT <= '1';
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--now: 68000 state machine and signals
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--now: 68000 state machine and signals
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--buffering signals
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--buffering signals
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@ -364,7 +365,7 @@ begin
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end if;
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end if;
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when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
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when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
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DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
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DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
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if( CLK_000_NE='1' and --falling edge
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if( CLK_000_NE_D0='1' and --falling edge
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--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
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--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
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((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
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((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
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(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
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(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
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@ -540,7 +541,7 @@ begin
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--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
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--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
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CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
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CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
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'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
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'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
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'0'; --off for the Amiga
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'0'; --off for the Amiga
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@ -1,6 +1,6 @@
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[synthesis-type]
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tool=Synplify
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[STRATEGY-LIST]
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[STRATEGY-LIST]
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Normal=True, 1412327082
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Normal=True, 1412327082
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[TOUCHED-REPORT]
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[TOUCHED-REPORT]
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Design.impFile=1426423374
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Design.tt4File=1426539232
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[synthesis-type]
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tool=Synplify
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
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[Revision]
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[Revision]
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Parent = m4a5.lci;
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Parent = m4a5.lci;
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DATE = 03/15/2015;
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DATE = 03/16/2015;
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TIME = 13:42:54;
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TIME = 21:53:52;
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Source_Format = Pure_VHDL;
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Source_Format = Pure_VHDL;
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Synthesis = Synplify;
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Synthesis = Synplify;
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@ -98,6 +98,8 @@ AMIGA_BUS_ENABLE_HIGH = Pin, 34, -, D, -;
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A_23_ = Pin, 85, -, H, -;
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A_23_ = Pin, 85, -, H, -;
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FPU_SENSE = Pin, 91, -, A, -;
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FPU_SENSE = Pin, 91, -, A, -;
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A1 = Pin, 60, -, F, -;
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A1 = Pin, 60, -, F, -;
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A_3_ = Pin, 44, -, E, -;
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A_2_ = Pin, 43, -, E, -;
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[Group Assignments]
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[Group Assignments]
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layer = OFF;
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layer = OFF;
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@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
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[Revision]
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[Revision]
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Parent = m4a5.lci;
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Parent = m4a5.lci;
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DATE = 03/15/2015;
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DATE = 03/16/2015;
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TIME = 13:42:54;
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TIME = 21:53:52;
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Source_Format = Pure_VHDL;
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Source_Format = Pure_VHDL;
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Synthesis = Synplify;
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Synthesis = Synplify;
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@ -98,6 +98,8 @@ AMIGA_BUS_ENABLE_HIGH = Pin, 34, -, D, -;
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A_23_ = Pin, 85, -, H, -;
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A_23_ = Pin, 85, -, H, -;
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FPU_SENSE = Pin, 91, -, A, -;
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FPU_SENSE = Pin, 91, -, A, -;
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A1 = Pin, 60, -, F, -;
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A1 = Pin, 60, -, F, -;
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A_3_ = Pin, 44, -, E, -;
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A_2_ = Pin, 43, -, E, -;
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[Group Assignments]
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[Group Assignments]
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layer = OFF;
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layer = OFF;
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5609
Logic/68030_TK.tcl
5609
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
1112
Logic/68030_tk - DMA-Working@50MHz-060.jed
Normal file
1112
Logic/68030_tk - DMA-Working@50MHz-060.jed
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -1,7 +1,7 @@
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// Signal Name Cross Reference File
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// Signal Name Cross Reference File
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// ispLEVER Classic 1.8.00.04.29.14
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// ispLEVER Classic 1.8.00.04.29.14
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// Design '68030_tk' created Sun Mar 15 13:42:37 2015
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// Design '68030_tk' created Sat Mar 28 22:02:48 2015
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// LEGEND: '>' Functional Block Port Separator
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// LEGEND: '>' Functional Block Port Separator
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@ -1 +1 @@
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<LATTICE_ENCRYPTED_BLIF>7410610toyi|\
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<LATTICE_ENCRYPTED_BLIF>8775301*z5Kd
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@ -1,6 +1,6 @@
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#-- Lattice Semiconductor Corporation Ltd.
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#-- Lattice Semiconductor Corporation Ltd.
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#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
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#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
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#-- Written on Sun Mar 15 13:42:23 2015
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#-- Written on Sat Mar 28 22:02:32 2015
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#device options
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#device options
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@ -19,8 +19,8 @@
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<BScanVal>0</BScanVal>
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<BScanVal>0</BScanVal>
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</Bypass>
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</Bypass>
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<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
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<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
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<FileTime>03/15/15 13:43:06</FileTime>
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<FileTime>03/15/15 19:56:52</FileTime>
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<JedecChecksum>0x2570</JedecChecksum>
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<JedecChecksum>0x7A4C</JedecChecksum>
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<Operation>Erase,Program,Verify</Operation>
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<Operation>Erase,Program,Verify</Operation>
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<Option>
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<Option>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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<SVFVendor>JTAG STANDARD</SVFVendor>
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@ -6,7 +6,7 @@
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#Implementation: logic
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#Implementation: logic
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$ Start of Compile
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$ Start of Compile
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#Sun Mar 15 13:42:30 2015
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#Sat Mar 28 22:02:40 2015
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Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
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Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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@ -14,7 +14,9 @@ Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated document
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@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
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@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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VHDL syntax check successful!
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VHDL syntax check successful!
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File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
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@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
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@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
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@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
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Post processing for work.bus68030.behavioral
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Post processing for work.bus68030.behavioral
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@ -23,7 +25,7 @@ Post processing for work.bus68030.behavioral
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_030_D0_2
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@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2
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@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
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@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
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@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
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@ -38,20 +40,22 @@ State machine has 8 reachable states with original encodings of:
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110
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110
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111
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111
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
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@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
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@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
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@END
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@END
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sun Mar 15 13:42:30 2015
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# Sat Mar 28 22:02:41 2015
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###########################################################]
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###########################################################]
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Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
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Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
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@N|Running in 64-bit mode
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@N|Running in 64-bit mode
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File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Sun Mar 15 13:42:32 2015
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# Sat Mar 28 22:02:43 2015
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###########################################################]
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###########################################################]
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@ -27,8 +27,8 @@ SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
|
||||||
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
|
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
|
||||||
SR<qM3="lkF8DHCVDRC"P(=""
|
SR<qM3="lkF8DHCVDRC"P(=""
|
||||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.j"
|
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.j"
|
||||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
|
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=j43j6jnj"
|
||||||
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjn46j/j">S
|
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjjjjj/j">S
|
||||||
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
|
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
|
||||||
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/
|
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/
|
||||||
/S<7>CV
|
/S<7>CV
|
||||||
|
|
|
@ -1 +1 @@
|
||||||
-src 68030_tk.tt4 -type PLA -devfile "C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -postfit -lci 68030_tk.lco
|
-src 68030_tk.tt4 -type PLA -devfile "C:/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -lci "68030_tk.lct" -touch "68030_tk.tt4"
|
||||||
|
|
|
@ -1,7 +1,7 @@
|
||||||
#-- Synopsys, Inc.
|
#-- Synopsys, Inc.
|
||||||
#-- Version I-2014.03LC
|
#-- Version I-2014.03LC
|
||||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||||
#-- Written on Sun Mar 15 13:42:30 2015
|
#-- Written on Sat Mar 28 22:02:40 2015
|
||||||
|
|
||||||
|
|
||||||
#project files
|
#project files
|
||||||
|
|
|
@ -1,9 +1,10 @@
|
||||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||||
@N|Running in 64-bit mode
|
@N|Running in 64-bit mode
|
||||||
|
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||||
|
|
||||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||||
|
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Sun Mar 15 13:42:32 2015
|
# Sat Mar 28 22:02:43 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
|
|
|
@ -12,7 +12,7 @@ original code -> new code
|
||||||
101 -> 00100001
|
101 -> 00100001
|
||||||
110 -> 01000001
|
110 -> 01000001
|
||||||
111 -> 10000001
|
111 -> 10000001
|
||||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:4:183:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":187:4:187:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||||
---------------------------------------
|
---------------------------------------
|
||||||
Resource Usage Report
|
Resource Usage Report
|
||||||
|
@ -20,13 +20,13 @@ Resource Usage Report
|
||||||
Simple gate primitives:
|
Simple gate primitives:
|
||||||
DFF 73 uses
|
DFF 73 uses
|
||||||
BI_DIR 11 uses
|
BI_DIR 11 uses
|
||||||
IBUF 32 uses
|
IBUF 46 uses
|
||||||
OBUF 16 uses
|
OBUF 16 uses
|
||||||
BUFTH 2 uses
|
BUFTH 2 uses
|
||||||
AND2 269 uses
|
AND2 270 uses
|
||||||
INV 240 uses
|
INV 229 uses
|
||||||
OR2 28 uses
|
OR2 26 uses
|
||||||
XOR2 5 uses
|
XOR2 4 uses
|
||||||
|
|
||||||
|
|
||||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||||
|
@ -36,6 +36,6 @@ Mapper successful!
|
||||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||||
|
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Sun Mar 15 13:42:32 2015
|
# Sat Mar 28 22:02:43 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
|
|
|
@ -1,4 +1,3 @@
|
||||||
@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":508:5:508:16|No matching overload for "or"
|
@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":543:65:543:65|No identifier "a2" in scope
|
||||||
@E: CD308 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":508:5:508:22|Unable to evaluate expression type
|
@E|Parse errors encountered - exiting
|
||||||
@E: CD676 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":508:5:508:22|Can't implement expression (no function signature?)
|
|
||||||
|
|
||||||
|
|
|
@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
|
||||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||||
</info>
|
</info>
|
||||||
<info name="Warnings">
|
<info name="Warnings">
|
||||||
<data>9</data>
|
<data>10</data>
|
||||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||||
</info>
|
</info>
|
||||||
<info name="Errors">
|
<info name="Errors">
|
||||||
|
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
|
||||||
<data>-</data>
|
<data>-</data>
|
||||||
</info>
|
</info>
|
||||||
<info name="Date &Time">
|
<info name="Date &Time">
|
||||||
<data type="timestamp">1426423350</data>
|
<data type="timestamp">1427576561</data>
|
||||||
</info>
|
</info>
|
||||||
</job_info>
|
</job_info>
|
||||||
</job_run_status>
|
</job_run_status>
|
|
@ -4,7 +4,8 @@
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_030_D0_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2
|
||||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||||
|
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
|
||||||
|
|
||||||
|
|
|
@ -1,3 +1,3 @@
|
||||||
@N: MF248 |Running in 64-bit mode.
|
@N: MF248 |Running in 64-bit mode.
|
||||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:4:183:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":187:4:187:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||||
|
|
|
@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
|
||||||
<data>105MB</data>
|
<data>105MB</data>
|
||||||
</info>
|
</info>
|
||||||
<info name="Date & Time">
|
<info name="Date & Time">
|
||||||
<data type="timestamp">1426423352</data>
|
<data type="timestamp">1427576563</data>
|
||||||
</info>
|
</info>
|
||||||
</job_info>
|
</job_info>
|
||||||
</job_run_status>
|
</job_run_status>
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
<html><body><samp><pre>
|
<html><body><samp><pre>
|
||||||
<!@TC:1426423350>
|
<!@TC:1427576560>
|
||||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||||
#install: C:\ispLever\synpbase
|
#install: C:\ispLever\synpbase
|
||||||
#OS: Windows 7 6.1
|
#OS: Windows 7 6.1
|
||||||
|
@ -8,27 +8,29 @@
|
||||||
#Implementation: logic
|
#Implementation: logic
|
||||||
|
|
||||||
<a name=compilerReport1>$ Start of Compile</a>
|
<a name=compilerReport1>$ Start of Compile</a>
|
||||||
#Sun Mar 15 13:42:30 2015
|
#Sat Mar 28 22:02:40 2015
|
||||||
|
|
||||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||||
@N: : <!@TM:1426423350> | Running in 64-bit mode
|
@N: : <!@TM:1427576561> | Running in 64-bit mode
|
||||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||||
|
|
||||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1426423350> | Setting time resolution to ns
|
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1427576561> | Setting time resolution to ns
|
||||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1426423350> | Top entity is set to BUS68030.
|
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1427576561> | Top entity is set to BUS68030.
|
||||||
|
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
VHDL syntax check successful!
|
VHDL syntax check successful!
|
||||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1426423350> | Synthesizing work.bus68030.behavioral
|
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1426423350> | Signal clk_out_pre is undriven </font>
|
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1427576561> | Synthesizing work.bus68030.behavioral
|
||||||
|
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1427576561> | Signal clk_out_pre is undriven </font>
|
||||||
Post processing for work.bus68030.behavioral
|
Post processing for work.bus68030.behavioral
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1426423350> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1427576561> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1426423350> | Pruning register CLK_000_D4_2 </font>
|
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1427576561> | Pruning register CLK_000_D4_2 </font>
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1426423350> | Pruning register CLK_000_D3_2 </font>
|
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1427576561> | Pruning register CLK_000_D3_2 </font>
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:34:129:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1426423350> | Pruning register CLK_000_D2_2 </font>
|
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:34:129:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1427576561> | Pruning register CLK_000_D2_2 </font>
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1426423350> | Pruning register CLK_OUT_PRE_50_D_2 </font>
|
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1427576561> | Pruning register CLK_OUT_PRE_50_D_2 </font>
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:148:2:148:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(148)</a><!@TM:1426423350> | Pruning register CLK_030_D0_2 </font>
|
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:152:2:152:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(152)</a><!@TM:1427576561> | Pruning register CLK_030_D0_2 </font>
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:61:133:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1426423350> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:61:133:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1427576561> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1426423350> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1427576561> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1426423350> | Trying to extract state machine for register SM_AMIGA
|
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1427576561> | Trying to extract state machine for register SM_AMIGA
|
||||||
Extracted state machine for register SM_AMIGA
|
Extracted state machine for register SM_AMIGA
|
||||||
State machine has 8 reachable states with original encodings of:
|
State machine has 8 reachable states with original encodings of:
|
||||||
000
|
000
|
||||||
|
@ -39,22 +41,24 @@ State machine has 8 reachable states with original encodings of:
|
||||||
101
|
101
|
||||||
110
|
110
|
||||||
111
|
111
|
||||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1426423350> | Trying to extract state machine for register cpu_est
|
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1427576561> | Trying to extract state machine for register cpu_est
|
||||||
|
<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1427576561> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
|
||||||
@END
|
@END
|
||||||
|
|
||||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||||
|
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Sun Mar 15 13:42:30 2015
|
# Sat Mar 28 22:02:41 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||||
@N: : <!@TM:1426423352> | Running in 64-bit mode
|
@N: : <!@TM:1427576563> | Running in 64-bit mode
|
||||||
|
File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
|
||||||
|
|
||||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||||
|
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Sun Mar 15 13:42:32 2015
|
# Sat Mar 28 22:02:43 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
Map & Optimize Report
|
Map & Optimize Report
|
||||||
|
@ -62,7 +66,7 @@ Map & Optimize Report
|
||||||
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
||||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||||
Product Version I-2014.03LC
|
Product Version I-2014.03LC
|
||||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1426423352> | Running in 64-bit mode.
|
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1427576563> | Running in 64-bit mode.
|
||||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||||
original code -> new code
|
original code -> new code
|
||||||
000 -> 00000000
|
000 -> 00000000
|
||||||
|
@ -73,31 +77,31 @@ original code -> new code
|
||||||
101 -> 00100001
|
101 -> 00100001
|
||||||
110 -> 01000001
|
110 -> 01000001
|
||||||
111 -> 10000001
|
111 -> 10000001
|
||||||
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:183:4:183:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(183)</a><!@TM:1426423352> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:187:4:187:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(187)</a><!@TM:1427576563> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1426423352> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1427576563> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||||
---------------------------------------
|
---------------------------------------
|
||||||
<a name=resourceUsage3>Resource Usage Report</a>
|
<a name=resourceUsage3>Resource Usage Report</a>
|
||||||
|
|
||||||
Simple gate primitives:
|
Simple gate primitives:
|
||||||
DFF 73 uses
|
DFF 73 uses
|
||||||
BI_DIR 11 uses
|
BI_DIR 11 uses
|
||||||
IBUF 32 uses
|
IBUF 46 uses
|
||||||
OBUF 16 uses
|
OBUF 16 uses
|
||||||
BUFTH 2 uses
|
BUFTH 2 uses
|
||||||
AND2 269 uses
|
AND2 270 uses
|
||||||
INV 240 uses
|
INV 229 uses
|
||||||
OR2 28 uses
|
OR2 26 uses
|
||||||
XOR2 5 uses
|
XOR2 4 uses
|
||||||
|
|
||||||
|
|
||||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1426423352> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1427576563> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||||
I-2014.03LC
|
I-2014.03LC
|
||||||
Mapper successful!
|
Mapper successful!
|
||||||
|
|
||||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||||
|
|
||||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||||
# Sun Mar 15 13:42:32 2015
|
# Sat Mar 28 22:02:43 2015
|
||||||
|
|
||||||
###########################################################]
|
###########################################################]
|
||||||
|
|
||||||
|
|
|
@ -16,7 +16,7 @@
|
||||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||||
<ul rel="open" >
|
<ul rel="open" >
|
||||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (13:42 15-Mar)</a>
|
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (22:02 28-Mar)</a>
|
||||||
<ul ></ul></li> </ul>
|
<ul ></ul></li> </ul>
|
||||||
</li>
|
</li>
|
||||||
</ul>
|
</ul>
|
||||||
|
|
|
@ -3,7 +3,7 @@
|
||||||
Synopsys, Inc.
|
Synopsys, Inc.
|
||||||
Version I-2014.03LC
|
Version I-2014.03LC
|
||||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||||
Written on Sun Mar 15 13:42:30 2015
|
Written on Sat Mar 28 22:02:40 2015
|
||||||
|
|
||||||
|
|
||||||
-->
|
-->
|
||||||
|
|
|
@ -33,12 +33,12 @@
|
||||||
<tr>
|
<tr>
|
||||||
<td class="optionTitle">Compile Input</td><td>Complete</td>
|
<td class="optionTitle">Compile Input</td><td>Complete</td>
|
||||||
<td>6</td>
|
<td>6</td>
|
||||||
<td>9</td>
|
<td>10</td>
|
||||||
<td>0</td>
|
<td>0</td>
|
||||||
<td>-</td>
|
<td>-</td>
|
||||||
<td>0m:01s</td>
|
<td>0m:01s</td>
|
||||||
<td>-</td>
|
<td>-</td>
|
||||||
<td><font size="-1">15.03.2015</font><br/><font size="-2">13:42:30</font></td>
|
<td><font size="-1">28.03.2015</font><br/><font size="-2">22:02:41</font></td>
|
||||||
</tr>
|
</tr>
|
||||||
|
|
||||||
<tr>
|
<tr>
|
||||||
|
@ -49,12 +49,12 @@
|
||||||
<td>0m:00s</td>
|
<td>0m:00s</td>
|
||||||
<td>0m:00s</td>
|
<td>0m:00s</td>
|
||||||
<td>105MB</td>
|
<td>105MB</td>
|
||||||
<td><font size="-1">15.03.2015</font><br/><font size="-2">13:42:32</font></td>
|
<td><font size="-1">28.03.2015</font><br/><font size="-2">22:02:43</font></td>
|
||||||
</tr>
|
</tr>
|
||||||
|
|
||||||
<tr>
|
<tr>
|
||||||
<td class="optionTitle">Multi-srs Generator</td>
|
<td class="optionTitle">Multi-srs Generator</td>
|
||||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">15.03.2015</font><br/><font size="-2">13:42:32</font></td> </tbody>
|
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:01s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">28.03.2015</font><br/><font size="-2">22:02:43</font></td> </tbody>
|
||||||
</table>
|
</table>
|
||||||
</td></tr></table></body>
|
</td></tr></table></body>
|
||||||
</html>
|
</html>
|
|
@ -9,7 +9,7 @@
|
||||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1426423340
|
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1427576546
|
||||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||||
|
|
||||||
# Dependency Lists (Uses list)
|
# Dependency Lists (Uses list)
|
||||||
|
|
|
@ -9,7 +9,7 @@
|
||||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1426423340
|
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1427576546
|
||||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||||
|
|
||||||
# Dependency Lists (Uses list)
|
# Dependency Lists (Uses list)
|
||||||
|
|
Binary file not shown.
|
@ -6,7 +6,7 @@ Post processing for work.bus68030.behavioral
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_030_D0_2
|
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":152:2:152:3|Pruning register CLK_030_D0_2
|
||||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
||||||
|
@ -21,3 +21,4 @@ State machine has 8 reachable states with original encodings of:
|
||||||
110
|
110
|
||||||
111
|
111
|
||||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
||||||
|
@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused
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