mirror of https://github.com/kr239/68030tk.git
Reset-Problem solved
The AMiga was not able to recover from a reste, because the e-clock was not generated properly during reste.
This commit is contained in:
MHeinrichs
parent
f63a9b8ddf
commit
aa7f8b7632
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,6 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.5.0">
|
||||
<eagle version="6.4">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="yes"/>
|
||||
|
|
@ -18,7 +18,7 @@
|
|||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
|
|
@ -71,9 +71,9 @@
|
|||
<dimension x1="0" y1="100" x2="0" y2="0" x3="-20.4216" y3="50" textsize="1.778" layer="20"/>
|
||||
<text x="2.794" y="90.2208" size="1.778" layer="1" ratio="20" rot="R90">TOP</text>
|
||||
<text x="1.016" y="90.3732" size="1.778" layer="16" ratio="20" rot="MR90">Bot</text>
|
||||
<text x="8.128" y="43.9928" size="1.016" layer="16" ratio="20" rot="MR90">a1k.org 68030-TK v0.9d
|
||||
(c) 2013 Matthias Heinrichs
|
||||
thx Buko Charly</text>
|
||||
<text x="8.128" y="43.9928" size="1.016" layer="16" ratio="20" distance="51" rot="MR90">a1k.org 68030-TK v0.9d
|
||||
(c) 2014 Matthias Heinrichs
|
||||
thx BukoCharly, Georg Braun, Herzi</text>
|
||||
<text x="22.9616" y="55.0672" size="1.016" layer="25" ratio="20" rot="R90">a1k.org 68030-TK V0.9
|
||||
(c)2013 Matthias Heinrichs
|
||||
Free for non commercial
|
||||
|
|
@ -2844,7 +2844,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<attribute name="VALUE" x="29.591" y="79.4512" size="1.27" layer="27" rot="R270"/>
|
||||
</element>
|
||||
<element name="R11" library="rcl" package="R0603" value="" x="30.6832" y="81.8134" smashed="yes" rot="R270">
|
||||
<attribute name="NAME" x="28.575" y="83.2104" size="0.8128" layer="25" rot="R270"/>
|
||||
<attribute name="NAME" x="28.7274" y="82.9056" size="0.8128" layer="25" rot="R270"/>
|
||||
<attribute name="VALUE" x="28.7782" y="82.4484" size="1.27" layer="27" rot="R270"/>
|
||||
</element>
|
||||
<element name="R14" library="rcl" package="R0603" value="" x="58.674" y="85.6488" smashed="yes" rot="R180">
|
||||
|
|
@ -6469,55 +6469,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="72.2376" y1="49.7468" x2="72.2376" y2="52.578" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0748" y1="57.7596" x2="65.0748" y2="55.0808" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0748" y1="55.0808" x2="65.0104" y2="55.0164" width="0.1524" layer="1"/>
|
||||
<wire x1="69.8246" y1="88.6596" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2328" y1="98.4504" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6354" y1="96.608" x2="57.1754" y2="98.4788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2896" y1="94.8172" x2="52.6034" y2="96.608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="86.5124" x2="44.1452" y2="93.726" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.323" y1="80.4418" x2="49.9872" y2="86.5124" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.4236" y1="75.272" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.133" y1="86.7664" x2="34.7256" y2="81.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="60.5028" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9062" y1="57.9628" x2="41.9862" y2="57.3926" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.5742" y1="53.3794" x2="42.5082" y2="56.8706" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="57.9628" x2="48.7172" y2="53.3908" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="52.8828" x2="52.1462" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="47.8028" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="53.34" y1="45.1104" x2="54.6862" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="42.7228" x2="52.1716" y2="44.7942" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.8262" y1="52.8828" x2="36.9062" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="47.8028" x2="31.8262" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3012" y1="45.2882" x2="34.3662" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="40.1828" x2="37.2872" y2="43.1038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.0104" y1="52.8828" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="68.7324" y1="49.2896" x2="65.0104" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.2376" y1="49.7468" x2="68.7324" y2="49.2896" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.424" y1="46.6344" x2="72.9116" y2="49.0728" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="79.8576" y1="36.7928" x2="75.4126" y2="44.6278" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.3872" y1="31.4084" x2="79.0956" y2="33.9208" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.7908" y1="28.868" x2="75.3872" y2="29.6164" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.8764" y1="24.9056" x2="78.7908" y2="28.194" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.724" y1="61.722" x2="71.9836" y2="54.4204" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="23.5712" x2="77.8764" y2="23.4696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="21.0312" x2="87.63" y2="23.5712" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="18.4912" x2="87.63" y2="21.0312" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.5976" y1="33.5788" x2="36.9062" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="35.2806" x2="31.5836" y2="33.5648" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="19.2786" x2="33.3134" y2="26.8986" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="34.3544" x2="24.7904" y2="35.2806" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="37.214" x2="15.3924" y2="34.3544" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="38.862" x2="10.9728" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="40.3606" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="6.5786" x2="33.3134" y2="16.7386" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.513" y1="32.4612" x2="52.1462" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="18.0086" x2="55.1434" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="12.5192" x2="61.4172" y2="17.4104" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.932" y1="5.0686" x2="65.5828" y2="12.5192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.0686" y1="53.9496" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="69.0372" x2="5.1816" y2="55.7022" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="4.9428" y1="84.582" x2="5.1816" y2="70.9422" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.334" y1="18.9738" x2="15.3924" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.4864" y1="3.429" x2="5.334" y2="16.1544" width="0" layer="19" extent="1-1"/>
|
||||
</signal>
|
||||
<signal name="GND">
|
||||
<contactref element="IC2" pad="16"/>
|
||||
|
|
@ -6651,8 +6602,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="44.2896" y1="77.4132" x2="44.8678" y2="76.835" width="0.3048" layer="1"/>
|
||||
<via x="62.992" y="58.0136" extent="1-16" drill="0.3"/>
|
||||
<via x="69.7484" y="58.42" extent="1-16" drill="0.3"/>
|
||||
<wire x1="62.8396" y1="55.372" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="64.0588" y1="55.3212" x2="64.0588" y2="55.3212" width="0" layer="19" extent="1-16"/>
|
||||
<via x="60.7568" y="86.5124" extent="1-16" drill="0.3"/>
|
||||
<via x="46.5328" y="84.4804" extent="1-16" drill="0.3"/>
|
||||
<via x="72.6948" y="84.328" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6980,204 +6929,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="15.24" y1="42.037" x2="16.764" y2="42.037" width="0.1524" layer="1"/>
|
||||
<wire x1="16.764" y1="42.037" x2="16.7894" y2="42.0624" width="0.1524" layer="1"/>
|
||||
<contactref element="R24" pad="2"/>
|
||||
<wire x1="85.7504" y1="96.1644" x2="86.5124" y2="98.7552" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.7316" y1="93.8784" x2="85.7504" y2="96.1644" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.9988" y1="93.5736" x2="87.7316" y2="93.8784" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.473" y1="90.354" x2="81.5532" y2="95.7202" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.7428" y1="88.4428" x2="75.7428" y2="89.9668" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.8952" y1="68.707" x2="78.473" y2="68.5228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.5904" y1="67.2846" x2="75.8952" y2="68.707" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="74.3204" y1="94.3102" x2="76.13" y2="90.354" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.6948" y1="84.328" x2="75.7428" y2="88.4428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="73.2028" y1="61.4172" x2="75.5904" y2="67.2846" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="69.7484" y1="58.42" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.8688" y1="60.8076" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.0588" y1="55.3212" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.8396" y1="55.372" x2="64.0588" y2="55.3212" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="58.0136" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.5556" y1="56.9976" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.6224" y1="57.0484" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.6232" y1="48.8696" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="50.3428" x2="58.6232" y2="48.8696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1716" y1="47.6504" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="45.2628" x2="52.1716" y2="46.5442" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.8188" y1="47.3964" x2="52.1716" y2="47.6504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.1452" y1="48.768" x2="48.8188" y2="47.3964" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="55.4228" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.0512" y1="46.496" x2="44.1452" y2="48.768" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.592" y1="47.7012" x2="39.0144" y2="46.5328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="50.2412" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="50.3428" x2="36.9824" y2="50.2412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="52.8828" x2="34.3662" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="55.4228" x2="34.3662" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="55.4228" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.7068" y1="43.688" x2="39.0512" y2="45.2882" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="30.5816" y1="54.2036" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.194" y1="57.2516" x2="30.5816" y2="54.2036" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="45.2628" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="40.1828" x2="41.7068" y2="43.688" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="54.356" x2="28.194" y2="57.2516" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.876" y1="51.7652" x2="24.7904" y2="54.356" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7396" y1="49.276" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="46.6852" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="44.9072" x2="24.7904" y2="46.6852" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="42.0116" x2="20.9804" y2="44.9072" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="40.3606" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.7894" y1="42.0624" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="14.2748" y1="37.8968" x2="15.24" y2="42.037" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.21" y1="49.022" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="40.1828" x2="41.7068" y2="43.688" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.0662" y1="40.1828" x2="44.5262" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.0314" y1="38.3286" x2="47.0662" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="40.1828" x2="48.0314" y2="38.3286" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="34.414" x2="14.2748" y2="37.8968" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3416" y1="32.1056" x2="10.9728" y2="32.766" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="30.4038" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="32.1056" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.7612" y1="34.2392" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="31.496" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="28.9052" x2="24.7904" y2="31.496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="25.7302" y1="28.829" x2="24.7904" y2="28.9052" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.718" y1="31.3944" x2="25.7302" y2="28.829" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="37.6428" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.16" y1="41.2496" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.798" y1="30.1244" x2="29.8336" y2="31.51" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.0934" y1="30.1244" x2="34.8234" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3634" y1="28.4086" x2="36.0934" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.6334" y1="30.099" x2="37.3634" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.9034" y1="28.4086" x2="38.6334" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="24.3586" x2="34.8234" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="22.2504" x2="31.9278" y2="24.3586" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="60.5028" x2="36.9824" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="60.5028" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2976" y1="57.9628" x2="44.5262" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="57.9628" x2="44.2976" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.3616" y1="57.9628" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.766" y1="55.3212" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="60.5028" x2="48.3616" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.956" y1="16.3462" x2="31.623" y2="21.8186" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.608" y1="11.9888" x2="33.3134" y2="15.4686" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.4688" y1="14.1224" x2="38.6334" y2="11.9634" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="14.1224" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="14.1224" x2="43.688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.228" y1="14.1224" x2="44.958" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.1076" y1="14.1224" x2="46.228" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.418" y1="19.8628" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="19.9136" x2="42.418" y2="19.8628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="19.9136" x2="43.688" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.2788" y1="19.9136" x2="44.958" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.102" y1="12.6492" x2="48.1076" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="15.4686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.1952" y1="17.1704" x2="61.214" y2="15.4572" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="18.1864" x2="63.1952" y2="17.1704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="16.7132" x2="65.3288" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="19.9136" x2="63.8048" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.7672" y1="15.2908" x2="65.5828" y2="15.3192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.5216" y1="19.9644" x2="62.992" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="52.2732" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="53.594" x2="15.24" y2="52.197" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.8808" y1="67.5132" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="5.0686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.2356" y1="3.7592" x2="52.6034" y2="3.683" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="3.7592" x2="56.2356" y2="3.7592" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.4116" y1="90.5256" x2="74.3204" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.1604" y1="94.3102" x2="67.4116" y2="90.5256" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="61.6712" y1="97.3836" x2="64.1604" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="95.6564" x2="61.6712" y2="97.3836" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="51.7896" y1="92.8172" x2="57.1754" y2="95.6788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.7896" y1="94.8172" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="98.3488" x2="49.276" y2="96.2152" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.212" y1="97.1296" x2="47.4472" y2="98.3488" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="94.8172" x2="43.2896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7632" y1="94.6912" x2="37.7896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.6108" y1="97.6884" x2="37.7896" y2="96.4636" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.5788" y1="97.6884" x2="35.6108" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="96.1484" x2="33.5788" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="87.4776" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="48.6156" y1="84.7344" x2="50.6476" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.2896" y1="78.8172" x2="49.3324" y2="80.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.5328" y1="84.4804" x2="48.6156" y2="84.7344" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.5676" y1="86.9696" x2="46.5328" y2="84.4804" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.7736" y1="86.3346" x2="45.5676" y2="86.9696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.9768" y1="84.9884" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.4342" y1="86.4108" x2="51.7896" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.7568" y1="86.5124" x2="56.4388" y2="86.4108" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.8678" y1="76.835" x2="49.6824" y2="76.8096" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.338" y1="86.8172" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7896" y1="86.8172" x2="37.338" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.383" y1="86.7664" x2="34.4424" y2="86.5632" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="78.8172" x2="43.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.8762" y1="79.0956" x2="37.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.9314" y1="24.7142" x2="15.3924" y2="30.4038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="16.8656" x2="9.9314" y2="24.7142" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="13.8176" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="12.1412" x2="10.3124" y2="13.8176" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.1234" y1="17.2212" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="8.0264" x2="10.3124" y2="12.1412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="13.6652" y1="8.0264" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.7028" y1="4.826" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="8.2296" y1="1.6764" x2="9.7028" y2="4.826" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="2.7432" y1="0.9144" x2="7.1234" y2="1.6764" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.778" y1="0.9144" x2="2.7432" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="0.8636" y1="0.9144" x2="1.778" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.494" y1="16.5608" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.5448" y1="14.859" x2="15.494" y2="16.5608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="3.1496" x2="13.6652" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.2852" y1="2.3876" x2="19.9136" y2="3.1496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="26.4668" y1="5.9944" x2="21.2852" y2="2.3876" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.114" y1="95.0468" x2="31.1912" y2="94.8944" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="18.9992" y1="97.3328" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="17.018" y1="95.1992" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.256" y1="98.7044" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.4376" y1="88.5444" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="82.4484" x2="21.4376" y2="88.5444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="83.7692" x2="15.24" y2="82.3722" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3746" y1="84.9376" x2="15.1892" y2="83.7692" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.5692" y1="82.3976" x2="10.3746" y2="84.9376" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.8288" y1="83.3628" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.922" y1="77.3684" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="53.7578" x2="15.1892" y2="53.594" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="71.4248" y1="49.6824" x2="64.0588" y2="55.3212" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.5424" y1="46.6344" x2="71.4248" y2="49.6824" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.867" y1="46.482" x2="73.6486" y2="46.609" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.1906" y1="39.5224" x2="78.867" y2="46.482" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="80.1624" y1="34.5948" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.7956" y1="31.75" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.1888" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="32.3088" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="68.6816" x2="10.922" y2="77.3684" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="68.9978" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="68.9864" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.24" y1="67.1322" x2="15.1892" y2="68.9864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="30.2006" x2="7.0104" y2="37.6428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="29.8704" x2="48.0314" y2="38.3286" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="57.2516" y1="30.1752" x2="52.6034" y2="29.8704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.4332" y1="35.1536" x2="57.263" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.3476" y1="33.4772" x2="62.4332" y2="35.1536" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="31.1912" x2="63.6016" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.3412" y1="83.2104" x2="78.473" y2="83.3436" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="72.9996" x2="78.473" y2="72.828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="62.9412" x2="88.4936" y2="72.9996" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="62.7888" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="52.8828" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="42.672" x2="88.4936" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="22.2504" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="15.9512" x2="88.4936" y2="22.2504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="13.4112" x2="87.63" y2="15.9512" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="12.192" x2="87.63" y2="13.4112" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.694" y1="12.3444" x2="88.4936" y2="12.192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="2.3368" x2="91.694" y2="12.3444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="1.2192" x2="91.6432" y2="2.3368" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="90.2716" y1="1.2192" x2="91.6432" y2="1.2192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="97.9932" x2="1.8288" y2="83.3628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="98.9076" x2="1.016" y2="97.9932" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.0104" y1="50.7492" x2="65.0104" y2="48.0704" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0104" y1="48.0704" x2="66.1416" y2="46.9392" width="0.1524" layer="1"/>
|
||||
<wire x1="66.1416" y1="46.9392" x2="66.1416" y2="45.72" width="0.1524" layer="1"/>
|
||||
<via x="66.1416" y="45.72" extent="1-16" drill="0.3"/>
|
||||
<wire x1="66.1416" y1="45.72" x2="66.5988" y2="45.72" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="66.5988" y1="45.72" x2="66.7512" y2="45.8724" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="66.7512" y1="45.8724" x2="72.5424" y2="46.6344" width="0" layer="19" extent="1-16"/>
|
||||
</signal>
|
||||
<signal name="A27">
|
||||
<wire x1="82.55" y1="69.2912" x2="75.3872" y2="69.2912" width="0.1524" layer="16"/>
|
||||
|
|
@ -8247,16 +8002,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="6.5532" y1="72.6948" x2="6.096" y2="72.2376" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
</signals>
|
||||
<errors>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,a0a8a9f4a989a0d5"/>
|
||||
<approved hash="18,30,93e4923c922593fd"/>
|
||||
</errors>
|
||||
</board>
|
||||
</drawing>
|
||||
<compatibility>
|
||||
|
|
|
|||
|
|
@ -2720,8 +2720,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<element name="R2" library="rcl" package="R0603" value="4,7k" x="74.2188" y="52.578" smashed="yes" rot="R180">
|
||||
<attribute name="NAME" x="75.1586" y="54.3814" size="0.8128" layer="25" rot="R180"/>
|
||||
</element>
|
||||
<element name="R12" library="rcl" package="R0603" value="4,7k" x="64.1604" y="50.7492" smashed="yes">
|
||||
<attribute name="NAME" x="63.2206" y="49.2506" size="0.8128" layer="25"/>
|
||||
<element name="R12" library="rcl" package="R0603" value="4,7k" x="64.1604" y="52.8828" smashed="yes">
|
||||
<attribute name="NAME" x="65.8114" y="52.6034" size="0.8128" layer="25"/>
|
||||
</element>
|
||||
<element name="R13" library="rcl" package="R0603" value="4,7k" x="79.0956" y="33.0708" smashed="yes" rot="R90">
|
||||
<attribute name="NAME" x="78.359" y="31.9786" size="0.8128" layer="25" rot="R90"/>
|
||||
|
|
@ -2738,8 +2738,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<element name="R20" library="rcl" package="R0603" value="4,7k" x="77.8764" y="25.7556" smashed="yes" rot="R270">
|
||||
<attribute name="NAME" x="78.7146" y="26.8986" size="0.8128" layer="25" rot="R270"/>
|
||||
</element>
|
||||
<element name="R21" library="rcl" package="R0603" value="4,7k" x="64.1604" y="52.8828" smashed="yes">
|
||||
<attribute name="NAME" x="65.8114" y="52.2986" size="0.8128" layer="25"/>
|
||||
<element name="R21" library="rcl" package="R0603" value="4,7k" x="64.1604" y="55.0164" smashed="yes">
|
||||
<attribute name="NAME" x="65.8114" y="54.4322" size="0.8128" layer="25"/>
|
||||
</element>
|
||||
<element name="RN2" library="resistor-dil" package="EXBV8V" value="4,7k" x="79.248" y="71.628" smashed="yes" rot="R90">
|
||||
<attribute name="OC_NEWARK" value="unknown" x="79.248" y="71.628" size="1.778" layer="27" rot="R90" display="off"/>
|
||||
|
|
@ -2912,6 +2912,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<element name="R23" library="rcl" package="R0603" value="4,7k" x="73.7616" y="49.0728" smashed="yes">
|
||||
<attribute name="NAME" x="72.8218" y="50.0126" size="0.8128" layer="25"/>
|
||||
</element>
|
||||
<element name="R24" library="rcl" package="R0603" value="4,7k" x="64.1604" y="50.7492" smashed="yes">
|
||||
<attribute name="NAME" x="63.373" y="49.2506" size="0.8128" layer="25"/>
|
||||
</element>
|
||||
</elements>
|
||||
<signals>
|
||||
<signal name="D0">
|
||||
|
|
@ -5671,17 +5674,21 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<signal name="MMUDIS">
|
||||
<contactref element="IC1" pad="F13"/>
|
||||
<contactref element="R21" pad="1"/>
|
||||
<wire x1="59.7662" y1="52.8828" x2="63.3104" y2="52.8828" width="0.1524" layer="1"/>
|
||||
<wire x1="59.7662" y1="52.8828" x2="60.5028" y2="52.8828" width="0.1524" layer="1"/>
|
||||
<wire x1="60.5028" y1="52.8828" x2="62.6364" y2="55.0164" width="0.1524" layer="1"/>
|
||||
<wire x1="62.6364" y1="55.0164" x2="63.3104" y2="55.0164" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="CDIS">
|
||||
<contactref element="IC1" pad="H12"/>
|
||||
<contactref element="R12" pad="1"/>
|
||||
<wire x1="61.2648" y1="48.006" x2="61.2648" y2="49.8348" width="0.1524" layer="1"/>
|
||||
<wire x1="61.2648" y1="49.8348" x2="62.1792" y2="50.7492" width="0.1524" layer="1"/>
|
||||
<wire x1="62.1792" y1="50.7492" x2="63.3104" y2="50.7492" width="0.1524" layer="1"/>
|
||||
<wire x1="61.2648" y1="48.006" x2="61.2648" y2="51.9684" width="0.1524" layer="1"/>
|
||||
<wire x1="61.2648" y1="51.9684" x2="62.1792" y2="52.8828" width="0.1524" layer="1"/>
|
||||
<wire x1="62.1792" y1="52.8828" x2="63.3104" y2="52.8828" width="0.1524" layer="1"/>
|
||||
<wire x1="57.2262" y1="47.8028" x2="58.0898" y2="46.9392" width="0.1524" layer="1"/>
|
||||
<wire x1="58.0898" y1="46.9392" x2="60.198" y2="46.9392" width="0.1524" layer="1"/>
|
||||
<wire x1="60.198" y1="46.9392" x2="61.2648" y2="48.006" width="0.1524" layer="1"/>
|
||||
<contactref element="R24" pad="1"/>
|
||||
<wire x1="63.3104" y1="50.7492" x2="63.3104" y2="52.8828" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="STATUS">
|
||||
<contactref element="IC1" pad="J12"/>
|
||||
|
|
@ -6233,7 +6240,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<contactref element="R20" pad="2"/>
|
||||
<contactref element="R18" pad="1"/>
|
||||
<contactref element="R19" pad="1"/>
|
||||
<wire x1="65.0104" y1="50.7492" x2="65.0104" y2="52.8828" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0104" y1="52.8828" x2="65.0104" y2="55.0164" width="0.1524" layer="1"/>
|
||||
<wire x1="42.5082" y1="56.8706" x2="41.9862" y2="57.3926" width="0.6096" layer="1"/>
|
||||
<wire x1="41.9862" y1="57.3926" x2="41.9862" y2="60.5028" width="0.6096" layer="1"/>
|
||||
<contactref element="C8" pad="1"/>
|
||||
|
|
@ -6382,9 +6389,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="5.4864" y1="3.429" x2="5.4864" y2="1.7894" width="0.8128" layer="1"/>
|
||||
<wire x1="5.4864" y1="1.7894" x2="5.3734" y2="1.6764" width="0.8128" layer="1"/>
|
||||
<wire x1="10.9728" y1="37.214" x2="10.9728" y2="38.862" width="0.8128" layer="1"/>
|
||||
<wire x1="65.0104" y1="52.8828" x2="65.0104" y2="54.4712" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0104" y1="54.4712" x2="64.4652" y2="55.0164" width="0.1524" layer="1"/>
|
||||
<via x="64.4652" y="55.0164" extent="1-16" drill="0.3"/>
|
||||
<wire x1="65.0104" y1="55.0164" x2="65.0104" y2="54.4712" width="0.1524" layer="1"/>
|
||||
<via x="65.0748" y="57.7596" extent="1-16" drill="0.3"/>
|
||||
<wire x1="75.3872" y1="44.6532" x2="75.3986" y2="44.6646" width="0.4064" layer="1"/>
|
||||
<wire x1="75.3986" y1="44.6646" x2="75.3986" y2="46.609" width="0.4064" layer="1"/>
|
||||
<wire x1="75.3986" y1="46.609" x2="75.424" y2="46.6344" width="0.4064" layer="1"/>
|
||||
|
|
@ -6461,6 +6467,57 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="78.7908" y="28.194" extent="1-16" drill="0.3"/>
|
||||
<wire x1="72.9116" y1="49.0728" x2="72.2376" y2="49.7468" width="0.1524" layer="1"/>
|
||||
<wire x1="72.2376" y1="49.7468" x2="72.2376" y2="52.578" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0748" y1="57.7596" x2="65.0748" y2="55.0808" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0748" y1="55.0808" x2="65.0104" y2="55.0164" width="0.1524" layer="1"/>
|
||||
<wire x1="69.8246" y1="88.6596" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2328" y1="98.4504" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6354" y1="96.608" x2="57.1754" y2="98.4788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2896" y1="94.8172" x2="52.6034" y2="96.608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="86.5124" x2="44.1452" y2="93.726" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.323" y1="80.4418" x2="49.9872" y2="86.5124" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.4236" y1="75.272" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.133" y1="86.7664" x2="34.7256" y2="81.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="60.5028" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9062" y1="57.9628" x2="41.9862" y2="57.3926" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.5742" y1="53.3794" x2="42.5082" y2="56.8706" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="57.9628" x2="48.7172" y2="53.3908" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="52.8828" x2="52.1462" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="47.8028" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="53.34" y1="45.1104" x2="54.6862" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="42.7228" x2="52.1716" y2="44.7942" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.8262" y1="52.8828" x2="36.9062" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="47.8028" x2="31.8262" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3012" y1="45.2882" x2="34.3662" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="40.1828" x2="37.2872" y2="43.1038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.0104" y1="52.8828" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="68.7324" y1="49.2896" x2="65.0104" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.2376" y1="49.7468" x2="68.7324" y2="49.2896" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.424" y1="46.6344" x2="72.9116" y2="49.0728" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="79.8576" y1="36.7928" x2="75.4126" y2="44.6278" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.3872" y1="31.4084" x2="79.0956" y2="33.9208" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.7908" y1="28.868" x2="75.3872" y2="29.6164" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.8764" y1="24.9056" x2="78.7908" y2="28.194" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.724" y1="61.722" x2="71.9836" y2="54.4204" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="23.5712" x2="77.8764" y2="23.4696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="21.0312" x2="87.63" y2="23.5712" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="18.4912" x2="87.63" y2="21.0312" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.5976" y1="33.5788" x2="36.9062" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="35.2806" x2="31.5836" y2="33.5648" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="19.2786" x2="33.3134" y2="26.8986" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="34.3544" x2="24.7904" y2="35.2806" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="37.214" x2="15.3924" y2="34.3544" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="38.862" x2="10.9728" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="40.3606" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="6.5786" x2="33.3134" y2="16.7386" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.513" y1="32.4612" x2="52.1462" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="18.0086" x2="55.1434" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="12.5192" x2="61.4172" y2="17.4104" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.932" y1="5.0686" x2="65.5828" y2="12.5192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.0686" y1="53.9496" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="69.0372" x2="5.1816" y2="55.7022" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="4.9428" y1="84.582" x2="5.1816" y2="70.9422" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.334" y1="18.9738" x2="15.3924" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.4864" y1="3.429" x2="5.334" y2="16.1544" width="0" layer="19" extent="1-1"/>
|
||||
</signal>
|
||||
<signal name="GND">
|
||||
<contactref element="IC2" pad="16"/>
|
||||
|
|
@ -6594,8 +6651,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="44.2896" y1="77.4132" x2="44.8678" y2="76.835" width="0.3048" layer="1"/>
|
||||
<via x="62.992" y="58.0136" extent="1-16" drill="0.3"/>
|
||||
<via x="69.7484" y="58.42" extent="1-16" drill="0.3"/>
|
||||
<via x="62.8396" y="55.372" extent="1-16" drill="0.3"/>
|
||||
<via x="65.4304" y="55.3212" extent="1-16" drill="0.3"/>
|
||||
<wire x1="62.8396" y1="55.372" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="64.0588" y1="55.3212" x2="64.0588" y2="55.3212" width="0" layer="19" extent="1-16"/>
|
||||
<via x="60.7568" y="86.5124" extent="1-16" drill="0.3"/>
|
||||
<via x="46.5328" y="84.4804" extent="1-16" drill="0.3"/>
|
||||
<via x="72.6948" y="84.328" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6922,6 +6979,205 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="16.7894" y="42.0624" extent="1-16" drill="0.3"/>
|
||||
<wire x1="15.24" y1="42.037" x2="16.764" y2="42.037" width="0.1524" layer="1"/>
|
||||
<wire x1="16.764" y1="42.037" x2="16.7894" y2="42.0624" width="0.1524" layer="1"/>
|
||||
<contactref element="R24" pad="2"/>
|
||||
<wire x1="85.7504" y1="96.1644" x2="86.5124" y2="98.7552" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.7316" y1="93.8784" x2="85.7504" y2="96.1644" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.9988" y1="93.5736" x2="87.7316" y2="93.8784" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.473" y1="90.354" x2="81.5532" y2="95.7202" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.7428" y1="88.4428" x2="75.7428" y2="89.9668" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.8952" y1="68.707" x2="78.473" y2="68.5228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.5904" y1="67.2846" x2="75.8952" y2="68.707" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="74.3204" y1="94.3102" x2="76.13" y2="90.354" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.6948" y1="84.328" x2="75.7428" y2="88.4428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="73.2028" y1="61.4172" x2="75.5904" y2="67.2846" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="69.7484" y1="58.42" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.8688" y1="60.8076" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.0588" y1="55.3212" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.8396" y1="55.372" x2="64.0588" y2="55.3212" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="58.0136" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.5556" y1="56.9976" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.6224" y1="57.0484" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.6232" y1="48.8696" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="50.3428" x2="58.6232" y2="48.8696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1716" y1="47.6504" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="45.2628" x2="52.1716" y2="46.5442" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.8188" y1="47.3964" x2="52.1716" y2="47.6504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.1452" y1="48.768" x2="48.8188" y2="47.3964" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="55.4228" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.0512" y1="46.496" x2="44.1452" y2="48.768" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.592" y1="47.7012" x2="39.0144" y2="46.5328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="50.2412" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="50.3428" x2="36.9824" y2="50.2412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="52.8828" x2="34.3662" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="55.4228" x2="34.3662" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="55.4228" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.7068" y1="43.688" x2="39.0512" y2="45.2882" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="30.5816" y1="54.2036" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.194" y1="57.2516" x2="30.5816" y2="54.2036" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="45.2628" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="40.1828" x2="41.7068" y2="43.688" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="54.356" x2="28.194" y2="57.2516" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.876" y1="51.7652" x2="24.7904" y2="54.356" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7396" y1="49.276" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="46.6852" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="44.9072" x2="24.7904" y2="46.6852" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="42.0116" x2="20.9804" y2="44.9072" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="40.3606" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.7894" y1="42.0624" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="14.2748" y1="37.8968" x2="15.24" y2="42.037" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.21" y1="49.022" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="40.1828" x2="41.7068" y2="43.688" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.0662" y1="40.1828" x2="44.5262" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.0314" y1="38.3286" x2="47.0662" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="40.1828" x2="48.0314" y2="38.3286" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="34.414" x2="14.2748" y2="37.8968" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3416" y1="32.1056" x2="10.9728" y2="32.766" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="30.4038" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="32.1056" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.7612" y1="34.2392" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="31.496" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="28.9052" x2="24.7904" y2="31.496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="25.7302" y1="28.829" x2="24.7904" y2="28.9052" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.718" y1="31.3944" x2="25.7302" y2="28.829" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="37.6428" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.16" y1="41.2496" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.798" y1="30.1244" x2="29.8336" y2="31.51" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.0934" y1="30.1244" x2="34.8234" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3634" y1="28.4086" x2="36.0934" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.6334" y1="30.099" x2="37.3634" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.9034" y1="28.4086" x2="38.6334" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="24.3586" x2="34.8234" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="22.2504" x2="31.9278" y2="24.3586" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="60.5028" x2="36.9824" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="60.5028" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2976" y1="57.9628" x2="44.5262" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="57.9628" x2="44.2976" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.3616" y1="57.9628" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.766" y1="55.3212" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="60.5028" x2="48.3616" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.956" y1="16.3462" x2="31.623" y2="21.8186" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.608" y1="11.9888" x2="33.3134" y2="15.4686" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.4688" y1="14.1224" x2="38.6334" y2="11.9634" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="14.1224" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="14.1224" x2="43.688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.228" y1="14.1224" x2="44.958" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.1076" y1="14.1224" x2="46.228" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.418" y1="19.8628" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="19.9136" x2="42.418" y2="19.8628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="19.9136" x2="43.688" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.2788" y1="19.9136" x2="44.958" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.102" y1="12.6492" x2="48.1076" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="15.4686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.1952" y1="17.1704" x2="61.214" y2="15.4572" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="18.1864" x2="63.1952" y2="17.1704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="16.7132" x2="65.3288" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="19.9136" x2="63.8048" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.7672" y1="15.2908" x2="65.5828" y2="15.3192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.5216" y1="19.9644" x2="62.992" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="52.2732" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="53.594" x2="15.24" y2="52.197" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.8808" y1="67.5132" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="5.0686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.2356" y1="3.7592" x2="52.6034" y2="3.683" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="3.7592" x2="56.2356" y2="3.7592" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.4116" y1="90.5256" x2="74.3204" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.1604" y1="94.3102" x2="67.4116" y2="90.5256" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="61.6712" y1="97.3836" x2="64.1604" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="95.6564" x2="61.6712" y2="97.3836" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="51.7896" y1="92.8172" x2="57.1754" y2="95.6788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.7896" y1="94.8172" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="98.3488" x2="49.276" y2="96.2152" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.212" y1="97.1296" x2="47.4472" y2="98.3488" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="94.8172" x2="43.2896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7632" y1="94.6912" x2="37.7896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.6108" y1="97.6884" x2="37.7896" y2="96.4636" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.5788" y1="97.6884" x2="35.6108" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="96.1484" x2="33.5788" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="87.4776" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="48.6156" y1="84.7344" x2="50.6476" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.2896" y1="78.8172" x2="49.3324" y2="80.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.5328" y1="84.4804" x2="48.6156" y2="84.7344" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.5676" y1="86.9696" x2="46.5328" y2="84.4804" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.7736" y1="86.3346" x2="45.5676" y2="86.9696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.9768" y1="84.9884" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.4342" y1="86.4108" x2="51.7896" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.7568" y1="86.5124" x2="56.4388" y2="86.4108" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.8678" y1="76.835" x2="49.6824" y2="76.8096" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.338" y1="86.8172" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7896" y1="86.8172" x2="37.338" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.383" y1="86.7664" x2="34.4424" y2="86.5632" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="78.8172" x2="43.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.8762" y1="79.0956" x2="37.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.9314" y1="24.7142" x2="15.3924" y2="30.4038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="16.8656" x2="9.9314" y2="24.7142" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="13.8176" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="12.1412" x2="10.3124" y2="13.8176" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.1234" y1="17.2212" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="8.0264" x2="10.3124" y2="12.1412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="13.6652" y1="8.0264" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.7028" y1="4.826" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="8.2296" y1="1.6764" x2="9.7028" y2="4.826" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="2.7432" y1="0.9144" x2="7.1234" y2="1.6764" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.778" y1="0.9144" x2="2.7432" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="0.8636" y1="0.9144" x2="1.778" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.494" y1="16.5608" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.5448" y1="14.859" x2="15.494" y2="16.5608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="3.1496" x2="13.6652" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.2852" y1="2.3876" x2="19.9136" y2="3.1496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="26.4668" y1="5.9944" x2="21.2852" y2="2.3876" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.114" y1="95.0468" x2="31.1912" y2="94.8944" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="18.9992" y1="97.3328" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="17.018" y1="95.1992" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.256" y1="98.7044" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.4376" y1="88.5444" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="82.4484" x2="21.4376" y2="88.5444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="83.7692" x2="15.24" y2="82.3722" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3746" y1="84.9376" x2="15.1892" y2="83.7692" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.5692" y1="82.3976" x2="10.3746" y2="84.9376" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.8288" y1="83.3628" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.922" y1="77.3684" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="53.7578" x2="15.1892" y2="53.594" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="71.4248" y1="49.6824" x2="64.0588" y2="55.3212" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.5424" y1="46.6344" x2="71.4248" y2="49.6824" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.867" y1="46.482" x2="73.6486" y2="46.609" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.1906" y1="39.5224" x2="78.867" y2="46.482" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="80.1624" y1="34.5948" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.7956" y1="31.75" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.1888" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="32.3088" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="68.6816" x2="10.922" y2="77.3684" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="68.9978" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="68.9864" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.24" y1="67.1322" x2="15.1892" y2="68.9864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="30.2006" x2="7.0104" y2="37.6428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="29.8704" x2="48.0314" y2="38.3286" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="57.2516" y1="30.1752" x2="52.6034" y2="29.8704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.4332" y1="35.1536" x2="57.263" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.3476" y1="33.4772" x2="62.4332" y2="35.1536" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="31.1912" x2="63.6016" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.3412" y1="83.2104" x2="78.473" y2="83.3436" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="72.9996" x2="78.473" y2="72.828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="62.9412" x2="88.4936" y2="72.9996" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="62.7888" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="52.8828" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="42.672" x2="88.4936" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="22.2504" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="15.9512" x2="88.4936" y2="22.2504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="13.4112" x2="87.63" y2="15.9512" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="12.192" x2="87.63" y2="13.4112" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.694" y1="12.3444" x2="88.4936" y2="12.192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="2.3368" x2="91.694" y2="12.3444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="1.2192" x2="91.6432" y2="2.3368" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="90.2716" y1="1.2192" x2="91.6432" y2="1.2192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="97.9932" x2="1.8288" y2="83.3628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="98.9076" x2="1.016" y2="97.9932" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.0104" y1="50.7492" x2="65.0104" y2="48.0704" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0104" y1="48.0704" x2="66.1416" y2="46.9392" width="0.1524" layer="1"/>
|
||||
<wire x1="66.1416" y1="46.9392" x2="66.1416" y2="45.72" width="0.1524" layer="1"/>
|
||||
<via x="66.1416" y="45.72" extent="1-16" drill="0.3"/>
|
||||
<wire x1="66.1416" y1="45.72" x2="66.5988" y2="45.72" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="66.5988" y1="45.72" x2="66.7512" y2="45.8724" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="66.7512" y1="45.8724" x2="72.5424" y2="46.6344" width="0" layer="19" extent="1-16"/>
|
||||
</signal>
|
||||
<signal name="A27">
|
||||
<wire x1="82.55" y1="69.2912" x2="75.3872" y2="69.2912" width="0.1524" layer="16"/>
|
||||
|
|
@ -7993,11 +8249,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
</signals>
|
||||
<errors>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,a0a8a9f4a989a0d5"/>
|
||||
<approved hash="18,30,93e4923c922593fd"/>
|
||||
</errors>
|
||||
|
|
|
|||
|
|
@ -5700,7 +5700,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="39.9796" y1="31.0896" x2="39.9796" y2="33.4264" width="0.1524" layer="1"/>
|
||||
<wire x1="41.148" y1="37.0332" x2="41.148" y2="44.3484" width="0.1524" layer="1"/>
|
||||
<via x="41.148" y="49.4284" extent="1-16" drill="0.3"/>
|
||||
<wire x1="41.148" y1="44.3484" x2="40.8432" y2="45.7962" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="41.148" y1="44.3484" x2="41.148" y2="49.4284" width="0.1524" layer="1"/>
|
||||
<wire x1="41.148" y1="49.4284" x2="32.7406" y2="49.4284" width="0.1524" layer="16"/>
|
||||
<wire x1="77.0128" y1="47.3456" x2="65.3288" y2="47.3456" width="0.1524" layer="16"/>
|
||||
|
|
@ -5731,7 +5730,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="40.6908" y1="64.77" x2="40.6908" y2="66.294" width="0.1524" layer="1"/>
|
||||
<wire x1="40.6908" y1="66.294" x2="41.148" y2="66.7512" width="0.1524" layer="1"/>
|
||||
<wire x1="41.148" y1="66.7512" x2="41.148" y2="67.4624" width="0.1524" layer="1"/>
|
||||
<wire x1="40.8622" y1="45.7772" x2="40.8432" y2="45.7962" width="0" layer="19" extent="1-16"/>
|
||||
<contactref element="R23" pad="2"/>
|
||||
<wire x1="74.6116" y1="49.0728" x2="76.3388" y2="47.3456" width="0.1524" layer="1"/>
|
||||
<wire x1="76.3388" y1="47.3456" x2="76.962" y2="47.3456" width="0.1524" layer="1"/>
|
||||
|
|
@ -5754,7 +5752,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="37.846" y1="52.1716" x2="37.6428" y2="51.9684" width="0.1524" layer="16"/>
|
||||
<wire x1="37.6428" y1="51.9684" x2="30.2006" y2="51.9684" width="0.1524" layer="16"/>
|
||||
<wire x1="30.2006" y1="51.9684" x2="29.2862" y2="52.8828" width="0.1524" layer="16"/>
|
||||
<wire x1="43.1484" y1="47.3772" x2="42.2148" y2="48.3108" width="0" layer="19" extent="1-16"/>
|
||||
<contactref element="X1" pad="A9"/>
|
||||
<wire x1="86.2076" y1="32.3088" x2="87.63" y2="33.7312" width="0.1524" layer="16"/>
|
||||
<wire x1="39.2684" y1="30.6832" x2="39.2684" y2="27.5082" width="0.1524" layer="16"/>
|
||||
|
|
@ -5766,10 +5763,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="79.4004" y1="31.3944" x2="65.9892" y2="31.3944" width="0.1524" layer="16"/>
|
||||
<wire x1="65.9892" y1="31.3944" x2="65.3796" y2="32.004" width="0.1524" layer="16"/>
|
||||
<wire x1="65.3796" y1="32.004" x2="39.4716" y2="32.004" width="0.1524" layer="16"/>
|
||||
<wire x1="42.2148" y1="48.3108" x2="42.2148" y2="52.1208" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="42.2148" y1="52.1208" x2="42.2148" y2="52.1208" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="42.2148" y1="52.1208" x2="42.164" y2="52.1716" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="42.164" y1="52.1716" x2="40.5384" y2="52.1716" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="40.6908" y1="37.0332" x2="39.7764" y2="36.1188" width="0.1524" layer="1"/>
|
||||
<wire x1="39.7764" y1="36.1188" x2="39.0144" y2="36.1188" width="0.1524" layer="1"/>
|
||||
<wire x1="39.0144" y1="36.1188" x2="38.5572" y2="35.6616" width="0.1524" layer="1"/>
|
||||
|
|
@ -5926,7 +5919,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="40.9956" y1="66.1416" x2="41.4528" y2="66.5988" width="0.1524" layer="1"/>
|
||||
<wire x1="41.4528" y1="66.5988" x2="41.4528" y2="67.6656" width="0.1524" layer="1"/>
|
||||
<wire x1="41.4528" y1="67.6656" x2="40.7896" y2="68.3288" width="0.1524" layer="1"/>
|
||||
<wire x1="41.7576" y1="47.5488" x2="42.5768" y2="46.5772" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="37.6428" y1="46.1772" x2="39.0144" y2="47.5488" width="0.1524" layer="16"/>
|
||||
<wire x1="39.0144" y1="47.5488" x2="41.7576" y2="47.5488" width="0.1524" layer="16"/>
|
||||
<contactref element="R9" pad="2"/>
|
||||
|
|
@ -6469,55 +6461,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="78.7908" y="28.194" extent="1-16" drill="0.3"/>
|
||||
<wire x1="72.9116" y1="49.0728" x2="72.2376" y2="49.7468" width="0.1524" layer="1"/>
|
||||
<wire x1="72.2376" y1="49.7468" x2="72.2376" y2="52.578" width="0.1524" layer="1"/>
|
||||
<wire x1="69.8246" y1="88.6596" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2328" y1="98.4504" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6354" y1="96.608" x2="57.1754" y2="98.4788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2896" y1="94.8172" x2="52.6034" y2="96.608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="86.5124" x2="44.1452" y2="93.726" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.323" y1="80.4418" x2="49.9872" y2="86.5124" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.4236" y1="75.272" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.133" y1="86.7664" x2="34.7256" y2="81.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="60.5028" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9062" y1="57.9628" x2="41.9862" y2="57.3926" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.5742" y1="53.3794" x2="42.5082" y2="56.8706" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="57.9628" x2="48.7172" y2="53.3908" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="52.8828" x2="52.1462" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="47.8028" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="53.34" y1="45.1104" x2="54.6862" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="42.7228" x2="52.1716" y2="44.7942" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.8262" y1="52.8828" x2="36.9062" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="47.8028" x2="31.8262" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3012" y1="45.2882" x2="34.3662" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="40.1828" x2="37.2872" y2="43.1038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.4652" y1="55.0164" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="68.7324" y1="49.2896" x2="65.0104" y2="50.7492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.2376" y1="49.7468" x2="68.7324" y2="49.2896" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.424" y1="46.6344" x2="72.9116" y2="49.0728" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="79.8576" y1="36.7928" x2="75.4126" y2="44.6278" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.3872" y1="31.4084" x2="79.0956" y2="33.9208" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.7908" y1="28.868" x2="75.3872" y2="29.6164" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.8764" y1="24.9056" x2="78.7908" y2="28.194" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.724" y1="61.722" x2="71.9836" y2="54.4204" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="23.5712" x2="77.8764" y2="23.4696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="21.0312" x2="87.63" y2="23.5712" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="18.4912" x2="87.63" y2="21.0312" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.5976" y1="33.5788" x2="36.9062" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="35.2806" x2="31.5836" y2="33.5648" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="19.2786" x2="33.3134" y2="26.8986" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="34.3544" x2="24.7904" y2="35.2806" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="37.214" x2="15.3924" y2="34.3544" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="38.862" x2="10.9728" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="40.3606" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="6.5786" x2="33.3134" y2="16.7386" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.513" y1="32.4612" x2="52.1462" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="18.0086" x2="55.1434" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="12.5192" x2="61.4172" y2="17.4104" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.932" y1="5.0686" x2="65.5828" y2="12.5192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.0686" y1="53.9496" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="69.0372" x2="5.1816" y2="55.7022" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="4.9428" y1="84.582" x2="5.1816" y2="70.9422" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.334" y1="18.9738" x2="15.3924" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.4864" y1="3.429" x2="5.334" y2="16.1544" width="0" layer="19" extent="1-1"/>
|
||||
</signal>
|
||||
<signal name="GND">
|
||||
<contactref element="IC2" pad="16"/>
|
||||
|
|
@ -6979,197 +6922,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="16.7894" y="42.0624" extent="1-16" drill="0.3"/>
|
||||
<wire x1="15.24" y1="42.037" x2="16.764" y2="42.037" width="0.1524" layer="1"/>
|
||||
<wire x1="16.764" y1="42.037" x2="16.7894" y2="42.0624" width="0.1524" layer="1"/>
|
||||
<wire x1="85.7504" y1="96.1644" x2="86.5124" y2="98.7552" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.7316" y1="93.8784" x2="85.7504" y2="96.1644" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.9988" y1="93.5736" x2="87.7316" y2="93.8784" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.473" y1="90.354" x2="81.5532" y2="95.7202" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.7428" y1="88.4428" x2="75.7428" y2="89.9668" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.8952" y1="68.707" x2="78.473" y2="68.5228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.5904" y1="67.2846" x2="75.8952" y2="68.707" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="74.3204" y1="94.3102" x2="76.13" y2="90.354" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.6948" y1="84.328" x2="75.7428" y2="88.4428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="73.2028" y1="61.4172" x2="75.5904" y2="67.2846" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="69.7484" y1="58.42" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.8688" y1="60.8076" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.4304" y1="55.3212" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.8396" y1="55.372" x2="65.4304" y2="55.3212" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="58.0136" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.5556" y1="56.9976" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.6224" y1="57.0484" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.6232" y1="48.8696" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="50.3428" x2="58.6232" y2="48.8696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1716" y1="47.6504" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="45.2628" x2="52.1716" y2="46.5442" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.8188" y1="47.3964" x2="52.1716" y2="47.6504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.1452" y1="48.768" x2="48.8188" y2="47.3964" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="55.4228" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.0512" y1="46.496" x2="44.1452" y2="48.768" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.592" y1="47.7012" x2="39.0144" y2="46.5328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="50.2412" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="50.3428" x2="36.9824" y2="50.2412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="52.8828" x2="34.3662" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="55.4228" x2="34.3662" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="55.4228" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.7068" y1="43.688" x2="39.0512" y2="45.2882" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="30.5816" y1="54.2036" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.194" y1="57.2516" x2="30.5816" y2="54.2036" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="45.2628" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="40.1828" x2="41.7068" y2="43.688" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="54.356" x2="28.194" y2="57.2516" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.876" y1="51.7652" x2="24.7904" y2="54.356" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7396" y1="49.276" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="46.6852" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="44.9072" x2="24.7904" y2="46.6852" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="42.0116" x2="20.9804" y2="44.9072" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="40.3606" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.7894" y1="42.0624" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="14.2748" y1="37.8968" x2="15.24" y2="42.037" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.21" y1="49.022" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="40.1828" x2="41.7068" y2="43.688" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.0662" y1="40.1828" x2="44.5262" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.0314" y1="38.3286" x2="47.0662" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="40.1828" x2="48.0314" y2="38.3286" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="34.414" x2="14.2748" y2="37.8968" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3416" y1="32.1056" x2="10.9728" y2="32.766" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="30.4038" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="32.1056" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.7612" y1="34.2392" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="31.496" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="28.9052" x2="24.7904" y2="31.496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="25.7302" y1="28.829" x2="24.7904" y2="28.9052" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.718" y1="31.3944" x2="25.7302" y2="28.829" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="37.6428" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.16" y1="41.2496" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.798" y1="30.1244" x2="29.8336" y2="31.51" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.0934" y1="30.1244" x2="34.8234" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3634" y1="28.4086" x2="36.0934" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.6334" y1="30.099" x2="37.3634" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.9034" y1="28.4086" x2="38.6334" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="24.3586" x2="34.8234" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="22.2504" x2="31.9278" y2="24.3586" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="60.5028" x2="36.9824" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="60.5028" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2976" y1="57.9628" x2="44.5262" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="57.9628" x2="44.2976" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.3616" y1="57.9628" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.766" y1="55.3212" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="60.5028" x2="48.3616" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.956" y1="16.3462" x2="31.623" y2="21.8186" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.608" y1="11.9888" x2="33.3134" y2="15.4686" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.4688" y1="14.1224" x2="38.6334" y2="11.9634" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="14.1224" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="14.1224" x2="43.688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.228" y1="14.1224" x2="44.958" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.1076" y1="14.1224" x2="46.228" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.418" y1="19.8628" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="19.9136" x2="42.418" y2="19.8628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="19.9136" x2="43.688" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.2788" y1="19.9136" x2="44.958" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.102" y1="12.6492" x2="48.1076" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="15.4686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.1952" y1="17.1704" x2="61.214" y2="15.4572" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="18.1864" x2="63.1952" y2="17.1704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="16.7132" x2="65.3288" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="19.9136" x2="63.8048" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.7672" y1="15.2908" x2="65.5828" y2="15.3192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.5216" y1="19.9644" x2="62.992" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="52.2732" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="53.594" x2="15.24" y2="52.197" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.8808" y1="67.5132" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="5.0686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.2356" y1="3.7592" x2="52.6034" y2="3.683" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="3.7592" x2="56.2356" y2="3.7592" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.4116" y1="90.5256" x2="74.3204" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.1604" y1="94.3102" x2="67.4116" y2="90.5256" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="61.6712" y1="97.3836" x2="64.1604" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="95.6564" x2="61.6712" y2="97.3836" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="51.7896" y1="92.8172" x2="57.1754" y2="95.6788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.7896" y1="94.8172" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="98.3488" x2="49.276" y2="96.2152" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.212" y1="97.1296" x2="47.4472" y2="98.3488" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="94.8172" x2="43.2896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7632" y1="94.6912" x2="37.7896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.6108" y1="97.6884" x2="37.7896" y2="96.4636" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.5788" y1="97.6884" x2="35.6108" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="96.1484" x2="33.5788" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="87.4776" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="48.6156" y1="84.7344" x2="50.6476" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.2896" y1="78.8172" x2="49.3324" y2="80.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.5328" y1="84.4804" x2="48.6156" y2="84.7344" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.5676" y1="86.9696" x2="46.5328" y2="84.4804" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.7736" y1="86.3346" x2="45.5676" y2="86.9696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.9768" y1="84.9884" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.4342" y1="86.4108" x2="51.7896" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.7568" y1="86.5124" x2="56.4388" y2="86.4108" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.8678" y1="76.835" x2="49.6824" y2="76.8096" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.338" y1="86.8172" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7896" y1="86.8172" x2="37.338" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.383" y1="86.7664" x2="34.4424" y2="86.5632" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="78.8172" x2="43.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.8762" y1="79.0956" x2="37.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.9314" y1="24.7142" x2="15.3924" y2="30.4038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="16.8656" x2="9.9314" y2="24.7142" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="13.8176" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="12.1412" x2="10.3124" y2="13.8176" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.1234" y1="17.2212" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="8.0264" x2="10.3124" y2="12.1412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="13.6652" y1="8.0264" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.7028" y1="4.826" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="8.2296" y1="1.6764" x2="9.7028" y2="4.826" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="2.7432" y1="0.9144" x2="7.1234" y2="1.6764" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.778" y1="0.9144" x2="2.7432" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="0.8636" y1="0.9144" x2="1.778" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.494" y1="16.5608" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.5448" y1="14.859" x2="15.494" y2="16.5608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="3.1496" x2="13.6652" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.2852" y1="2.3876" x2="19.9136" y2="3.1496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="26.4668" y1="5.9944" x2="21.2852" y2="2.3876" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.114" y1="95.0468" x2="31.1912" y2="94.8944" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="18.9992" y1="97.3328" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="17.018" y1="95.1992" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.256" y1="98.7044" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.4376" y1="88.5444" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="82.4484" x2="21.4376" y2="88.5444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="83.7692" x2="15.24" y2="82.3722" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3746" y1="84.9376" x2="15.1892" y2="83.7692" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.5692" y1="82.3976" x2="10.3746" y2="84.9376" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.8288" y1="83.3628" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.922" y1="77.3684" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="53.7578" x2="15.1892" y2="53.594" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="71.4248" y1="49.6824" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.5424" y1="46.6344" x2="71.4248" y2="49.6824" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.867" y1="46.482" x2="73.6486" y2="46.609" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.1906" y1="39.5224" x2="78.867" y2="46.482" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="80.1624" y1="34.5948" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.7956" y1="31.75" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.1888" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="32.3088" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="68.6816" x2="10.922" y2="77.3684" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="68.9978" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="68.9864" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.24" y1="67.1322" x2="15.1892" y2="68.9864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="30.2006" x2="7.0104" y2="37.6428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="29.8704" x2="48.0314" y2="38.3286" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="57.2516" y1="30.1752" x2="52.6034" y2="29.8704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.4332" y1="35.1536" x2="57.263" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.3476" y1="33.4772" x2="62.4332" y2="35.1536" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="31.1912" x2="63.6016" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.3412" y1="83.2104" x2="78.473" y2="83.3436" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="72.9996" x2="78.473" y2="72.828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="62.9412" x2="88.4936" y2="72.9996" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="62.7888" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="52.8828" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="42.672" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="22.2504" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="15.9512" x2="88.4936" y2="22.2504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="13.4112" x2="87.63" y2="15.9512" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="12.192" x2="87.63" y2="13.4112" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.694" y1="12.3444" x2="88.4936" y2="12.192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="2.3368" x2="91.694" y2="12.3444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="1.2192" x2="91.6432" y2="2.3368" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="90.2716" y1="1.2192" x2="91.6432" y2="1.2192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="97.9932" x2="1.8288" y2="83.3628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="98.9076" x2="1.016" y2="97.9932" width="0" layer="19" extent="1-1"/>
|
||||
</signal>
|
||||
<signal name="A27">
|
||||
<wire x1="82.55" y1="69.2912" x2="75.3872" y2="69.2912" width="0.1524" layer="16"/>
|
||||
|
|
|
|||
|
|
@ -5404,12 +5404,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="37.9476" y="31.6992" extent="1-16" drill="0.3"/>
|
||||
<wire x1="40.386" y1="37.338" x2="40.386" y2="43.434" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="43.434" x2="39.9288" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<wire x1="39.9288" y1="43.8912" x2="39.9288" y2="46.482" width="0.1524" layer="1"/>
|
||||
<wire x1="39.9288" y1="46.482" x2="39.4716" y2="46.9392" width="0.1524" layer="1"/>
|
||||
<wire x1="39.4716" y1="46.9392" x2="39.4716" y2="53.0352" width="0.1524" layer="1"/>
|
||||
<via x="39.4716" y="53.0352" extent="1-16" drill="0.3"/>
|
||||
<wire x1="39.4716" y1="53.0352" x2="39.9288" y2="53.4924" width="0.1524" layer="16"/>
|
||||
<wire x1="39.9288" y1="53.4924" x2="47.3964" y2="53.4924" width="0.1524" layer="16"/>
|
||||
<wire x1="39.9288" y1="43.8912" x2="39.9288" y2="53.1876" width="0.1524" layer="1"/>
|
||||
<via x="39.9288" y="53.1876" extent="1-16" drill="0.3"/>
|
||||
<wire x1="39.9288" y1="53.1876" x2="40.2336" y2="53.4924" width="0.1524" layer="16"/>
|
||||
<wire x1="40.2336" y1="53.4924" x2="47.3964" y2="53.4924" width="0.1524" layer="16"/>
|
||||
<wire x1="47.3964" y1="53.4924" x2="48.006" y2="54.102" width="0.1524" layer="16"/>
|
||||
<wire x1="48.006" y1="54.102" x2="54.864" y2="54.102" width="0.1524" layer="16"/>
|
||||
<wire x1="60.6552" y1="60.198" x2="58.5216" y2="58.0644" width="0.1524" layer="1"/>
|
||||
|
|
@ -5566,7 +5564,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="44.958" y1="88.392" x2="68.58" y2="88.392" width="0.1524" layer="16"/>
|
||||
<wire x1="71.9328" y1="85.0392" x2="71.9328" y2="64.77" width="0.1524" layer="1"/>
|
||||
<wire x1="71.9328" y1="64.77" x2="80.772" y2="55.9308" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="55.9308" x2="80.772" y2="33.2232" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="55.9308" x2="80.772" y2="35.6616" width="0.1524" layer="1"/>
|
||||
<contactref element="R8" pad="2"/>
|
||||
<contactref element="X1" pad="A6"/>
|
||||
<wire x1="43.8912" y1="87.3252" x2="39.3192" y2="87.3252" width="0.1524" layer="16"/>
|
||||
|
|
@ -5575,11 +5573,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="39.3192" y1="94.7876" x2="39.2896" y2="94.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="39.3192" y1="87.3252" x2="39.3192" y2="82.296" width="0.1524" layer="1"/>
|
||||
<wire x1="39.3192" y1="82.296" x2="36.7284" y2="79.7052" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="33.2232" x2="81.534" y2="32.4612" width="0.1524" layer="1"/>
|
||||
<wire x1="81.534" y1="32.4612" x2="85.9536" y2="32.4612" width="0.1524" layer="1"/>
|
||||
<wire x1="85.9536" y1="32.4612" x2="86.4108" y2="32.004" width="0.1524" layer="1"/>
|
||||
<wire x1="86.4108" y1="32.004" x2="86.4108" y2="27.3304" width="0.1524" layer="1"/>
|
||||
<wire x1="86.4108" y1="27.3304" x2="87.63" y2="26.1112" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="35.6616" x2="81.534" y2="34.8996" width="0.1524" layer="1"/>
|
||||
<wire x1="81.534" y1="34.8996" x2="88.392" y2="34.8996" width="0.1524" layer="1"/>
|
||||
<wire x1="88.392" y1="34.8996" x2="88.8492" y2="34.4424" width="0.1524" layer="1"/>
|
||||
<wire x1="88.8492" y1="34.4424" x2="88.8492" y2="27.3304" width="0.1524" layer="1"/>
|
||||
<wire x1="88.8492" y1="27.3304" x2="87.63" y2="26.1112" width="0.1524" layer="1"/>
|
||||
<via x="35.814" y="40.8432" extent="1-16" drill="0.3"/>
|
||||
<wire x1="36.4236" y1="77.1144" x2="36.4236" y2="78.0288" width="0.1524" layer="1"/>
|
||||
<wire x1="36.4236" y1="78.0288" x2="36.7284" y2="78.3336" width="0.1524" layer="1"/>
|
||||
|
|
@ -5612,17 +5610,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="65.9892" y1="32.9184" x2="66.9036" y2="32.9184" width="0.1524" layer="16"/>
|
||||
<wire x1="66.9036" y1="32.9184" x2="68.1228" y2="31.6992" width="0.1524" layer="16"/>
|
||||
<wire x1="68.1228" y1="31.6992" x2="80.4672" y2="31.6992" width="0.1524" layer="16"/>
|
||||
<wire x1="86.4108" y1="33.3756" x2="86.4108" y2="34.29" width="0.1524" layer="16"/>
|
||||
<wire x1="86.4108" y1="34.29" x2="87.0204" y2="34.8996" width="0.1524" layer="16"/>
|
||||
<wire x1="87.0204" y1="34.8996" x2="88.392" y2="34.8996" width="0.1524" layer="16"/>
|
||||
<wire x1="88.392" y1="34.8996" x2="89.3064" y2="33.9852" width="0.1524" layer="16"/>
|
||||
<wire x1="89.3064" y1="33.9852" x2="89.3064" y2="31.5468" width="0.1524" layer="16"/>
|
||||
<wire x1="89.3064" y1="31.5468" x2="89.0016" y2="31.242" width="0.1524" layer="16"/>
|
||||
<wire x1="89.0016" y1="31.242" x2="87.6808" y2="31.242" width="0.1524" layer="16"/>
|
||||
<wire x1="87.6808" y1="31.242" x2="87.63" y2="31.1912" width="0.1524" layer="16"/>
|
||||
<wire x1="80.6196" y1="31.8516" x2="80.9244" y2="32.1564" width="0.1524" layer="16"/>
|
||||
<wire x1="80.9244" y1="32.1564" x2="85.1916" y2="32.1564" width="0.1524" layer="16"/>
|
||||
<wire x1="85.1916" y1="32.1564" x2="86.4108" y2="33.3756" width="0.1524" layer="16"/>
|
||||
<wire x1="79.0956" y1="32.2208" x2="80.2504" y2="32.2208" width="0.1524" layer="1"/>
|
||||
<wire x1="80.2504" y1="32.2208" x2="80.6196" y2="31.8516" width="0.1524" layer="1"/>
|
||||
<via x="80.6196" y="31.8516" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -5632,6 +5619,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="30.48" y1="38.4048" x2="30.48" y2="40.386" width="0.1524" layer="1"/>
|
||||
<wire x1="30.48" y1="40.386" x2="29.2862" y2="41.5798" width="0.1524" layer="1"/>
|
||||
<wire x1="29.2862" y1="41.5798" x2="29.2862" y2="42.7228" width="0.1524" layer="1"/>
|
||||
<wire x1="80.6196" y1="31.8516" x2="81.0768" y2="32.3088" width="0.1524" layer="1"/>
|
||||
<wire x1="81.0768" y1="32.3088" x2="86.5124" y2="32.3088" width="0.1524" layer="1"/>
|
||||
<wire x1="86.5124" y1="32.3088" x2="87.63" y2="31.1912" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="CBACK">
|
||||
<contactref element="IC1" pad="J01"/>
|
||||
|
|
@ -5708,24 +5698,23 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="41.1734" y1="29.8958" x2="39.9796" y2="31.0896" width="0.1524" layer="16"/>
|
||||
<via x="39.9796" y="31.0896" extent="1-16" drill="0.3"/>
|
||||
<wire x1="39.9796" y1="31.0896" x2="39.9796" y2="33.4264" width="0.1524" layer="1"/>
|
||||
<wire x1="40.9956" y1="36.8808" x2="40.9956" y2="44.196" width="0.1524" layer="1"/>
|
||||
<wire x1="40.9956" y1="44.196" x2="40.8432" y2="44.3484" width="0.1524" layer="1"/>
|
||||
<via x="40.8432" y="49.276" extent="1-16" drill="0.3"/>
|
||||
<wire x1="40.8432" y1="44.3484" x2="40.8432" y2="45.7962" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="40.8432" y1="44.3484" x2="40.8432" y2="49.276" width="0.1524" layer="1"/>
|
||||
<wire x1="40.8432" y1="49.276" x2="32.893" y2="49.276" width="0.1524" layer="16"/>
|
||||
<wire x1="41.148" y1="37.0332" x2="41.148" y2="44.3484" width="0.1524" layer="1"/>
|
||||
<via x="41.148" y="49.4284" extent="1-16" drill="0.3"/>
|
||||
<wire x1="41.148" y1="44.3484" x2="40.8432" y2="45.7962" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="41.148" y1="44.3484" x2="41.148" y2="49.4284" width="0.1524" layer="1"/>
|
||||
<wire x1="41.148" y1="49.4284" x2="32.7406" y2="49.4284" width="0.1524" layer="16"/>
|
||||
<wire x1="77.0128" y1="47.3456" x2="65.3288" y2="47.3456" width="0.1524" layer="16"/>
|
||||
<wire x1="60.198" y1="44.3484" x2="40.8432" y2="44.3484" width="0.1524" layer="16"/>
|
||||
<via x="40.8432" y="44.3484" extent="1-16" drill="0.3"/>
|
||||
<wire x1="40.8432" y1="49.276" x2="40.8432" y2="55.9308" width="0.1524" layer="1"/>
|
||||
<wire x1="40.8432" y1="55.9308" x2="40.386" y2="56.388" width="0.1524" layer="1"/>
|
||||
<wire x1="60.198" y1="44.3484" x2="41.148" y2="44.3484" width="0.1524" layer="16"/>
|
||||
<via x="41.148" y="44.3484" extent="1-16" drill="0.3"/>
|
||||
<wire x1="41.148" y1="49.4284" x2="41.148" y2="55.626" width="0.1524" layer="1"/>
|
||||
<wire x1="41.148" y1="55.626" x2="40.386" y2="56.388" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="56.388" x2="40.386" y2="61.4172" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="61.4172" x2="40.0812" y2="61.722" width="0.1524" layer="1"/>
|
||||
<wire x1="40.0812" y1="61.722" x2="40.0812" y2="62.484" width="0.1524" layer="1"/>
|
||||
<wire x1="40.0812" y1="62.484" x2="40.386" y2="62.7888" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="62.7888" x2="40.386" y2="64.4652" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="64.4652" x2="40.6908" y2="64.77" width="0.1524" layer="1"/>
|
||||
<wire x1="32.893" y1="49.276" x2="31.8262" y2="50.3428" width="0.1524" layer="16"/>
|
||||
<wire x1="32.7406" y1="49.4284" x2="31.8262" y2="50.3428" width="0.1524" layer="16"/>
|
||||
<contactref element="IC7" pad="81"/>
|
||||
<wire x1="40.2896" y1="78.8172" x2="40.2896" y2="68.3208" width="0.1524" layer="1"/>
|
||||
<wire x1="40.2896" y1="68.3208" x2="41.148" y2="67.4624" width="0.1524" layer="1"/>
|
||||
|
|
@ -5736,7 +5725,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="60.198" y1="44.3484" x2="60.5028" y2="44.6532" width="0.1524" layer="16"/>
|
||||
<wire x1="60.5028" y1="44.6532" x2="62.6364" y2="44.6532" width="0.1524" layer="16"/>
|
||||
<wire x1="62.6364" y1="44.6532" x2="65.3288" y2="47.3456" width="0.1524" layer="16"/>
|
||||
<wire x1="40.9956" y1="36.8808" x2="40.386" y2="36.2712" width="0.1524" layer="1"/>
|
||||
<wire x1="41.148" y1="37.0332" x2="40.386" y2="36.2712" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="36.2712" x2="40.386" y2="33.8328" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="33.8328" x2="39.9796" y2="33.4264" width="0.1524" layer="1"/>
|
||||
<wire x1="40.6908" y1="64.77" x2="40.6908" y2="66.294" width="0.1524" layer="1"/>
|
||||
|
|
@ -5757,13 +5746,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<contactref element="IC3" pad="31"/>
|
||||
<wire x1="39.9034" y1="5.0686" x2="39.9034" y2="26.8732" width="0.1524" layer="1"/>
|
||||
<via x="39.9034" y="26.8732" extent="1-16" drill="0.3"/>
|
||||
<wire x1="40.6908" y1="37.0332" x2="40.6908" y2="43.5864" width="0.1524" layer="1"/>
|
||||
<wire x1="40.6908" y1="43.5864" x2="40.2336" y2="44.0436" width="0.1524" layer="1"/>
|
||||
<wire x1="40.2336" y1="44.0436" x2="40.2336" y2="47.0916" width="0.1524" layer="1"/>
|
||||
<wire x1="40.2336" y1="47.0916" x2="40.0812" y2="47.244" width="0.1524" layer="1"/>
|
||||
<via x="40.0812" y="52.1716" extent="1-16" drill="0.3"/>
|
||||
<wire x1="40.0812" y1="47.244" x2="40.0812" y2="52.1716" width="0.1524" layer="1"/>
|
||||
<wire x1="40.0812" y1="52.1716" x2="37.846" y2="52.1716" width="0.1524" layer="16"/>
|
||||
<wire x1="40.6908" y1="37.0332" x2="40.6908" y2="43.7388" width="0.1524" layer="1"/>
|
||||
<wire x1="40.6908" y1="43.7388" x2="40.5384" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<via x="40.5384" y="52.1716" extent="1-16" drill="0.3"/>
|
||||
<wire x1="40.5384" y1="43.8912" x2="40.5384" y2="52.1716" width="0.1524" layer="1"/>
|
||||
<wire x1="40.5384" y1="52.1716" x2="37.846" y2="52.1716" width="0.1524" layer="16"/>
|
||||
<wire x1="37.846" y1="52.1716" x2="37.6428" y2="51.9684" width="0.1524" layer="16"/>
|
||||
<wire x1="37.6428" y1="51.9684" x2="30.2006" y2="51.9684" width="0.1524" layer="16"/>
|
||||
<wire x1="30.2006" y1="51.9684" x2="29.2862" y2="52.8828" width="0.1524" layer="16"/>
|
||||
|
|
@ -5782,7 +5769,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="42.2148" y1="48.3108" x2="42.2148" y2="52.1208" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="42.2148" y1="52.1208" x2="42.2148" y2="52.1208" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="42.2148" y1="52.1208" x2="42.164" y2="52.1716" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="42.164" y1="52.1716" x2="40.0812" y2="52.1716" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="42.164" y1="52.1716" x2="40.5384" y2="52.1716" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="40.6908" y1="37.0332" x2="39.7764" y2="36.1188" width="0.1524" layer="1"/>
|
||||
<wire x1="39.7764" y1="36.1188" x2="39.0144" y2="36.1188" width="0.1524" layer="1"/>
|
||||
<wire x1="39.0144" y1="36.1188" x2="38.5572" y2="35.6616" width="0.1524" layer="1"/>
|
||||
|
|
@ -5912,15 +5899,15 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="30.9372" y1="42.3672" x2="32.766" y2="40.5384" width="0.1524" layer="1"/>
|
||||
<wire x1="32.766" y1="40.5384" x2="32.766" y2="29.4132" width="0.1524" layer="1"/>
|
||||
<wire x1="32.766" y1="29.4132" x2="32.4612" y2="29.1084" width="0.1524" layer="1"/>
|
||||
<via x="41.6052" y="47.5488" extent="1-16" drill="0.3"/>
|
||||
<via x="41.7576" y="47.5488" extent="1-16" drill="0.3"/>
|
||||
<wire x1="82.55" y1="64.2112" x2="73.8632" y2="64.2112" width="0.1524" layer="16"/>
|
||||
<wire x1="73.8632" y1="64.2112" x2="71.374" y2="61.722" width="0.1524" layer="16"/>
|
||||
<wire x1="71.374" y1="61.722" x2="40.9956" y2="61.722" width="0.1524" layer="16"/>
|
||||
<wire x1="40.9956" y1="61.722" x2="40.6908" y2="62.0268" width="0.1524" layer="16"/>
|
||||
<via x="40.6908" y="62.0268" extent="1-16" drill="0.3"/>
|
||||
<wire x1="40.6908" y1="62.0268" x2="40.6908" y2="56.5404" width="0.1524" layer="1"/>
|
||||
<wire x1="40.6908" y1="56.5404" x2="41.6052" y2="55.626" width="0.1524" layer="1"/>
|
||||
<wire x1="41.6052" y1="55.626" x2="41.6052" y2="47.5488" width="0.1524" layer="1"/>
|
||||
<wire x1="40.6908" y1="56.5404" x2="41.7576" y2="55.4736" width="0.1524" layer="1"/>
|
||||
<wire x1="41.7576" y1="55.4736" x2="41.7576" y2="47.5488" width="0.1524" layer="1"/>
|
||||
<wire x1="40.6908" y1="62.0268" x2="40.6908" y2="63.7032" width="0.1524" layer="1"/>
|
||||
<contactref element="IC7" pad="82"/>
|
||||
<wire x1="40.7896" y1="78.8172" x2="40.7896" y2="68.3288" width="0.1524" layer="1"/>
|
||||
|
|
@ -5939,9 +5926,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="40.9956" y1="66.1416" x2="41.4528" y2="66.5988" width="0.1524" layer="1"/>
|
||||
<wire x1="41.4528" y1="66.5988" x2="41.4528" y2="67.6656" width="0.1524" layer="1"/>
|
||||
<wire x1="41.4528" y1="67.6656" x2="40.7896" y2="68.3288" width="0.1524" layer="1"/>
|
||||
<wire x1="41.6052" y1="47.5488" x2="42.5768" y2="46.5772" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="41.7576" y1="47.5488" x2="42.5768" y2="46.5772" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="37.6428" y1="46.1772" x2="39.0144" y2="47.5488" width="0.1524" layer="16"/>
|
||||
<wire x1="39.0144" y1="47.5488" x2="41.6052" y2="47.5488" width="0.1524" layer="16"/>
|
||||
<wire x1="39.0144" y1="47.5488" x2="41.7576" y2="47.5488" width="0.1524" layer="16"/>
|
||||
<contactref element="R9" pad="2"/>
|
||||
<wire x1="80.4028" y1="64.6176" x2="80.8092" y2="64.2112" width="0.1524" layer="1"/>
|
||||
<wire x1="80.8092" y1="64.2112" x2="82.55" y2="64.2112" width="0.1524" layer="1"/>
|
||||
|
|
@ -5953,7 +5940,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="33.0708" y1="41.4782" x2="31.8262" y2="42.7228" width="0.1524" layer="1"/>
|
||||
<wire x1="32.9184" y1="43.7388" x2="39.2176" y2="43.7388" width="0.1524" layer="16"/>
|
||||
<wire x1="39.2176" y1="43.7388" x2="40.4368" y2="44.958" width="0.1524" layer="16"/>
|
||||
<wire x1="40.4368" y1="44.958" x2="43.5864" y2="44.958" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="40.4368" y1="44.958" x2="47.7012" y2="44.958" width="0.1524" layer="16"/>
|
||||
<wire x1="47.7012" y1="44.958" x2="51.9684" y2="44.958" width="0.1524" layer="16"/>
|
||||
<wire x1="51.9684" y1="44.958" x2="53.1876" y2="46.1772" width="0.1524" layer="16"/>
|
||||
|
|
@ -5968,8 +5954,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<contactref element="IC7" pad="98"/>
|
||||
<wire x1="50.7492" y1="74.422" x2="48.7896" y2="76.3816" width="0.1524" layer="1"/>
|
||||
<wire x1="48.7896" y1="76.3816" x2="48.7896" y2="78.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="43.6056" y1="44.9772" x2="43.5864" y2="44.958" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="43.5864" y1="44.958" x2="43.5864" y2="44.958" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="28.1178" y1="27.9146" x2="28.3972" y2="28.194" width="0.1524" layer="1"/>
|
||||
<via x="28.3972" y="28.194" extent="1-16" drill="0.3"/>
|
||||
<via x="32.6136" y="28.194" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -5983,8 +5967,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="81.3816" y1="37.7952" x2="81.6864" y2="37.4904" width="0.1524" layer="1"/>
|
||||
<wire x1="81.6864" y1="37.4904" x2="86.4108" y2="37.4904" width="0.1524" layer="1"/>
|
||||
<wire x1="86.4108" y1="37.4904" x2="87.63" y2="36.2712" width="0.1524" layer="1"/>
|
||||
<wire x1="81.3816" y1="60.198" x2="81.6864" y2="60.5028" width="0.1524" layer="1"/>
|
||||
<wire x1="81.6864" y1="60.5028" x2="86.4616" y2="60.5028" width="0.1524" layer="1"/>
|
||||
<wire x1="86.4616" y1="60.5028" x2="87.63" y2="61.6712" width="0.1524" layer="1"/>
|
||||
<wire x1="28.1178" y1="15.0114" x2="28.9306" y2="14.1986" width="0.1524" layer="1"/>
|
||||
<wire x1="50.7492" y1="60.198" x2="49.9872" y2="59.436" width="0.1524" layer="1"/>
|
||||
|
|
@ -5995,8 +5977,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="47.7012" y1="51.816" x2="47.7012" y2="44.958" width="0.1524" layer="1"/>
|
||||
<via x="47.7012" y="44.958" extent="1-16" drill="0.3"/>
|
||||
<contactref element="R3" pad="2"/>
|
||||
<wire x1="81.6864" y1="60.5028" x2="81.6864" y2="60.4384" width="0.1524" layer="1"/>
|
||||
<wire x1="81.6864" y1="60.4384" x2="80.4028" y2="61.722" width="0.1524" layer="1"/>
|
||||
<wire x1="81.3816" y1="60.198" x2="81.6864" y2="60.5028" width="0.1524" layer="1"/>
|
||||
<wire x1="81.6864" y1="60.5028" x2="81.6864" y2="60.96" width="0.1524" layer="1"/>
|
||||
<wire x1="81.6864" y1="60.96" x2="80.9244" y2="61.722" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="61.722" x2="80.4028" y2="61.722" width="0.1524" layer="1"/>
|
||||
<wire x1="81.6864" y1="60.5028" x2="86.4616" y2="60.5028" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="DBEN">
|
||||
<contactref element="IC1" pad="M01"/>
|
||||
|
|
@ -6283,9 +6268,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="75.4126" y1="44.6278" x2="75.3872" y2="44.6532" width="0.6096" layer="1"/>
|
||||
<wire x1="35.7896" y1="81.8172" x2="35.8112" y2="81.8388" width="0.1524" layer="1"/>
|
||||
<wire x1="37.3012" y1="45.2882" x2="37.3012" y2="44.1084" width="0.6096" layer="1"/>
|
||||
<wire x1="37.3012" y1="44.1084" x2="37.1348" y2="43.942" width="0.6096" layer="1"/>
|
||||
<wire x1="37.1348" y1="43.942" x2="37.1348" y2="42.9514" width="0.6096" layer="1"/>
|
||||
<wire x1="37.1348" y1="42.9514" x2="36.9062" y2="42.7228" width="0.6096" layer="1"/>
|
||||
<wire x1="37.3012" y1="44.1084" x2="37.2872" y2="44.0944" width="0.6096" layer="1"/>
|
||||
<wire x1="37.2872" y1="44.0944" x2="37.2872" y2="43.1038" width="0.6096" layer="1"/>
|
||||
<wire x1="37.2872" y1="43.1038" x2="36.9062" y2="42.7228" width="0.6096" layer="1"/>
|
||||
<contactref element="C10" pad="1"/>
|
||||
<contactref element="C11" pad="1"/>
|
||||
<wire x1="33.133" y1="86.7664" x2="33.6838" y2="87.3172" width="0.3048" layer="1"/>
|
||||
|
|
@ -6503,7 +6488,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="31.8262" y1="52.8828" x2="36.9062" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="47.8028" x2="31.8262" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3012" y1="45.2882" x2="34.3662" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="40.1828" x2="37.1348" y2="42.9514" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="40.1828" x2="37.2872" y2="43.1038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.4652" y1="55.0164" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="68.7324" y1="49.2896" x2="65.0104" y2="50.7492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.2376" y1="49.7468" x2="68.7324" y2="49.2896" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -6887,7 +6872,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="88.4936" y="62.9412" extent="1-16" drill="0.3"/>
|
||||
<via x="88.4936" y="52.8828" extent="1-16" drill="0.3"/>
|
||||
<via x="88.4936" y="42.672" extent="1-16" drill="0.3"/>
|
||||
<via x="88.4936" y="32.4612" extent="1-16" drill="0.3"/>
|
||||
<via x="88.1888" y="32.4612" extent="1-16" drill="0.3"/>
|
||||
<via x="88.4936" y="22.2504" extent="1-16" drill="0.3"/>
|
||||
<via x="88.4936" y="12.192" extent="1-16" drill="0.3"/>
|
||||
<via x="71.4248" y="49.6824" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -7157,8 +7142,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="77.1906" y1="39.5224" x2="78.867" y2="46.482" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="80.1624" y1="34.5948" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.7956" y1="31.75" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="32.3088" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.1888" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="32.3088" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="68.6816" x2="10.922" y2="77.3684" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="68.9978" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="68.9864" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7174,8 +7159,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="88.4936" y1="62.9412" x2="88.4936" y2="72.9996" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="62.7888" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="52.8828" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="42.672" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="22.2504" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="42.672" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="22.2504" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="15.9512" x2="88.4936" y2="22.2504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="13.4112" x2="87.63" y2="15.9512" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="12.192" x2="87.63" y2="13.4112" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7498,7 +7483,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="22.5552" y1="43.5864" x2="22.5552" y2="37.4904" width="0.1524" layer="1"/>
|
||||
<wire x1="22.5552" y1="37.4904" x2="23.1648" y2="36.8808" width="0.1524" layer="1"/>
|
||||
<contactref element="IC7" pad="80"/>
|
||||
<wire x1="38.5572" y1="52.578" x2="38.5572" y2="66.294" width="0.1524" layer="1"/>
|
||||
<wire x1="38.5572" y1="57.6072" x2="38.5572" y2="66.294" width="0.1524" layer="1"/>
|
||||
<wire x1="39.7896" y1="78.8172" x2="39.7896" y2="67.5264" width="0.1524" layer="1"/>
|
||||
<wire x1="39.7896" y1="67.5264" x2="38.5572" y2="66.294" width="0.1524" layer="1"/>
|
||||
<wire x1="22.5552" y1="43.5864" x2="23.1648" y2="44.196" width="0.1524" layer="16"/>
|
||||
|
|
@ -7506,12 +7491,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="25.908" y1="44.196" x2="28.6512" y2="46.9392" width="0.1524" layer="16"/>
|
||||
<wire x1="28.6512" y1="46.9392" x2="29.718" y2="46.9392" width="0.1524" layer="16"/>
|
||||
<wire x1="29.718" y1="46.9392" x2="31.5468" y2="48.768" width="0.1524" layer="16"/>
|
||||
<wire x1="31.5468" y1="48.768" x2="37.4904" y2="48.768" width="0.1524" layer="16"/>
|
||||
<wire x1="37.4904" y1="48.768" x2="37.7952" y2="48.4632" width="0.1524" layer="16"/>
|
||||
<wire x1="37.7952" y1="48.4632" x2="38.862" y2="48.4632" width="0.1524" layer="16"/>
|
||||
<via x="38.862" y="48.4632" extent="1-16" drill="0.3"/>
|
||||
<wire x1="38.862" y1="48.4632" x2="38.862" y2="52.2732" width="0.1524" layer="1"/>
|
||||
<wire x1="38.862" y1="52.2732" x2="38.5572" y2="52.578" width="0.1524" layer="1"/>
|
||||
<wire x1="31.5468" y1="48.768" x2="38.862" y2="48.768" width="0.1524" layer="16"/>
|
||||
<via x="38.862" y="48.768" extent="1-16" drill="0.3"/>
|
||||
<wire x1="38.862" y1="48.768" x2="38.862" y2="57.3024" width="0.1524" layer="1"/>
|
||||
<wire x1="38.862" y1="57.3024" x2="38.5572" y2="57.6072" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="AMIGA_A1">
|
||||
<contactref element="IC2" pad="29"/>
|
||||
|
|
@ -8258,12 +8241,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
</signals>
|
||||
<errors>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,3849587e8adf1064"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,a0a8a9f4a989a0d5"/>
|
||||
<approved hash="18,30,93e4923c922593fd"/>
|
||||
</errors>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2952,7 +2952,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="43.7388" y1="34.5948" x2="43.688" y2="34.6456" width="0.1524" layer="1"/>
|
||||
<wire x1="43.688" y1="34.6456" x2="43.688" y2="35.4584" width="0.1524" layer="1"/>
|
||||
<wire x1="43.688" y1="35.4584" x2="45.8724" y2="37.6428" width="0.1524" layer="1"/>
|
||||
<wire x1="45.8724" y1="37.6428" x2="45.8724" y2="40.5384" width="0.1524" layer="1"/>
|
||||
<wire x1="45.8724" y1="37.6428" x2="45.8724" y2="40.8432" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="C16"/>
|
||||
<wire x1="62.5348" y1="49.5808" x2="69.5452" y2="49.5808" width="0.1524" layer="16"/>
|
||||
<wire x1="69.5452" y1="49.5808" x2="71.4756" y2="51.5112" width="0.1524" layer="16"/>
|
||||
|
|
@ -2962,10 +2962,12 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="56.5404" y1="44.196" x2="57.15" y2="43.5864" width="0.1524" layer="1"/>
|
||||
<wire x1="57.15" y1="43.5864" x2="57.15" y2="42.799" width="0.1524" layer="1"/>
|
||||
<wire x1="57.15" y1="42.799" x2="57.2262" y2="42.7228" width="0.1524" layer="1"/>
|
||||
<wire x1="45.8724" y1="40.5384" x2="48.006" y2="42.672" width="0.1524" layer="1"/>
|
||||
<wire x1="48.006" y1="42.672" x2="50.9016" y2="42.672" width="0.1524" layer="1"/>
|
||||
<wire x1="50.9016" y1="42.672" x2="52.1208" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<wire x1="52.1208" y1="43.8912" x2="53.1876" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<wire x1="45.8724" y1="40.8432" x2="46.1772" y2="41.148" width="0.1524" layer="1"/>
|
||||
<wire x1="46.1772" y1="41.148" x2="48.4632" y2="41.148" width="0.1524" layer="1"/>
|
||||
<wire x1="48.4632" y1="41.148" x2="49.9872" y2="42.672" width="0.1524" layer="1"/>
|
||||
<wire x1="49.9872" y1="42.672" x2="50.9016" y2="42.672" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="D2">
|
||||
<contactref element="IC1" pad="L13"/>
|
||||
|
|
@ -5081,7 +5083,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="50.4952" y1="83.82" x2="45.2882" y2="83.82" width="0.3048" layer="16"/>
|
||||
<via x="45.2882" y="83.82" extent="1-16" drill="0.3"/>
|
||||
<wire x1="45.2896" y1="83.8186" x2="45.2882" y2="83.82" width="0.1524" layer="1"/>
|
||||
<wire x1="38.862" y1="41.3004" x2="57.4548" y2="41.3004" width="0.4064" layer="16"/>
|
||||
<wire x1="38.862" y1="41.3004" x2="46.7868" y2="41.3004" width="0.4064" layer="16"/>
|
||||
<wire x1="38.862" y1="41.3004" x2="38.2524" y2="40.6908" width="0.4064" layer="16"/>
|
||||
<wire x1="38.2524" y1="40.6908" x2="38.2524" y2="39.1668" width="0.4064" layer="16"/>
|
||||
<wire x1="38.2524" y1="39.1668" x2="37.9476" y2="38.862" width="0.4064" layer="16"/>
|
||||
|
|
@ -5090,20 +5092,16 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="26.3906" y1="37.8206" x2="24.7904" y2="37.8206" width="0.4064" layer="16"/>
|
||||
<wire x1="64.4652" y1="58.9788" x2="64.4652" y2="58.2168" width="0.4064" layer="1"/>
|
||||
<wire x1="64.4652" y1="58.2168" x2="60.3504" y2="54.102" width="0.4064" layer="1"/>
|
||||
<wire x1="60.3504" y1="54.102" x2="59.5884" y2="54.102" width="0.4064" layer="1"/>
|
||||
<wire x1="59.5884" y1="54.102" x2="58.5216" y2="53.0352" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="53.0352" x2="58.5216" y2="50.1396" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="50.1396" x2="57.4548" y2="49.0728" width="0.4064" layer="1"/>
|
||||
<wire x1="57.4548" y1="49.0728" x2="56.8452" y2="49.0728" width="0.4064" layer="1"/>
|
||||
<wire x1="56.8452" y1="49.0728" x2="55.9308" y2="48.1584" width="0.4064" layer="1"/>
|
||||
<wire x1="55.9308" y1="48.1584" x2="55.9308" y2="47.244" width="0.4064" layer="1"/>
|
||||
<wire x1="55.9308" y1="47.244" x2="56.5404" y2="46.6344" width="0.4064" layer="1"/>
|
||||
<wire x1="56.5404" y1="46.6344" x2="57.7596" y2="46.6344" width="0.4064" layer="1"/>
|
||||
<wire x1="57.7596" y1="46.6344" x2="58.5216" y2="45.8724" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="45.8724" x2="58.5216" y2="42.3672" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="42.3672" x2="58.2168" y2="42.0624" width="0.4064" layer="1"/>
|
||||
<wire x1="57.4548" y1="41.3004" x2="58.2168" y2="42.0624" width="0.4064" layer="16"/>
|
||||
<via x="58.2168" y="42.0624" extent="1-16" drill="0.3"/>
|
||||
<wire x1="60.3504" y1="54.102" x2="59.1312" y2="54.102" width="0.4064" layer="1"/>
|
||||
<wire x1="59.1312" y1="54.102" x2="58.5216" y2="53.4924" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="53.4924" x2="58.5216" y2="49.9872" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="49.9872" x2="57.6072" y2="49.0728" width="0.4064" layer="1"/>
|
||||
<wire x1="46.7868" y1="41.3004" x2="47.5488" y2="42.0624" width="0.4064" layer="16"/>
|
||||
<via x="47.5488" y="42.0624" extent="1-16" drill="0.3"/>
|
||||
<wire x1="47.5488" y1="42.0624" x2="50.7492" y2="45.2628" width="0.4064" layer="1"/>
|
||||
<wire x1="50.7492" y1="45.2628" x2="50.7492" y2="48.3108" width="0.4064" layer="1"/>
|
||||
<wire x1="50.7492" y1="48.3108" x2="51.5112" y2="49.0728" width="0.4064" layer="1"/>
|
||||
<wire x1="51.5112" y1="49.0728" x2="57.6072" y2="49.0728" width="0.4064" layer="1"/>
|
||||
</signal>
|
||||
<signal name="BERR">
|
||||
<contactref element="IC2" pad="22"/>
|
||||
|
|
@ -5374,11 +5372,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="71.1708" y1="54.864" x2="69.342" y2="53.0352" width="0.1524" layer="16"/>
|
||||
<wire x1="69.342" y1="53.0352" x2="62.6364" y2="53.0352" width="0.1524" layer="16"/>
|
||||
<wire x1="62.6364" y1="53.0352" x2="61.8744" y2="53.7972" width="0.1524" layer="16"/>
|
||||
<wire x1="59.2836" y1="53.7972" x2="58.3692" y2="52.8828" width="0.1524" layer="16"/>
|
||||
<wire x1="58.3692" y1="52.8828" x2="57.2262" y2="52.8828" width="0.1524" layer="16"/>
|
||||
<wire x1="58.8264" y1="53.7972" x2="57.912" y2="52.8828" width="0.1524" layer="16"/>
|
||||
<wire x1="57.912" y1="52.8828" x2="57.2262" y2="52.8828" width="0.1524" layer="16"/>
|
||||
<wire x1="33.3134" y1="23.0886" x2="34.671" y2="23.0886" width="0.1524" layer="1"/>
|
||||
<wire x1="60.6552" y1="81.4832" x2="60.6552" y2="59.8932" width="0.1524" layer="1"/>
|
||||
<wire x1="61.8744" y1="53.7972" x2="59.2836" y2="53.7972" width="0.1524" layer="16"/>
|
||||
<wire x1="60.6552" y1="81.4832" x2="60.6552" y2="60.198" width="0.1524" layer="1"/>
|
||||
<wire x1="61.8744" y1="53.7972" x2="58.8264" y2="53.7972" width="0.1524" layer="16"/>
|
||||
<contactref element="IC7" pad="3"/>
|
||||
<wire x1="51.7896" y1="81.8172" x2="57.6364" y2="81.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="57.6364" y1="81.8172" x2="57.8104" y2="81.9912" width="0.1524" layer="1"/>
|
||||
|
|
@ -5405,12 +5403,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="39.4716" y1="53.0352" x2="39.9288" y2="53.4924" width="0.1524" layer="16"/>
|
||||
<wire x1="39.9288" y1="53.4924" x2="47.3964" y2="53.4924" width="0.1524" layer="16"/>
|
||||
<wire x1="47.3964" y1="53.4924" x2="48.006" y2="54.102" width="0.1524" layer="16"/>
|
||||
<wire x1="48.006" y1="54.102" x2="56.007" y2="54.102" width="0.1524" layer="16"/>
|
||||
<wire x1="56.007" y1="54.102" x2="57.2262" y2="52.8828" width="0.1524" layer="16"/>
|
||||
<wire x1="60.6552" y1="59.8932" x2="59.8932" y2="59.1312" width="0.1524" layer="1"/>
|
||||
<wire x1="59.8932" y1="59.1312" x2="58.9788" y2="59.1312" width="0.1524" layer="1"/>
|
||||
<wire x1="58.9788" y1="59.1312" x2="58.5216" y2="58.674" width="0.1524" layer="1"/>
|
||||
<wire x1="58.5216" y1="58.674" x2="58.5216" y2="55.3212" width="0.1524" layer="1"/>
|
||||
<wire x1="48.006" y1="54.102" x2="54.864" y2="54.102" width="0.1524" layer="16"/>
|
||||
<wire x1="60.6552" y1="60.198" x2="58.5216" y2="58.0644" width="0.1524" layer="1"/>
|
||||
<wire x1="58.5216" y1="58.0644" x2="58.5216" y2="55.3212" width="0.1524" layer="1"/>
|
||||
<wire x1="58.5216" y1="55.3212" x2="57.2262" y2="54.0258" width="0.1524" layer="1"/>
|
||||
<wire x1="57.2262" y1="54.0258" x2="57.2262" y2="52.8828" width="0.1524" layer="1"/>
|
||||
<wire x1="40.386" y1="37.338" x2="39.4716" y2="36.4236" width="0.1524" layer="1"/>
|
||||
|
|
@ -5419,6 +5414,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="38.1" y1="35.814" x2="38.1" y2="34.29" width="0.1524" layer="1"/>
|
||||
<wire x1="38.1" y1="34.29" x2="37.9476" y2="34.1376" width="0.1524" layer="1"/>
|
||||
<wire x1="37.9476" y1="34.1376" x2="37.9476" y2="31.6992" width="0.1524" layer="1"/>
|
||||
<wire x1="54.864" y1="54.102" x2="56.0832" y2="52.8828" width="0.1524" layer="16"/>
|
||||
<wire x1="56.0832" y1="52.8828" x2="57.2262" y2="52.8828" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="BG_30">
|
||||
<contactref element="R19" pad="2"/>
|
||||
|
|
@ -5441,11 +5438,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="32.6136" y1="53.9496" x2="32.766" y2="53.7972" width="0.1524" layer="16"/>
|
||||
<wire x1="32.766" y1="53.7972" x2="47.244" y2="53.7972" width="0.1524" layer="16"/>
|
||||
<wire x1="47.244" y1="53.7972" x2="47.8536" y2="54.4068" width="0.1524" layer="16"/>
|
||||
<wire x1="47.8536" y1="54.4068" x2="57.7596" y2="54.4068" width="0.1524" layer="16"/>
|
||||
<wire x1="57.7596" y1="54.4068" x2="58.2168" y2="54.864" width="0.1524" layer="16"/>
|
||||
<wire x1="58.2168" y1="54.864" x2="58.8264" y2="54.864" width="0.1524" layer="16"/>
|
||||
<wire x1="58.8264" y1="54.864" x2="59.1312" y2="54.5592" width="0.1524" layer="16"/>
|
||||
<wire x1="59.1312" y1="54.5592" x2="60.3504" y2="54.5592" width="0.1524" layer="16"/>
|
||||
<wire x1="47.8536" y1="54.4068" x2="55.4736" y2="54.4068" width="0.1524" layer="16"/>
|
||||
<wire x1="55.4736" y1="54.4068" x2="55.9308" y2="54.864" width="0.1524" layer="16"/>
|
||||
<wire x1="55.9308" y1="54.864" x2="56.5404" y2="54.864" width="0.1524" layer="16"/>
|
||||
<wire x1="56.5404" y1="54.864" x2="56.8452" y2="54.5592" width="0.1524" layer="16"/>
|
||||
<wire x1="56.8452" y1="54.5592" x2="60.3504" y2="54.5592" width="0.1524" layer="16"/>
|
||||
<wire x1="60.3504" y1="54.5592" x2="61.8744" y2="56.0832" width="0.1524" layer="16"/>
|
||||
<wire x1="61.8744" y1="56.0832" x2="73.152" y2="56.0832" width="0.1524" layer="16"/>
|
||||
<via x="79.7052" y="56.0832" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6778,8 +6775,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="23.114" y="95.0468" extent="1-16" drill="0.3"/>
|
||||
<via x="18.9992" y="97.3328" extent="1-16" drill="0.3"/>
|
||||
<via x="17.018" y="95.1992" extent="1-16" drill="0.3"/>
|
||||
<via x="58.4708" y="48.8696" extent="1-16" drill="0.3"/>
|
||||
<via x="56.7944" y="49.022" extent="1-16" drill="0.3"/>
|
||||
<via x="58.6232" y="48.8696" extent="1-16" drill="0.3"/>
|
||||
<via x="41.7068" y="43.688" extent="1-16" drill="0.3"/>
|
||||
<via x="48.0314" y="38.3286" extent="1-16" drill="0.3"/>
|
||||
<via x="24.7904" y="31.496" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -7099,10 +7095,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
</signal>
|
||||
<signal name="IPL2_30">
|
||||
<contactref element="IC1" pad="G12"/>
|
||||
<via x="58.5216" y="54.1528" extent="1-16" drill="0.3"/>
|
||||
<wire x1="58.5216" y1="54.1528" x2="58.5216" y2="51.6382" width="0.1524" layer="1"/>
|
||||
<wire x1="58.5216" y1="51.6382" x2="57.2262" y2="50.3428" width="0.1524" layer="1"/>
|
||||
<wire x1="58.5216" y1="54.1528" x2="68.1736" y2="54.1528" width="0.1524" layer="16"/>
|
||||
<via x="56.2356" y="54.1528" extent="1-16" drill="0.3"/>
|
||||
<wire x1="56.2356" y1="54.1528" x2="56.2356" y2="51.3334" width="0.1524" layer="1"/>
|
||||
<wire x1="56.2356" y1="51.3334" x2="57.2262" y2="50.3428" width="0.1524" layer="1"/>
|
||||
<wire x1="56.2356" y1="54.1528" x2="68.1736" y2="54.1528" width="0.1524" layer="16"/>
|
||||
<wire x1="68.1736" y1="54.1528" x2="68.2752" y2="54.2544" width="0.1524" layer="16"/>
|
||||
<via x="68.2752" y="54.2544" extent="1-16" drill="0.3"/>
|
||||
<wire x1="68.2752" y1="54.2544" x2="68.2752" y2="57.5564" width="0.1524" layer="1"/>
|
||||
|
|
@ -7993,15 +7989,15 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
</signal>
|
||||
</signals>
|
||||
<errors>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,3849587e8adf1064"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,a0a8a9f4a989a0d5"/>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,3849587e8adf1064"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,93e4923c922593fd"/>
|
||||
<approved hash="18,30,a0a8a9f4a989a0d5"/>
|
||||
</errors>
|
||||
</board>
|
||||
</drawing>
|
||||
|
|
|
|||
|
|
@ -2919,18 +2919,20 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="63.5254" y1="48.5902" x2="63.5254" y2="43.3832" width="0.1524" layer="1"/>
|
||||
<wire x1="42.4434" y1="28.4086" x2="42.4434" y2="34.0614" width="0.1524" layer="1"/>
|
||||
<wire x1="42.4434" y1="34.0614" x2="42.9768" y2="34.5948" width="0.1524" layer="1"/>
|
||||
<via x="43.5864" y="41.8084" extent="1-16" drill="0.3"/>
|
||||
<wire x1="58.8518" y1="41.8084" x2="59.7662" y2="42.7228" width="0.1524" layer="16"/>
|
||||
<via x="43.5864" y="39.3192" extent="1-16" drill="0.3"/>
|
||||
<contactref element="X1" pad="B16"/>
|
||||
<wire x1="63.5508" y1="48.6156" x2="64.008" y2="49.0728" width="0.1524" layer="16"/>
|
||||
<wire x1="64.008" y1="49.0728" x2="69.6468" y2="49.0728" width="0.1524" layer="16"/>
|
||||
<wire x1="69.6468" y1="49.0728" x2="71.0184" y2="50.4444" width="0.1524" layer="16"/>
|
||||
<wire x1="71.0184" y1="50.4444" x2="84.0232" y2="50.4444" width="0.1524" layer="16"/>
|
||||
<wire x1="84.0232" y1="50.4444" x2="85.09" y2="51.5112" width="0.1524" layer="16"/>
|
||||
<wire x1="43.5864" y1="41.8084" x2="58.8518" y2="41.8084" width="0.1524" layer="16"/>
|
||||
<wire x1="43.5864" y1="41.8084" x2="43.5864" y2="37.338" width="0.1524" layer="1"/>
|
||||
<wire x1="43.5864" y1="39.3192" x2="58.0644" y2="39.3192" width="0.1524" layer="16"/>
|
||||
<wire x1="43.5864" y1="39.3192" x2="43.5864" y2="37.338" width="0.1524" layer="1"/>
|
||||
<wire x1="43.5864" y1="37.338" x2="42.9768" y2="36.7284" width="0.1524" layer="1"/>
|
||||
<wire x1="42.9768" y1="36.7284" x2="42.9768" y2="34.5948" width="0.1524" layer="1"/>
|
||||
<wire x1="58.0644" y1="39.3192" x2="58.8264" y2="40.0812" width="0.1524" layer="16"/>
|
||||
<wire x1="58.8264" y1="40.0812" x2="58.8264" y2="41.783" width="0.1524" layer="16"/>
|
||||
<wire x1="58.8264" y1="41.783" x2="59.7662" y2="42.7228" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="D1">
|
||||
<contactref element="IC1" pad="K12"/>
|
||||
|
|
@ -2949,8 +2951,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="43.7388" y1="28.434" x2="43.7388" y2="34.5948" width="0.1524" layer="1"/>
|
||||
<wire x1="43.7388" y1="34.5948" x2="43.688" y2="34.6456" width="0.1524" layer="1"/>
|
||||
<wire x1="43.688" y1="34.6456" x2="43.688" y2="35.4584" width="0.1524" layer="1"/>
|
||||
<wire x1="43.688" y1="35.4584" x2="45.5676" y2="37.338" width="0.1524" layer="1"/>
|
||||
<wire x1="45.5676" y1="37.338" x2="45.5676" y2="40.2336" width="0.1524" layer="1"/>
|
||||
<wire x1="43.688" y1="35.4584" x2="45.8724" y2="37.6428" width="0.1524" layer="1"/>
|
||||
<wire x1="45.8724" y1="37.6428" x2="45.8724" y2="40.5384" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="C16"/>
|
||||
<wire x1="62.5348" y1="49.5808" x2="69.5452" y2="49.5808" width="0.1524" layer="16"/>
|
||||
<wire x1="69.5452" y1="49.5808" x2="71.4756" y2="51.5112" width="0.1524" layer="16"/>
|
||||
|
|
@ -2960,10 +2962,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="56.5404" y1="44.196" x2="57.15" y2="43.5864" width="0.1524" layer="1"/>
|
||||
<wire x1="57.15" y1="43.5864" x2="57.15" y2="42.799" width="0.1524" layer="1"/>
|
||||
<wire x1="57.15" y1="42.799" x2="57.2262" y2="42.7228" width="0.1524" layer="1"/>
|
||||
<wire x1="45.5676" y1="40.2336" x2="48.4632" y2="43.1292" width="0.1524" layer="1"/>
|
||||
<wire x1="48.4632" y1="43.1292" x2="51.2064" y2="43.1292" width="0.1524" layer="1"/>
|
||||
<wire x1="51.2064" y1="43.1292" x2="51.9684" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<wire x1="51.9684" y1="43.8912" x2="53.1876" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<wire x1="45.8724" y1="40.5384" x2="48.006" y2="42.672" width="0.1524" layer="1"/>
|
||||
<wire x1="48.006" y1="42.672" x2="50.9016" y2="42.672" width="0.1524" layer="1"/>
|
||||
<wire x1="50.9016" y1="42.672" x2="52.1208" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<wire x1="52.1208" y1="43.8912" x2="53.1876" y2="43.8912" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="D2">
|
||||
<contactref element="IC1" pad="L13"/>
|
||||
|
|
@ -3014,11 +3016,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="46.2026" y1="35.433" x2="47.244" y2="36.4744" width="0.1524" layer="1"/>
|
||||
<via x="47.244" y="36.4744" extent="1-16" drill="0.3"/>
|
||||
<wire x1="47.244" y1="36.4744" x2="47.3456" y2="36.576" width="0.1524" layer="16"/>
|
||||
<wire x1="47.3456" y1="36.576" x2="54.864" y2="36.576" width="0.1524" layer="16"/>
|
||||
<wire x1="54.864" y1="36.576" x2="56.8452" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="56.8452" y1="38.5572" x2="57.6072" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="57.6072" y1="38.5572" x2="58.5216" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<wire x1="58.5216" y1="37.6428" x2="59.7662" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<wire x1="47.3456" y1="36.576" x2="58.674" y2="36.576" width="0.1524" layer="16"/>
|
||||
<wire x1="58.674" y1="36.576" x2="59.7408" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<wire x1="59.7408" y1="37.6428" x2="59.7662" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<contactref element="X1" pad="C15"/>
|
||||
<wire x1="69.6468" y1="48.514" x2="70.104" y2="48.9712" width="0.1524" layer="16"/>
|
||||
<wire x1="64.516" y1="39.5732" x2="65.3288" y2="39.5732" width="0.1524" layer="1"/>
|
||||
|
|
@ -3110,9 +3110,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="62.23" y1="37.4904" x2="63.9572" y2="35.7632" width="0.1524" layer="1"/>
|
||||
<wire x1="63.9572" y1="35.7632" x2="65.3288" y2="35.7632" width="0.1524" layer="1"/>
|
||||
<via x="68.4276" y="42.8244" extent="1-16" drill="0.3"/>
|
||||
<wire x1="68.4276" y1="42.8244" x2="69.342" y2="42.8244" width="0.1524" layer="16"/>
|
||||
<wire x1="69.342" y1="42.8244" x2="69.6468" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<wire x1="69.6468" y1="43.1292" x2="71.1708" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<wire x1="68.4276" y1="42.8244" x2="68.8848" y2="42.8244" width="0.1524" layer="16"/>
|
||||
<wire x1="68.8848" y1="42.8244" x2="69.1896" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<wire x1="69.1896" y1="43.1292" x2="71.1708" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<wire x1="71.1708" y1="43.1292" x2="71.4756" y2="42.8244" width="0.1524" layer="16"/>
|
||||
<wire x1="71.4756" y1="42.8244" x2="84.0232" y2="42.8244" width="0.1524" layer="16"/>
|
||||
<wire x1="84.0232" y1="42.8244" x2="85.09" y2="43.8912" width="0.1524" layer="16"/>
|
||||
|
|
@ -3184,8 +3184,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<contactref element="IC1" pad="M11"/>
|
||||
<contactref element="IC3" pad="60"/>
|
||||
<contactref element="IC6" pad="3"/>
|
||||
<wire x1="64.3636" y1="38.862" x2="55.9308" y2="38.862" width="0.1524" layer="16"/>
|
||||
<wire x1="55.9308" y1="38.862" x2="54.7116" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<wire x1="65.278" y1="38.5572" x2="55.626" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="55.626" y1="38.5572" x2="54.7116" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<wire x1="54.7116" y1="37.6428" x2="54.6862" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<wire x1="56.6534" y1="26.8986" x2="56.388" y2="27.164" width="0.1524" layer="1"/>
|
||||
<wire x1="56.388" y1="28.0416" x2="56.388" y2="33.0708" width="0.1524" layer="1"/>
|
||||
|
|
@ -3206,8 +3206,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="70.866" y1="41.4528" x2="71.5772" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<wire x1="71.5772" y1="41.4528" x2="71.6788" y2="41.3512" width="0.1524" layer="16"/>
|
||||
<wire x1="71.6788" y1="41.3512" x2="82.55" y2="41.3512" width="0.1524" layer="16"/>
|
||||
<wire x1="64.3636" y1="38.862" x2="66.548" y2="41.0464" width="0.1524" layer="16"/>
|
||||
<wire x1="66.548" y1="41.0464" x2="70.4596" y2="41.0464" width="0.1524" layer="16"/>
|
||||
<wire x1="65.278" y1="38.5572" x2="67.7672" y2="41.0464" width="0.1524" layer="16"/>
|
||||
<wire x1="67.7672" y1="41.0464" x2="70.4596" y2="41.0464" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="D10">
|
||||
<contactref element="IC1" pad="L10"/>
|
||||
|
|
@ -4045,10 +4045,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="17.0688" y1="27.7368" x2="17.8308" y2="26.9748" width="0.1524" layer="16"/>
|
||||
<wire x1="17.8308" y1="26.9748" x2="21.6408" y2="26.9748" width="0.1524" layer="16"/>
|
||||
<via x="21.6408" y="26.9748" extent="1-16" drill="0.3"/>
|
||||
<wire x1="35.5854" y1="38.862" x2="36.9062" y2="40.1828" width="0.1524" layer="16"/>
|
||||
<wire x1="35.5854" y1="38.862" x2="28.956" y2="38.862" width="0.1524" layer="16"/>
|
||||
<wire x1="28.956" y1="38.862" x2="28.3972" y2="39.4208" width="0.1524" layer="16"/>
|
||||
<wire x1="28.3972" y1="39.4208" x2="19.812" y2="39.4208" width="0.1524" layer="16"/>
|
||||
<wire x1="19.812" y1="39.4208" x2="19.812" y2="36.4236" width="0.1524" layer="1"/>
|
||||
<wire x1="19.812" y1="36.4236" x2="21.6408" y2="34.5948" width="0.1524" layer="1"/>
|
||||
<wire x1="35.6616" y1="40.2336" x2="36.8554" y2="40.2336" width="0.1524" layer="1"/>
|
||||
|
|
@ -4056,6 +4052,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="35.5092" y1="41.4528" x2="35.2044" y2="41.148" width="0.1524" layer="1"/>
|
||||
<wire x1="35.2044" y1="41.148" x2="35.2044" y2="40.6908" width="0.1524" layer="1"/>
|
||||
<wire x1="35.2044" y1="40.6908" x2="35.6616" y2="40.2336" width="0.1524" layer="1"/>
|
||||
<wire x1="19.812" y1="39.4208" x2="21.844" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<wire x1="21.844" y1="41.4528" x2="36.1188" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<wire x1="36.1188" y1="41.4528" x2="36.9062" y2="40.6654" width="0.1524" layer="16"/>
|
||||
<wire x1="36.9062" y1="40.6654" x2="36.9062" y2="40.1828" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="D31">
|
||||
<contactref element="IC1" pad="N01"/>
|
||||
|
|
@ -5081,19 +5081,29 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="50.4952" y1="83.82" x2="45.2882" y2="83.82" width="0.3048" layer="16"/>
|
||||
<via x="45.2882" y="83.82" extent="1-16" drill="0.3"/>
|
||||
<wire x1="45.2896" y1="83.8186" x2="45.2882" y2="83.82" width="0.1524" layer="1"/>
|
||||
<wire x1="51.2064" y1="58.9788" x2="64.4652" y2="58.9788" width="0.3048" layer="16"/>
|
||||
<via x="64.4652" y="58.9788" extent="1-16" drill="0.3"/>
|
||||
<wire x1="24.7904" y1="37.8206" x2="23.2918" y2="37.8206" width="0.4064" layer="1"/>
|
||||
<wire x1="23.2918" y1="37.8206" x2="23.1648" y2="37.9476" width="0.4064" layer="1"/>
|
||||
<wire x1="23.1648" y1="37.9476" x2="23.1648" y2="41.7576" width="0.4064" layer="1"/>
|
||||
<via x="23.1648" y="41.7576" extent="1-16" drill="0.3"/>
|
||||
<wire x1="23.1648" y1="41.7576" x2="41.4528" y2="41.7576" width="0.4064" layer="16"/>
|
||||
<wire x1="41.4528" y1="41.7576" x2="43.434" y2="43.7388" width="0.4064" layer="16"/>
|
||||
<wire x1="43.434" y1="43.7388" x2="50.7492" y2="43.7388" width="0.4064" layer="16"/>
|
||||
<via x="50.7492" y="43.7388" extent="1-16" drill="0.3"/>
|
||||
<wire x1="50.7492" y1="43.7388" x2="50.7492" y2="58.5216" width="0.4064" layer="1"/>
|
||||
<via x="50.7492" y="58.5216" extent="1-16" drill="0.3"/>
|
||||
<wire x1="51.2064" y1="58.9788" x2="50.7492" y2="58.5216" width="0.3048" layer="16"/>
|
||||
<wire x1="38.862" y1="41.3004" x2="57.4548" y2="41.3004" width="0.4064" layer="16"/>
|
||||
<wire x1="38.862" y1="41.3004" x2="38.2524" y2="40.6908" width="0.4064" layer="16"/>
|
||||
<wire x1="38.2524" y1="40.6908" x2="38.2524" y2="39.1668" width="0.4064" layer="16"/>
|
||||
<wire x1="38.2524" y1="39.1668" x2="37.9476" y2="38.862" width="0.4064" layer="16"/>
|
||||
<wire x1="37.9476" y1="38.862" x2="27.432" y2="38.862" width="0.4064" layer="16"/>
|
||||
<wire x1="27.432" y1="38.862" x2="26.3906" y2="37.8206" width="0.4064" layer="16"/>
|
||||
<wire x1="26.3906" y1="37.8206" x2="24.7904" y2="37.8206" width="0.4064" layer="16"/>
|
||||
<wire x1="64.4652" y1="58.9788" x2="64.4652" y2="58.2168" width="0.4064" layer="1"/>
|
||||
<wire x1="64.4652" y1="58.2168" x2="60.3504" y2="54.102" width="0.4064" layer="1"/>
|
||||
<wire x1="60.3504" y1="54.102" x2="59.5884" y2="54.102" width="0.4064" layer="1"/>
|
||||
<wire x1="59.5884" y1="54.102" x2="58.5216" y2="53.0352" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="53.0352" x2="58.5216" y2="50.1396" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="50.1396" x2="57.4548" y2="49.0728" width="0.4064" layer="1"/>
|
||||
<wire x1="57.4548" y1="49.0728" x2="56.8452" y2="49.0728" width="0.4064" layer="1"/>
|
||||
<wire x1="56.8452" y1="49.0728" x2="55.9308" y2="48.1584" width="0.4064" layer="1"/>
|
||||
<wire x1="55.9308" y1="48.1584" x2="55.9308" y2="47.244" width="0.4064" layer="1"/>
|
||||
<wire x1="55.9308" y1="47.244" x2="56.5404" y2="46.6344" width="0.4064" layer="1"/>
|
||||
<wire x1="56.5404" y1="46.6344" x2="57.7596" y2="46.6344" width="0.4064" layer="1"/>
|
||||
<wire x1="57.7596" y1="46.6344" x2="58.5216" y2="45.8724" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="45.8724" x2="58.5216" y2="42.3672" width="0.4064" layer="1"/>
|
||||
<wire x1="58.5216" y1="42.3672" x2="58.2168" y2="42.0624" width="0.4064" layer="1"/>
|
||||
<wire x1="57.4548" y1="41.3004" x2="58.2168" y2="42.0624" width="0.4064" layer="16"/>
|
||||
<via x="58.2168" y="42.0624" extent="1-16" drill="0.3"/>
|
||||
</signal>
|
||||
<signal name="BERR">
|
||||
<contactref element="IC2" pad="22"/>
|
||||
|
|
@ -5503,13 +5513,12 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="87.63" y1="43.8912" x2="86.106" y2="42.3672" width="0.1524" layer="16"/>
|
||||
<wire x1="78.3336" y1="42.3672" x2="71.3232" y2="42.3672" width="0.1524" layer="16"/>
|
||||
<wire x1="71.3232" y1="42.3672" x2="71.0184" y2="42.672" width="0.1524" layer="16"/>
|
||||
<wire x1="71.0184" y1="42.672" x2="69.9516" y2="42.672" width="0.1524" layer="16"/>
|
||||
<wire x1="69.9516" y1="42.672" x2="68.7324" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<wire x1="68.7324" y1="41.4528" x2="46.1772" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<wire x1="46.1772" y1="41.4528" x2="45.8724" y2="41.148" width="0.1524" layer="16"/>
|
||||
<wire x1="45.8724" y1="41.148" x2="45.4152" y2="41.148" width="0.1524" layer="16"/>
|
||||
<via x="45.4152" y="41.148" extent="1-16" drill="0.3"/>
|
||||
<wire x1="45.4152" y1="41.148" x2="45.4152" y2="41.91" width="0.1524" layer="1"/>
|
||||
<wire x1="71.0184" y1="42.672" x2="69.342" y2="42.672" width="0.1524" layer="16"/>
|
||||
<wire x1="69.342" y1="42.672" x2="68.1228" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<via x="45.2628" y="38.7096" extent="1-16" drill="0.3"/>
|
||||
<wire x1="45.2628" y1="38.7096" x2="45.2628" y2="39.624" width="0.1524" layer="1"/>
|
||||
<wire x1="45.2628" y1="39.624" x2="45.4152" y2="39.7764" width="0.1524" layer="1"/>
|
||||
<wire x1="45.4152" y1="39.7764" x2="45.4152" y2="41.91" width="0.1524" layer="1"/>
|
||||
<wire x1="45.4152" y1="41.91" x2="46.0248" y2="42.5196" width="0.1524" layer="1"/>
|
||||
<wire x1="46.0248" y1="42.5196" x2="47.0916" y2="42.5196" width="0.1524" layer="1"/>
|
||||
<wire x1="47.0916" y1="42.5196" x2="49.8348" y2="45.2628" width="0.1524" layer="1"/>
|
||||
|
|
@ -5538,13 +5547,16 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="46.1772" y1="54.356" x2="46.5836" y2="54.356" width="0.1524" layer="16"/>
|
||||
<wire x1="46.5836" y1="54.356" x2="48.1584" y2="55.9308" width="0.1524" layer="16"/>
|
||||
<wire x1="48.1584" y1="55.9308" x2="49.0728" y2="55.9308" width="0.1524" layer="16"/>
|
||||
<wire x1="45.2628" y1="38.7096" x2="45.8724" y2="38.7096" width="0.1524" layer="16"/>
|
||||
<wire x1="45.8724" y1="38.7096" x2="46.0248" y2="38.862" width="0.1524" layer="16"/>
|
||||
<wire x1="46.0248" y1="38.862" x2="64.77" y2="38.862" width="0.1524" layer="16"/>
|
||||
<wire x1="64.77" y1="38.862" x2="67.3608" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<wire x1="67.3608" y1="41.4528" x2="68.1228" y2="41.4528" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="CIIN">
|
||||
<contactref element="IC1" pad="L01"/>
|
||||
<contactref element="IC7" pad="47"/>
|
||||
<wire x1="35.814" y1="72.0852" x2="35.814" y2="40.8432" width="0.1524" layer="1"/>
|
||||
<wire x1="35.2044" y1="39.1668" x2="30.3022" y2="39.1668" width="0.1524" layer="16"/>
|
||||
<wire x1="30.3022" y1="39.1668" x2="29.2862" y2="40.1828" width="0.1524" layer="16"/>
|
||||
<wire x1="43.8912" y1="87.3252" x2="44.958" y2="88.392" width="0.1524" layer="16"/>
|
||||
<wire x1="44.958" y1="88.392" x2="68.58" y2="88.392" width="0.1524" layer="16"/>
|
||||
<wire x1="71.9328" y1="85.0392" x2="71.9328" y2="64.77" width="0.1524" layer="1"/>
|
||||
|
|
@ -5563,8 +5575,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="85.9536" y1="32.4612" x2="86.4108" y2="32.004" width="0.1524" layer="1"/>
|
||||
<wire x1="86.4108" y1="32.004" x2="86.4108" y2="27.3304" width="0.1524" layer="1"/>
|
||||
<wire x1="86.4108" y1="27.3304" x2="87.63" y2="26.1112" width="0.1524" layer="1"/>
|
||||
<wire x1="35.2044" y1="39.1668" x2="35.814" y2="39.7764" width="0.1524" layer="16"/>
|
||||
<wire x1="35.814" y1="39.7764" x2="35.814" y2="40.8432" width="0.1524" layer="16"/>
|
||||
<via x="35.814" y="40.8432" extent="1-16" drill="0.3"/>
|
||||
<wire x1="36.4236" y1="77.1144" x2="36.4236" y2="78.0288" width="0.1524" layer="1"/>
|
||||
<wire x1="36.4236" y1="78.0288" x2="36.7284" y2="78.3336" width="0.1524" layer="1"/>
|
||||
|
|
@ -5578,6 +5588,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="36.4608" y1="73.6092" x2="36.4236" y2="73.572" width="0.1524" layer="1"/>
|
||||
<via x="68.58" y="88.392" extent="1-16" drill="0.3"/>
|
||||
<wire x1="68.58" y1="88.392" x2="71.9328" y2="85.0392" width="0.1524" layer="1"/>
|
||||
<wire x1="29.2862" y1="40.1828" x2="30.2514" y2="41.148" width="0.1524" layer="16"/>
|
||||
<wire x1="30.2514" y1="41.148" x2="34.8996" y2="41.148" width="0.1524" layer="16"/>
|
||||
<wire x1="34.8996" y1="41.148" x2="35.2044" y2="40.8432" width="0.1524" layer="16"/>
|
||||
<wire x1="35.2044" y1="40.8432" x2="35.814" y2="40.8432" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="CIOUT">
|
||||
<contactref element="IC1" pad="C02"/>
|
||||
|
|
@ -6766,8 +6780,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="17.018" y="95.1992" extent="1-16" drill="0.3"/>
|
||||
<via x="58.4708" y="48.8696" extent="1-16" drill="0.3"/>
|
||||
<via x="56.7944" y="49.022" extent="1-16" drill="0.3"/>
|
||||
<via x="42.0116" y="43.5356" extent="1-16" drill="0.3"/>
|
||||
<via x="49.8602" y="42.4434" extent="1-16" drill="0.3"/>
|
||||
<via x="41.7068" y="43.688" extent="1-16" drill="0.3"/>
|
||||
<via x="48.0314" y="38.3286" extent="1-16" drill="0.3"/>
|
||||
<via x="24.7904" y="31.496" extent="1-16" drill="0.3"/>
|
||||
<via x="24.7904" y="28.9052" extent="1-16" drill="0.3"/>
|
||||
<via x="19.9136" y="32.1056" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -7088,9 +7102,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="58.5216" y="54.1528" extent="1-16" drill="0.3"/>
|
||||
<wire x1="58.5216" y1="54.1528" x2="58.5216" y2="51.6382" width="0.1524" layer="1"/>
|
||||
<wire x1="58.5216" y1="51.6382" x2="57.2262" y2="50.3428" width="0.1524" layer="1"/>
|
||||
<wire x1="58.5216" y1="54.1528" x2="60.198" y2="54.1528" width="0.1524" layer="16"/>
|
||||
<wire x1="60.198" y1="54.1528" x2="60.2996" y2="54.2544" width="0.1524" layer="16"/>
|
||||
<wire x1="60.2996" y1="54.2544" x2="68.2752" y2="54.2544" width="0.1524" layer="16"/>
|
||||
<wire x1="58.5216" y1="54.1528" x2="68.1736" y2="54.1528" width="0.1524" layer="16"/>
|
||||
<wire x1="68.1736" y1="54.1528" x2="68.2752" y2="54.2544" width="0.1524" layer="16"/>
|
||||
<via x="68.2752" y="54.2544" extent="1-16" drill="0.3"/>
|
||||
<wire x1="68.2752" y1="54.2544" x2="68.2752" y2="57.5564" width="0.1524" layer="1"/>
|
||||
<wire x1="68.2752" y1="57.5564" x2="65.8876" y2="59.944" width="0.1524" layer="1"/>
|
||||
|
|
@ -7178,8 +7191,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="18.8976" y1="98.298" x2="12.8016" y2="92.202" width="0.1524" layer="1"/>
|
||||
<wire x1="15.3162" y1="19.05" x2="13.142375" y2="19.05" width="0.1524" layer="1"/>
|
||||
<wire x1="13.142375" y1="19.05" x2="12.8016" y2="19.390775" width="0.1524" layer="1"/>
|
||||
<wire x1="12.8016" y1="19.390775" x2="12.8016" y2="38.7096" width="0.1524" layer="1"/>
|
||||
<wire x1="12.8016" y1="38.7096" x2="12.8016" y2="92.202" width="0.1524" layer="1"/>
|
||||
<wire x1="12.8016" y1="19.390775" x2="12.8016" y2="41.4528" width="0.1524" layer="1"/>
|
||||
<wire x1="12.8016" y1="41.4528" x2="12.8016" y2="92.202" width="0.1524" layer="1"/>
|
||||
<wire x1="12.8016" y1="3.81" x2="13.1826" y2="3.429" width="0.1524" layer="1"/>
|
||||
<wire x1="13.1826" y1="3.429" x2="15.5448" y2="3.429" width="0.1524" layer="1"/>
|
||||
<wire x1="15.3924" y1="18.9738" x2="15.3162" y2="19.05" width="0.1524" layer="1"/>
|
||||
|
|
@ -7194,12 +7207,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="64.9224" y1="46.0248" x2="63.0936" y2="44.196" width="0.1524" layer="16"/>
|
||||
<wire x1="63.0936" y1="44.196" x2="60.8076" y2="44.196" width="0.1524" layer="16"/>
|
||||
<wire x1="60.8076" y1="44.196" x2="60.5028" y2="43.8912" width="0.1524" layer="16"/>
|
||||
<wire x1="51.9684" y1="43.8912" x2="51.2064" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<wire x1="51.2064" y1="43.1292" x2="43.6118" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<via x="12.8016" y="38.7096" extent="1-16" drill="0.3"/>
|
||||
<wire x1="39.0398" y1="38.5572" x2="28.6512" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="28.6512" y1="38.5572" x2="28.4988" y2="38.7096" width="0.1524" layer="16"/>
|
||||
<wire x1="28.4988" y1="38.7096" x2="12.8016" y2="38.7096" width="0.1524" layer="16"/>
|
||||
<via x="12.8016" y="41.4528" extent="1-16" drill="0.3"/>
|
||||
<wire x1="65.3288" y1="29.6164" x2="65.4304" y2="29.718" width="0.1524" layer="1"/>
|
||||
<wire x1="65.4304" y1="29.718" x2="66.7512" y2="29.718" width="0.1524" layer="1"/>
|
||||
<wire x1="66.7512" y1="29.718" x2="67.056" y2="30.0228" width="0.1524" layer="1"/>
|
||||
|
|
@ -7209,8 +7217,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="69.9516" y="46.482" extent="1-16" drill="0.3"/>
|
||||
<wire x1="69.9516" y1="46.482" x2="65.6844" y2="46.482" width="0.1524" layer="16"/>
|
||||
<wire x1="65.6844" y1="46.482" x2="65.2272" y2="46.0248" width="0.1524" layer="16"/>
|
||||
<wire x1="51.9684" y1="43.8912" x2="60.5028" y2="43.8912" width="0.1524" layer="16"/>
|
||||
<wire x1="43.6118" y1="43.1292" x2="39.0398" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="12.8016" y1="41.4528" x2="21.336" y2="41.4528" width="0.1524" layer="16"/>
|
||||
<wire x1="21.336" y1="41.4528" x2="21.6408" y2="41.7576" width="0.1524" layer="16"/>
|
||||
<wire x1="21.6408" y1="41.7576" x2="40.6908" y2="41.7576" width="0.1524" layer="16"/>
|
||||
<wire x1="40.6908" y1="41.7576" x2="42.8244" y2="43.8912" width="0.1524" layer="16"/>
|
||||
<wire x1="42.8244" y1="43.8912" x2="60.5028" y2="43.8912" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="R/W_00">
|
||||
<contactref element="IC2" pad="9"/>
|
||||
|
|
@ -7982,15 +7993,15 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
</signal>
|
||||
</signals>
|
||||
<errors>
|
||||
<approved hash="18,30,3849587e8adf1064"/>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,93e4923c922593fd"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,3849587e8adf1064"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,a0a8a9f4a989a0d5"/>
|
||||
<approved hash="18,30,93e4923c922593fd"/>
|
||||
</errors>
|
||||
</board>
|
||||
</drawing>
|
||||
|
|
|
|||
|
|
@ -2859,8 +2859,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<attribute name="NAME" x="27.559" y="88.9762" size="1.27" layer="25" rot="R90"/>
|
||||
<attribute name="VALUE" x="27.3558" y="88.6714" size="1.27" layer="27" rot="R90"/>
|
||||
</element>
|
||||
<element name="R17" library="rcl" package="R0603" value="4,7k" x="80.01" y="37.6428" smashed="yes" rot="R90">
|
||||
<attribute name="NAME" x="79.0702" y="36.3982" size="1.27" layer="25" rot="R90"/>
|
||||
<element name="R17" library="rcl" package="R0603" value="4,7k" x="79.8576" y="37.6428" smashed="yes" rot="R90">
|
||||
<attribute name="NAME" x="78.9178" y="36.3982" size="1.27" layer="25" rot="R90"/>
|
||||
</element>
|
||||
<element name="RN4" library="resistor-dil" package="EXBV8V" value="4,7k" x="79.248" y="75.1332" smashed="yes" rot="R90">
|
||||
<attribute name="OC_NEWARK" value="unknown" x="79.248" y="75.1332" size="1.778" layer="27" rot="R90" display="off"/>
|
||||
|
|
@ -5517,7 +5517,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="49.8348" y="55.1688" extent="1-16" drill="0.3"/>
|
||||
<wire x1="49.8348" y1="55.1688" x2="49.0728" y2="55.9308" width="0.1524" layer="16"/>
|
||||
<contactref element="R17" pad="2"/>
|
||||
<wire x1="80.01" y1="38.4928" x2="79.4648" y2="38.4928" width="0.1524" layer="1"/>
|
||||
<wire x1="79.8576" y1="38.4928" x2="79.4648" y2="38.4928" width="0.1524" layer="1"/>
|
||||
<wire x1="79.4648" y1="38.4928" x2="78.7908" y2="39.1668" width="0.1524" layer="1"/>
|
||||
<wire x1="78.7908" y1="39.1668" x2="78.7908" y2="41.91" width="0.1524" layer="1"/>
|
||||
<via x="78.7908" y="41.91" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -5547,13 +5547,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="30.3022" y1="39.1668" x2="29.2862" y2="40.1828" width="0.1524" layer="16"/>
|
||||
<wire x1="43.8912" y1="87.3252" x2="44.958" y2="88.392" width="0.1524" layer="16"/>
|
||||
<wire x1="44.958" y1="88.392" x2="68.58" y2="88.392" width="0.1524" layer="16"/>
|
||||
<wire x1="71.9328" y1="85.0392" x2="71.9328" y2="64.9224" width="0.1524" layer="1"/>
|
||||
<wire x1="71.9328" y1="64.9224" x2="80.9244" y2="55.9308" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="55.9308" x2="80.9244" y2="48.1584" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="48.1584" x2="80.772" y2="48.006" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="48.006" x2="80.772" y2="47.0916" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="47.0916" x2="80.9244" y2="46.9392" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="46.9392" x2="80.9244" y2="33.0708" width="0.1524" layer="1"/>
|
||||
<wire x1="71.9328" y1="85.0392" x2="71.9328" y2="64.77" width="0.1524" layer="1"/>
|
||||
<wire x1="71.9328" y1="64.77" x2="80.772" y2="55.9308" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="55.9308" x2="80.772" y2="33.2232" width="0.1524" layer="1"/>
|
||||
<contactref element="R8" pad="2"/>
|
||||
<contactref element="X1" pad="A6"/>
|
||||
<wire x1="43.8912" y1="87.3252" x2="39.3192" y2="87.3252" width="0.1524" layer="16"/>
|
||||
|
|
@ -5562,7 +5558,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="39.3192" y1="94.7876" x2="39.2896" y2="94.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="39.3192" y1="87.3252" x2="39.3192" y2="82.296" width="0.1524" layer="1"/>
|
||||
<wire x1="39.3192" y1="82.296" x2="36.7284" y2="79.7052" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="33.0708" x2="81.534" y2="32.4612" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="33.2232" x2="81.534" y2="32.4612" width="0.1524" layer="1"/>
|
||||
<wire x1="81.534" y1="32.4612" x2="85.9536" y2="32.4612" width="0.1524" layer="1"/>
|
||||
<wire x1="85.9536" y1="32.4612" x2="86.4108" y2="32.004" width="0.1524" layer="1"/>
|
||||
<wire x1="86.4108" y1="32.004" x2="86.4108" y2="27.3304" width="0.1524" layer="1"/>
|
||||
|
|
@ -6436,8 +6432,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="52.1716" y1="44.7942" x2="53.0238" y2="44.7942" width="0.6096" layer="1"/>
|
||||
<wire x1="53.0238" y1="44.7942" x2="53.34" y2="45.1104" width="0.6096" layer="1"/>
|
||||
<contactref element="R17" pad="1"/>
|
||||
<wire x1="80.01" y1="36.7928" x2="80.01" y2="36.703" width="0.1524" layer="1"/>
|
||||
<wire x1="80.01" y1="36.703" x2="79.0956" y2="35.7886" width="0.1524" layer="1"/>
|
||||
<wire x1="79.8576" y1="36.7928" x2="79.8576" y2="36.5506" width="0.1524" layer="1"/>
|
||||
<wire x1="79.8576" y1="36.5506" x2="79.0956" y2="35.7886" width="0.1524" layer="1"/>
|
||||
<wire x1="36.4236" y1="75.272" x2="36.4236" y2="76.2" width="0.1524" layer="1"/>
|
||||
<wire x1="36.4236" y1="76.2" x2="34.8996" y2="77.724" width="0.1524" layer="1"/>
|
||||
<wire x1="52.6034" y1="96.608" x2="52.6034" y2="97.663" width="0.1524" layer="1"/>
|
||||
|
|
@ -6448,54 +6444,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="70.5612" y="87.4776" extent="1-16" drill="0.3"/>
|
||||
<wire x1="71.9836" y1="54.4204" x2="71.9836" y2="52.832" width="0.1524" layer="1"/>
|
||||
<wire x1="71.9836" y1="52.832" x2="72.2376" y2="52.578" width="0.1524" layer="1"/>
|
||||
<wire x1="69.8246" y1="88.6596" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2328" y1="98.4504" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6354" y1="96.608" x2="57.1754" y2="98.4788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2896" y1="94.8172" x2="52.6034" y2="96.608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="86.5124" x2="44.1452" y2="93.726" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.323" y1="80.4418" x2="49.9872" y2="86.5124" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.4236" y1="75.272" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.133" y1="86.7664" x2="34.7256" y2="81.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="60.5028" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.0436" y1="55.3352" x2="42.5082" y2="56.8706" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.5742" y1="53.3794" x2="44.0436" y2="54.19" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9062" y1="57.9628" x2="41.9862" y2="57.3926" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.0248" y1="48.1584" x2="47.5742" y2="53.3794" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="57.9628" x2="48.7172" y2="53.3908" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="52.8828" x2="52.1462" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="47.8028" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="53.34" y1="45.1104" x2="54.6862" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1462" y1="42.7228" x2="52.1716" y2="44.7942" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="41.9862" y1="40.1828" x2="46.0378" y2="44.9772" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.1348" y1="42.9514" x2="41.9862" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="47.8028" x2="37.3012" y2="45.2882" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.8262" y1="52.8828" x2="34.3662" y2="47.8028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.4652" y1="55.0164" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="71.9836" y1="54.4204" x2="65.0104" y2="54.4712" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.424" y1="46.6344" x2="73.3688" y2="52.578" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="80.01" y1="36.7928" x2="75.4126" y2="44.6278" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.3872" y1="31.4084" x2="79.0956" y2="33.9208" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.8764" y1="24.9056" x2="75.3872" y2="29.6164" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="23.5712" x2="77.8764" y2="23.4696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="21.0312" x2="87.63" y2="23.5712" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="18.4912" x2="87.63" y2="21.0312" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.5976" y1="33.5788" x2="36.9062" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="35.2806" x2="31.5836" y2="33.5648" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="19.2786" x2="33.3134" y2="26.8986" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="34.3544" x2="24.7904" y2="35.2806" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="37.214" x2="15.3924" y2="34.3544" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="38.862" x2="10.9728" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="40.3606" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="6.5786" x2="33.3134" y2="16.7386" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.513" y1="32.4612" x2="52.1462" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="18.0086" x2="55.1434" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="12.5192" x2="61.4172" y2="17.4104" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.932" y1="5.0686" x2="65.5828" y2="12.5192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.0686" y1="53.9496" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="69.0372" x2="5.1816" y2="55.7022" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="4.9428" y1="84.582" x2="5.1816" y2="70.9422" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.334" y1="18.9738" x2="15.3924" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.4864" y1="3.429" x2="5.334" y2="16.1544" width="0" layer="19" extent="1-1"/>
|
||||
</signal>
|
||||
<signal name="GND">
|
||||
<contactref element="IC2" pad="16"/>
|
||||
|
|
@ -6952,206 +6900,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="20.9804" y="42.0116" extent="1-16" drill="0.3"/>
|
||||
<via x="36.9824" y="55.4228" extent="1-16" drill="0.3"/>
|
||||
<via x="36.9824" y="50.2412" extent="1-16" drill="0.3"/>
|
||||
<via x="72.5932" y="60.8076" extent="1-16" drill="0.3"/>
|
||||
<via x="73.2028" y="61.4172" extent="1-16" drill="0.3"/>
|
||||
<via x="76.5556" y="56.9976" extent="1-16" drill="0.3"/>
|
||||
<via x="48.8188" y="47.3964" extent="1-16" drill="0.3"/>
|
||||
<via x="78.867" y="46.6344" extent="1-16" drill="0.3"/>
|
||||
<via x="16.7894" y="42.0624" extent="1-16" drill="0.3"/>
|
||||
<wire x1="85.7504" y1="96.1644" x2="86.5124" y2="98.7552" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.7316" y1="93.8784" x2="85.7504" y2="96.1644" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.9988" y1="93.5736" x2="87.7316" y2="93.8784" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.473" y1="90.354" x2="81.5532" y2="95.7202" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.7428" y1="88.4428" x2="75.7428" y2="89.9668" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.8952" y1="68.707" x2="78.473" y2="68.5228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.5904" y1="67.2846" x2="75.8952" y2="68.707" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="74.3204" y1="94.3102" x2="76.13" y2="90.354" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.6948" y1="84.328" x2="75.7428" y2="88.4428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="73.2028" y1="61.4172" x2="75.5904" y2="67.2846" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.5932" y1="60.8076" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.8688" y1="60.8076" x2="72.5932" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="69.7484" y1="58.42" x2="67.8688" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.4304" y1="55.3212" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.8396" y1="55.372" x2="65.4304" y2="55.3212" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="58.0136" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.5556" y1="56.9976" x2="72.5932" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.6224" y1="57.0484" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.4116" y1="90.5256" x2="72.6948" y2="84.328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.1604" y1="94.3102" x2="67.4116" y2="90.5256" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="61.6712" y1="97.3836" x2="64.1604" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="95.6564" x2="61.6712" y2="97.3836" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="51.7896" y1="92.8172" x2="57.1754" y2="95.6788" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.7896" y1="94.8172" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="98.3488" x2="49.276" y2="96.2152" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.212" y1="97.1296" x2="47.4472" y2="98.3488" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="94.8172" x2="43.2896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7632" y1="94.6912" x2="37.7896" y2="94.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.6108" y1="97.6884" x2="37.7896" y2="96.4636" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.5788" y1="97.6884" x2="35.6108" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="96.1484" x2="33.5788" y2="97.6884" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.9872" y1="87.4776" x2="50.2864" y2="92.8172" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="48.6156" y1="84.7344" x2="50.6476" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.2896" y1="78.8172" x2="49.3324" y2="80.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.5328" y1="84.4804" x2="48.6156" y2="84.7344" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="45.5676" y1="86.9696" x2="46.5328" y2="84.4804" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.7736" y1="86.3346" x2="45.5676" y2="86.9696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.9768" y1="84.9884" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.4342" y1="86.4108" x2="51.7896" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="60.7568" y1="86.5124" x2="56.4388" y2="86.4108" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.8678" y1="76.835" x2="49.6824" y2="76.8096" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.338" y1="86.8172" x2="42.7736" y2="86.3346" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.7896" y1="86.8172" x2="37.338" y2="86.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.383" y1="86.7664" x2="34.4424" y2="86.5632" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="78.8172" x2="43.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.8762" y1="79.0956" x2="37.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.4708" y1="48.8696" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.7944" y1="49.022" x2="58.4708" y2="48.8696" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="50.3428" x2="56.7944" y2="49.022" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.1716" y1="47.6504" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="45.2628" x2="52.1716" y2="46.5442" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.8188" y1="47.3964" x2="52.1716" y2="47.6504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.8602" y1="42.4434" x2="52.1716" y2="46.5442" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="40.1828" x2="49.8602" y2="42.4434" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.0662" y1="40.1828" x2="49.6062" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="40.1828" x2="47.0662" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.0116" y1="43.5356" x2="44.5262" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.0512" y1="45.2882" x2="42.0116" y2="43.5356" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.592" y1="47.7012" x2="39.0144" y2="46.5328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="50.2412" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="50.3428" x2="36.9824" y2="50.2412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="52.8828" x2="34.3662" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="55.4228" x2="34.3662" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.9824" y1="55.4228" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="30.5816" y1="54.2036" x2="34.3662" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.194" y1="57.2516" x2="30.5816" y2="54.2036" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.3662" y1="45.2628" x2="37.592" y2="47.7012" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="40.1828" x2="42.0116" y2="43.5356" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="54.356" x2="28.194" y2="57.2516" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.876" y1="51.7652" x2="24.7904" y2="54.356" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7396" y1="49.276" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="46.6852" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="44.9072" x2="24.7904" y2="46.6852" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="42.0116" x2="20.9804" y2="44.9072" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="40.3606" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.7894" y1="42.0624" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="14.2748" y1="37.8968" x2="15.24" y2="42.037" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.21" y1="49.022" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="34.414" x2="14.2748" y2="37.8968" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3416" y1="32.1056" x2="10.9728" y2="32.766" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="30.4038" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="32.1056" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.7612" y1="34.2392" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.1452" y1="48.768" x2="48.8188" y2="47.3964" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="31.496" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="28.9052" x2="24.7904" y2="31.496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="25.7302" y1="28.829" x2="24.7904" y2="28.9052" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.718" y1="31.3944" x2="25.7302" y2="28.829" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6862" y1="55.4228" x2="54.6862" y2="50.3428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="37.6428" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.16" y1="41.2496" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.798" y1="30.1244" x2="29.8336" y2="31.51" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.0934" y1="30.1244" x2="34.8234" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3634" y1="28.4086" x2="36.0934" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.6334" y1="30.099" x2="37.3634" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.9034" y1="28.4086" x2="38.6334" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="24.3586" x2="34.8234" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="22.2504" x2="31.9278" y2="24.3586" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="60.5028" x2="36.9824" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="60.5028" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2976" y1="57.9628" x2="44.5262" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.4472" y1="57.9628" x2="44.2976" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.3616" y1="57.9628" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.766" y1="55.3212" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="60.5028" x2="48.3616" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.956" y1="16.3462" x2="31.623" y2="21.8186" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.608" y1="11.9888" x2="33.3134" y2="15.4686" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.4688" y1="14.1224" x2="38.6334" y2="11.9634" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="14.1224" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="14.1224" x2="43.688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.228" y1="14.1224" x2="44.958" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.1076" y1="14.1224" x2="46.228" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.418" y1="19.8628" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="19.9136" x2="42.418" y2="19.8628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="19.9136" x2="43.688" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.2788" y1="19.9136" x2="44.958" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.102" y1="12.6492" x2="48.1076" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="15.4686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.1952" y1="17.1704" x2="61.214" y2="15.4572" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="18.1864" x2="63.1952" y2="17.1704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="16.7132" x2="65.3288" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="19.9136" x2="63.8048" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.7672" y1="15.2908" x2="65.5828" y2="15.3192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.5216" y1="19.9644" x2="62.992" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="52.2732" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="53.594" x2="15.24" y2="52.197" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.8808" y1="67.5132" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.9314" y1="24.7142" x2="15.3924" y2="30.4038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="5.0686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.2356" y1="3.7592" x2="52.6034" y2="3.683" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="3.7592" x2="56.2356" y2="3.7592" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="16.8656" x2="9.9314" y2="24.7142" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="13.8176" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="12.1412" x2="10.3124" y2="13.8176" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.1234" y1="17.2212" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="8.0264" x2="10.3124" y2="12.1412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="13.6652" y1="8.0264" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.7028" y1="4.826" x2="10.7696" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="8.2296" y1="1.6764" x2="9.7028" y2="4.826" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="2.7432" y1="0.9144" x2="7.1234" y2="1.6764" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.778" y1="0.9144" x2="2.7432" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="0.8636" y1="0.9144" x2="1.778" y2="0.9144" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.494" y1="16.5608" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.5448" y1="14.859" x2="15.494" y2="16.5608" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="3.1496" x2="13.6652" y2="8.0264" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.2852" y1="2.3876" x2="19.9136" y2="3.1496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="26.4668" y1="5.9944" x2="21.2852" y2="2.3876" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="23.114" y1="95.0468" x2="31.1912" y2="94.8944" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="18.9992" y1="97.3328" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="17.018" y1="95.1992" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.256" y1="98.7044" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="21.4376" y1="88.5444" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="82.4484" x2="21.4376" y2="88.5444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="83.7692" x2="15.24" y2="82.3722" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3746" y1="84.9376" x2="15.1892" y2="83.7692" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.5692" y1="82.3976" x2="10.3746" y2="84.9376" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.8288" y1="83.3628" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.922" y1="77.3684" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="53.7578" x2="15.1892" y2="53.594" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.0344" y1="49.6824" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.5424" y1="46.6344" x2="72.0344" y2="49.6824" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.867" y1="46.6344" x2="73.6486" y2="46.609" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.1906" y1="39.5224" x2="78.867" y2="46.6344" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.1144" y1="34.5948" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.7956" y1="31.75" x2="77.1144" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="80.1624" y1="34.5948" x2="77.1144" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="32.3088" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.7696" y1="68.6816" x2="10.922" y2="77.3684" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="68.9978" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="68.9864" x2="10.7696" y2="68.6816" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.24" y1="67.1322" x2="15.1892" y2="68.9864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="30.2006" x2="7.0104" y2="37.6428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.3412" y1="83.2104" x2="78.473" y2="83.3436" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="72.9996" x2="78.473" y2="72.828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="62.9412" x2="88.4936" y2="72.9996" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="62.7888" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="52.8828" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="42.672" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="22.2504" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="15.9512" x2="88.4936" y2="22.2504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="13.4112" x2="87.63" y2="15.9512" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.4936" y1="12.192" x2="87.63" y2="13.4112" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.694" y1="12.3444" x2="88.4936" y2="12.192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="2.3368" x2="91.694" y2="12.3444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="1.2192" x2="91.6432" y2="2.3368" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="90.2716" y1="1.2192" x2="91.6432" y2="1.2192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="57.2516" y1="30.1752" x2="58.5216" y2="19.9644" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="29.8704" x2="57.2516" y2="30.1752" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.4332" y1="35.1536" x2="57.263" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.3476" y1="33.4772" x2="62.4332" y2="35.1536" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="31.1912" x2="63.6016" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="97.9932" x2="1.8288" y2="83.3628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="98.9076" x2="1.016" y2="97.9932" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.24" y1="42.037" x2="16.764" y2="42.037" width="0.1524" layer="1"/>
|
||||
<wire x1="16.764" y1="42.037" x2="16.7894" y2="42.0624" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
|
|
@ -8229,13 +7982,13 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
</signal>
|
||||
</signals>
|
||||
<errors>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,3849587e8adf1064"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,4daddc4e8f67e619"/>
|
||||
<approved hash="18,30,1b42dc4e8e6fb74c"/>
|
||||
<approved hash="18,30,a5d25a4e8a6e8dce"/>
|
||||
<approved hash="18,30,c2185cc68efeee34"/>
|
||||
<approved hash="18,30,f646dbc696e743f0"/>
|
||||
<approved hash="18,30,933d5dc68ee6b8e9"/>
|
||||
<approved hash="18,30,93e4923c922593fd"/>
|
||||
<approved hash="18,30,a0a8a9f4a989a0d5"/>
|
||||
</errors>
|
||||
|
|
|
|||
|
|
@ -2974,7 +2974,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="44.9834" y1="34.163" x2="45.4152" y2="34.5948" width="0.1524" layer="1"/>
|
||||
<wire x1="45.4152" y1="34.5948" x2="45.4152" y2="36.576" width="0.1524" layer="1"/>
|
||||
<wire x1="45.4152" y1="36.576" x2="46.1772" y2="37.338" width="0.1524" layer="1"/>
|
||||
<wire x1="46.1772" y1="37.338" x2="46.1772" y2="37.9476" width="0.1524" layer="1"/>
|
||||
<wire x1="46.1772" y1="37.338" x2="46.1772" y2="38.1" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="B15"/>
|
||||
<wire x1="61.5696" y1="46.7868" x2="63.246" y2="46.7868" width="0.1524" layer="16"/>
|
||||
<wire x1="63.246" y1="46.7868" x2="64.4398" y2="47.9806" width="0.1524" layer="16"/>
|
||||
|
|
@ -2991,10 +2991,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="62.9412" y1="41.3004" x2="63.8556" y2="41.3004" width="0.1524" layer="1"/>
|
||||
<wire x1="63.8556" y1="41.3004" x2="64.3128" y2="40.8432" width="0.1524" layer="1"/>
|
||||
<wire x1="64.3128" y1="40.8432" x2="65.3288" y2="40.8432" width="0.1524" layer="1"/>
|
||||
<wire x1="46.1772" y1="37.9476" x2="48.4632" y2="40.2336" width="0.1524" layer="1"/>
|
||||
<wire x1="48.4632" y1="40.2336" x2="48.4632" y2="40.6908" width="0.1524" layer="1"/>
|
||||
<wire x1="48.4632" y1="40.6908" x2="49.53" y2="41.7576" width="0.1524" layer="1"/>
|
||||
<wire x1="49.53" y1="41.7576" x2="52.578" y2="41.7576" width="0.1524" layer="1"/>
|
||||
<wire x1="46.1772" y1="38.1" x2="49.8348" y2="41.7576" width="0.1524" layer="1"/>
|
||||
<wire x1="49.8348" y1="41.7576" x2="52.578" y2="41.7576" width="0.1524" layer="1"/>
|
||||
<wire x1="52.578" y1="41.7576" x2="53.1876" y2="42.3672" width="0.1524" layer="1"/>
|
||||
<wire x1="53.1876" y1="42.3672" x2="53.1876" y2="43.1292" width="0.1524" layer="1"/>
|
||||
<wire x1="53.1876" y1="43.1292" x2="53.9496" y2="43.8912" width="0.1524" layer="1"/>
|
||||
|
|
@ -4047,12 +4045,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="17.0688" y1="27.7368" x2="17.8308" y2="26.9748" width="0.1524" layer="16"/>
|
||||
<wire x1="17.8308" y1="26.9748" x2="21.6408" y2="26.9748" width="0.1524" layer="16"/>
|
||||
<via x="21.6408" y="26.9748" extent="1-16" drill="0.3"/>
|
||||
<wire x1="36.9062" y1="39.2684" x2="36.9062" y2="40.1828" width="0.1524" layer="16"/>
|
||||
<wire x1="36.9062" y1="39.2684" x2="36.4998" y2="38.862" width="0.1524" layer="16"/>
|
||||
<wire x1="36.4998" y1="38.862" x2="29.8704" y2="38.862" width="0.1524" layer="16"/>
|
||||
<wire x1="29.8704" y1="38.862" x2="29.5656" y2="39.1668" width="0.1524" layer="16"/>
|
||||
<wire x1="29.5656" y1="39.1668" x2="28.6512" y2="39.1668" width="0.1524" layer="16"/>
|
||||
<wire x1="28.6512" y1="39.1668" x2="28.3972" y2="39.4208" width="0.1524" layer="16"/>
|
||||
<wire x1="35.5854" y1="38.862" x2="36.9062" y2="40.1828" width="0.1524" layer="16"/>
|
||||
<wire x1="35.5854" y1="38.862" x2="28.956" y2="38.862" width="0.1524" layer="16"/>
|
||||
<wire x1="28.956" y1="38.862" x2="28.3972" y2="39.4208" width="0.1524" layer="16"/>
|
||||
<wire x1="28.3972" y1="39.4208" x2="19.812" y2="39.4208" width="0.1524" layer="16"/>
|
||||
<wire x1="19.812" y1="39.4208" x2="19.812" y2="36.4236" width="0.1524" layer="1"/>
|
||||
<wire x1="19.812" y1="36.4236" x2="21.6408" y2="34.5948" width="0.1524" layer="1"/>
|
||||
|
|
@ -4999,10 +4994,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<signal name="R/W">
|
||||
<contactref element="IC1" pad="L03"/>
|
||||
<contactref element="IC3" pad="28"/>
|
||||
<wire x1="66.7004" y1="33.6296" x2="69.4944" y2="36.4236" width="0.1524" layer="1"/>
|
||||
<wire x1="69.4944" y1="36.4236" x2="69.4944" y2="43.4848" width="0.1524" layer="1"/>
|
||||
<wire x1="69.4944" y1="43.4848" x2="69.6468" y2="43.6372" width="0.1524" layer="1"/>
|
||||
<wire x1="69.6468" y1="43.6372" x2="69.6468" y2="44.196" width="0.1524" layer="1"/>
|
||||
<wire x1="66.7004" y1="33.6296" x2="69.6468" y2="36.576" width="0.1524" layer="1"/>
|
||||
<wire x1="69.6468" y1="36.576" x2="69.6468" y2="44.196" width="0.1524" layer="1"/>
|
||||
<wire x1="69.6468" y1="44.196" x2="69.1896" y2="44.6532" width="0.1524" layer="1"/>
|
||||
<wire x1="69.1896" y1="44.6532" x2="69.1896" y2="46.9392" width="0.1524" layer="1"/>
|
||||
<wire x1="69.1896" y1="46.9392" x2="69.6468" y2="47.3964" width="0.1524" layer="1"/>
|
||||
|
|
@ -5094,9 +5087,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="23.2918" y1="37.8206" x2="23.1648" y2="37.9476" width="0.4064" layer="1"/>
|
||||
<wire x1="23.1648" y1="37.9476" x2="23.1648" y2="41.7576" width="0.4064" layer="1"/>
|
||||
<via x="23.1648" y="41.7576" extent="1-16" drill="0.3"/>
|
||||
<wire x1="23.1648" y1="41.7576" x2="41.7576" y2="41.7576" width="0.4064" layer="16"/>
|
||||
<wire x1="41.7576" y1="41.7576" x2="43.7388" y2="43.7388" width="0.4064" layer="16"/>
|
||||
<wire x1="43.7388" y1="43.7388" x2="50.7492" y2="43.7388" width="0.4064" layer="16"/>
|
||||
<wire x1="23.1648" y1="41.7576" x2="41.4528" y2="41.7576" width="0.4064" layer="16"/>
|
||||
<wire x1="41.4528" y1="41.7576" x2="43.434" y2="43.7388" width="0.4064" layer="16"/>
|
||||
<wire x1="43.434" y1="43.7388" x2="50.7492" y2="43.7388" width="0.4064" layer="16"/>
|
||||
<via x="50.7492" y="43.7388" extent="1-16" drill="0.3"/>
|
||||
<wire x1="50.7492" y1="43.7388" x2="50.7492" y2="58.5216" width="0.4064" layer="1"/>
|
||||
<via x="50.7492" y="58.5216" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -5423,11 +5416,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="79.756" y="39.624" extent="1-16" drill="0.3"/>
|
||||
<wire x1="79.756" y1="39.624" x2="79.7052" y2="39.6748" width="0.1524" layer="1"/>
|
||||
<wire x1="79.7052" y1="39.6748" x2="79.7052" y2="56.0832" width="0.1524" layer="1"/>
|
||||
<wire x1="79.7052" y1="56.0832" x2="79.7052" y2="60.96" width="0.1524" layer="1"/>
|
||||
<contactref element="IC7" pad="21"/>
|
||||
<wire x1="79.7052" y1="60.96" x2="70.1548" y2="70.5104" width="0.1524" layer="1"/>
|
||||
<wire x1="70.1548" y1="70.5104" x2="70.1548" y2="85.9536" width="0.1524" layer="1"/>
|
||||
<wire x1="70.1548" y1="85.9536" x2="65.2912" y2="90.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="79.7052" y1="56.0832" x2="71.374" y2="64.4144" width="0.1524" layer="1"/>
|
||||
<wire x1="71.374" y1="64.4144" x2="71.374" y2="84.7344" width="0.1524" layer="1"/>
|
||||
<wire x1="71.374" y1="84.7344" x2="65.2912" y2="90.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="65.2912" y1="90.8172" x2="51.7896" y2="90.8172" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="A12"/>
|
||||
<contactref element="IC1" pad="B02"/>
|
||||
|
|
@ -5555,9 +5547,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="30.3022" y1="39.1668" x2="29.2862" y2="40.1828" width="0.1524" layer="16"/>
|
||||
<wire x1="43.8912" y1="87.3252" x2="44.958" y2="88.392" width="0.1524" layer="16"/>
|
||||
<wire x1="44.958" y1="88.392" x2="68.58" y2="88.392" width="0.1524" layer="16"/>
|
||||
<wire x1="70.5612" y1="86.4108" x2="70.5612" y2="70.866" width="0.1524" layer="1"/>
|
||||
<wire x1="70.5612" y1="70.866" x2="80.9244" y2="60.5028" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="60.5028" x2="80.9244" y2="48.1584" width="0.1524" layer="1"/>
|
||||
<wire x1="71.9328" y1="85.0392" x2="71.9328" y2="64.9224" width="0.1524" layer="1"/>
|
||||
<wire x1="71.9328" y1="64.9224" x2="80.9244" y2="55.9308" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="55.9308" x2="80.9244" y2="48.1584" width="0.1524" layer="1"/>
|
||||
<wire x1="80.9244" y1="48.1584" x2="80.772" y2="48.006" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="48.006" x2="80.772" y2="47.0916" width="0.1524" layer="1"/>
|
||||
<wire x1="80.772" y1="47.0916" x2="80.9244" y2="46.9392" width="0.1524" layer="1"/>
|
||||
|
|
@ -5589,7 +5581,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="36.8808" y1="73.6092" x2="36.4608" y2="73.6092" width="0.1524" layer="1"/>
|
||||
<wire x1="36.4608" y1="73.6092" x2="36.4236" y2="73.572" width="0.1524" layer="1"/>
|
||||
<via x="68.58" y="88.392" extent="1-16" drill="0.3"/>
|
||||
<wire x1="68.58" y1="88.392" x2="70.5612" y2="86.4108" width="0.1524" layer="1"/>
|
||||
<wire x1="68.58" y1="88.392" x2="71.9328" y2="85.0392" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="CIOUT">
|
||||
<contactref element="IC1" pad="C02"/>
|
||||
|
|
@ -6011,14 +6003,13 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="70.2056" y="68.2752" extent="1-16" drill="0.3"/>
|
||||
<contactref element="IC7" pad="19"/>
|
||||
<wire x1="51.7896" y1="89.8172" x2="65.1228" y2="89.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="65.1228" y1="89.8172" x2="69.2912" y2="85.6488" width="0.1524" layer="1"/>
|
||||
<wire x1="69.2912" y1="85.6488" x2="69.2912" y2="69.1896" width="0.1524" layer="1"/>
|
||||
<wire x1="69.2912" y1="69.1896" x2="70.2056" y2="68.2752" width="0.1524" layer="1"/>
|
||||
<wire x1="65.1228" y1="89.8172" x2="70.2056" y2="84.7344" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="C24"/>
|
||||
<contactref element="RN1" pad="2"/>
|
||||
<wire x1="80.023" y1="71.228" x2="80.7784" y2="71.228" width="0.1524" layer="1"/>
|
||||
<wire x1="80.7784" y1="71.228" x2="81.3816" y2="71.8312" width="0.1524" layer="1"/>
|
||||
<wire x1="81.3816" y1="71.8312" x2="82.55" y2="71.8312" width="0.1524" layer="1"/>
|
||||
<wire x1="70.2056" y1="68.2752" x2="70.2056" y2="84.7344" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="A25">
|
||||
<contactref element="IC1" pad="B06"/>
|
||||
|
|
@ -6034,15 +6025,14 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="69.4944" y="67.6656" extent="1-16" drill="0.3"/>
|
||||
<contactref element="IC7" pad="18"/>
|
||||
<wire x1="65.0132" y1="89.3172" x2="51.7896" y2="89.3172" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0132" y1="89.3172" x2="68.7832" y2="85.5472" width="0.1524" layer="1"/>
|
||||
<wire x1="68.7832" y1="85.5472" x2="68.7832" y2="68.3768" width="0.1524" layer="1"/>
|
||||
<wire x1="68.7832" y1="68.3768" x2="69.4944" y2="67.6656" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="B24"/>
|
||||
<contactref element="RN1" pad="3"/>
|
||||
<wire x1="80.023" y1="72.028" x2="80.7148" y2="72.028" width="0.1524" layer="1"/>
|
||||
<wire x1="80.7148" y1="72.028" x2="81.534" y2="72.8472" width="0.1524" layer="1"/>
|
||||
<wire x1="81.534" y1="72.8472" x2="84.074" y2="72.8472" width="0.1524" layer="1"/>
|
||||
<wire x1="84.074" y1="72.8472" x2="85.09" y2="71.8312" width="0.1524" layer="1"/>
|
||||
<wire x1="69.4944" y1="84.836" x2="69.4944" y2="67.6656" width="0.1524" layer="1"/>
|
||||
<wire x1="69.4944" y1="84.836" x2="65.0132" y2="89.3172" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="A26">
|
||||
<contactref element="IC1" pad="A05"/>
|
||||
|
|
@ -6054,9 +6044,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="68.834" y="67.056" extent="1-16" drill="0.3"/>
|
||||
<contactref element="IC7" pad="17"/>
|
||||
<wire x1="64.7512" y1="88.8172" x2="51.7896" y2="88.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="68.834" y1="67.056" x2="68.326" y2="67.564" width="0.1524" layer="1"/>
|
||||
<wire x1="68.326" y1="67.564" x2="68.326" y2="85.2424" width="0.1524" layer="1"/>
|
||||
<wire x1="68.326" y1="85.2424" x2="64.7512" y2="88.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="68.834" y1="84.7344" x2="64.7512" y2="88.8172" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="A24"/>
|
||||
<wire x1="41.148" y1="67.056" x2="40.6908" y2="67.5132" width="0.1524" layer="16"/>
|
||||
<wire x1="40.6908" y1="67.5132" x2="39.7764" y2="67.5132" width="0.1524" layer="16"/>
|
||||
|
|
@ -6067,6 +6055,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="80.7528" y1="72.828" x2="81.2292" y2="73.3044" width="0.1524" layer="1"/>
|
||||
<wire x1="81.2292" y1="73.3044" x2="86.1568" y2="73.3044" width="0.1524" layer="1"/>
|
||||
<wire x1="86.1568" y1="73.3044" x2="87.63" y2="71.8312" width="0.1524" layer="1"/>
|
||||
<wire x1="68.834" y1="84.7344" x2="68.834" y2="67.056" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="A28">
|
||||
<contactref element="IC1" pad="A04"/>
|
||||
|
|
@ -6080,16 +6069,15 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="67.564" y="65.7352" extent="1-16" drill="0.3"/>
|
||||
<contactref element="IC7" pad="15"/>
|
||||
<wire x1="51.7896" y1="87.8172" x2="64.532" y2="87.8172" width="0.1524" layer="1"/>
|
||||
<wire x1="64.532" y1="87.8172" x2="67.31" y2="85.0392" width="0.1524" layer="1"/>
|
||||
<wire x1="67.31" y1="85.0392" x2="67.31" y2="65.9892" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="B23"/>
|
||||
<wire x1="67.31" y1="65.9892" x2="67.564" y2="65.7352" width="0.1524" layer="1"/>
|
||||
<contactref element="RN2" pad="4"/>
|
||||
<wire x1="80.023" y1="69.3228" x2="80.448" y2="69.3228" width="0.1524" layer="1"/>
|
||||
<wire x1="80.448" y1="69.3228" x2="81.534" y2="70.4088" width="0.1524" layer="1"/>
|
||||
<wire x1="81.534" y1="70.4088" x2="83.9724" y2="70.4088" width="0.1524" layer="1"/>
|
||||
<wire x1="83.9724" y1="70.4088" x2="85.09" y2="69.2912" width="0.1524" layer="1"/>
|
||||
<wire x1="67.564" y1="65.7352" x2="72.4408" y2="65.7352" width="0.1524" layer="16"/>
|
||||
<wire x1="64.532" y1="87.8172" x2="67.564" y2="84.7852" width="0.1524" layer="1"/>
|
||||
<wire x1="67.564" y1="84.7852" x2="67.564" y2="65.7352" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="A29">
|
||||
<contactref element="IC1" pad="B04"/>
|
||||
|
|
@ -6146,9 +6134,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="85.09" y1="66.7512" x2="83.8708" y2="65.532" width="0.1524" layer="16"/>
|
||||
<wire x1="83.8708" y1="65.532" x2="74.0664" y2="65.532" width="0.1524" layer="16"/>
|
||||
<wire x1="74.0664" y1="65.532" x2="71.4756" y2="62.9412" width="0.1524" layer="16"/>
|
||||
<wire x1="71.4756" y1="62.9412" x2="63.3984" y2="62.9412" width="0.1524" layer="16"/>
|
||||
<wire x1="63.3984" y1="62.9412" x2="62.992" y2="62.5348" width="0.1524" layer="16"/>
|
||||
<wire x1="62.992" y1="62.5348" x2="61.976" y2="62.5348" width="0.1524" layer="16"/>
|
||||
<wire x1="71.4756" y1="62.9412" x2="62.3824" y2="62.9412" width="0.1524" layer="16"/>
|
||||
<wire x1="62.3824" y1="62.9412" x2="61.976" y2="62.5348" width="0.1524" layer="16"/>
|
||||
<wire x1="61.976" y1="62.5348" x2="61.468" y2="62.0268" width="0.1524" layer="16"/>
|
||||
<wire x1="61.468" y1="62.0268" x2="41.6052" y2="62.0268" width="0.1524" layer="16"/>
|
||||
<wire x1="40.9956" y1="62.6364" x2="40.386" y2="62.6364" width="0.1524" layer="16"/>
|
||||
|
|
@ -6180,8 +6167,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<contactref element="IC7" pad="78"/>
|
||||
<wire x1="38.7896" y1="78.8172" x2="38.7896" y2="69.1172" width="0.1524" layer="1"/>
|
||||
<wire x1="38.7896" y1="69.1172" x2="38.2524" y2="68.58" width="0.1524" layer="1"/>
|
||||
<wire x1="38.2524" y1="68.58" x2="38.2524" y2="36.8808" width="0.1524" layer="1"/>
|
||||
<wire x1="38.2524" y1="36.8808" x2="37.8968" y2="36.5252" width="0.1524" layer="1"/>
|
||||
<wire x1="38.2524" y1="68.58" x2="38.2524" y2="37.6428" width="0.1524" layer="1"/>
|
||||
<via x="36.1188" y="31.5468" extent="1-16" drill="0.3"/>
|
||||
<wire x1="36.1188" y1="31.5468" x2="36.1188" y2="31.242" width="0.1524" layer="16"/>
|
||||
<via x="37.338" y="26.8224" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6189,9 +6175,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="36.7284" y1="30.6324" x2="36.7284" y2="27.432" width="0.1524" layer="16"/>
|
||||
<wire x1="36.7284" y1="27.432" x2="37.338" y2="26.8224" width="0.1524" layer="16"/>
|
||||
<wire x1="36.1188" y1="31.5468" x2="35.9664" y2="31.6992" width="0.1524" layer="1"/>
|
||||
<wire x1="35.9664" y1="31.6992" x2="35.9664" y2="35.6616" width="0.1524" layer="1"/>
|
||||
<wire x1="35.9664" y1="35.6616" x2="36.83" y2="36.5252" width="0.1524" layer="1"/>
|
||||
<wire x1="36.83" y1="36.5252" x2="37.8968" y2="36.5252" width="0.1524" layer="1"/>
|
||||
<wire x1="35.9664" y1="31.6992" x2="35.9664" y2="35.3568" width="0.1524" layer="1"/>
|
||||
<wire x1="35.9664" y1="35.3568" x2="38.2524" y2="37.6428" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="VCC">
|
||||
<contactref element="IC3" pad="18"/>
|
||||
|
|
@ -6648,8 +6633,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="65.4304" y="55.3212" extent="1-16" drill="0.3"/>
|
||||
<via x="60.7568" y="86.5124" extent="1-16" drill="0.3"/>
|
||||
<via x="46.5328" y="84.4804" extent="1-16" drill="0.3"/>
|
||||
<via x="72.0852" y="84.328" extent="1-16" drill="0.3"/>
|
||||
<via x="78.8416" y="57.0484" extent="1-16" drill="0.3"/>
|
||||
<via x="72.6948" y="84.328" extent="1-16" drill="0.3"/>
|
||||
<via x="77.6224" y="57.0484" extent="1-16" drill="0.3"/>
|
||||
<via x="63.1952" y="17.1704" extent="1-16" drill="0.3"/>
|
||||
<contactref element="C10" pad="2"/>
|
||||
<contactref element="C11" pad="2"/>
|
||||
|
|
@ -6741,7 +6726,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="42.4688" y="14.1224" extent="1-16" drill="0.3"/>
|
||||
<via x="47.4472" y="57.9628" extent="1-16" drill="0.3"/>
|
||||
<via x="48.3616" y="57.9628" extent="1-16" drill="0.3"/>
|
||||
<via x="70.612" y="60.8076" extent="1-16" drill="0.3"/>
|
||||
<via x="67.8688" y="60.8076" extent="1-16" drill="0.3"/>
|
||||
<via x="77.1906" y="39.5224" extent="1-16" drill="0.3"/>
|
||||
<wire x1="47.5742" y1="55.1294" x2="47.766" y2="55.3212" width="0.6096" layer="1"/>
|
||||
<wire x1="47.766" y1="55.3212" x2="48.8696" y2="55.3212" width="0.6096" layer="1"/>
|
||||
|
|
@ -6852,7 +6837,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="10.922" y="77.3684" extent="1-16" drill="0.3"/>
|
||||
<via x="10.7696" y="68.6816" extent="1-16" drill="0.3"/>
|
||||
<via x="10.16" y="41.2496" extent="1-16" drill="0.3"/>
|
||||
<via x="10.3886" y="24.7142" extent="1-16" drill="0.3"/>
|
||||
<via x="9.9314" y="24.7142" extent="1-16" drill="0.3"/>
|
||||
<via x="10.3124" y="13.8176" extent="1-16" drill="0.3"/>
|
||||
<via x="10.3124" y="16.8656" extent="1-16" drill="0.3"/>
|
||||
<via x="10.3124" y="12.1412" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6968,7 +6953,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="36.9824" y="55.4228" extent="1-16" drill="0.3"/>
|
||||
<via x="36.9824" y="50.2412" extent="1-16" drill="0.3"/>
|
||||
<via x="72.5932" y="60.8076" extent="1-16" drill="0.3"/>
|
||||
<via x="73.66" y="61.8744" extent="1-16" drill="0.3"/>
|
||||
<via x="73.2028" y="61.4172" extent="1-16" drill="0.3"/>
|
||||
<via x="76.5556" y="56.9976" extent="1-16" drill="0.3"/>
|
||||
<via x="48.8188" y="47.3964" extent="1-16" drill="0.3"/>
|
||||
<via x="78.867" y="46.6344" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6981,17 +6966,17 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="75.8952" y1="68.707" x2="78.473" y2="68.5228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="75.5904" y1="67.2846" x2="75.8952" y2="68.707" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="74.3204" y1="94.3102" x2="76.13" y2="90.354" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.0852" y1="84.328" x2="75.7428" y2="88.4428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="73.66" y1="61.8744" x2="75.5904" y2="67.2846" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.5932" y1="60.8076" x2="73.66" y2="61.8744" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="70.612" y1="60.8076" x2="72.5932" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="69.7484" y1="58.42" x2="70.612" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.6948" y1="84.328" x2="75.7428" y2="88.4428" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="73.2028" y1="61.4172" x2="75.5904" y2="67.2846" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="72.5932" y1="60.8076" x2="73.2028" y2="61.4172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.8688" y1="60.8076" x2="72.5932" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="69.7484" y1="58.42" x2="67.8688" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.4304" y1="55.3212" x2="69.7484" y2="58.42" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.8396" y1="55.372" x2="65.4304" y2="55.3212" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="58.0136" x2="62.8396" y2="55.372" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.5556" y1="56.9976" x2="72.5932" y2="60.8076" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="78.8416" y1="57.0484" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.4116" y1="90.5256" x2="72.0852" y2="84.328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.6224" y1="57.0484" x2="76.5556" y2="56.9976" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.4116" y1="90.5256" x2="72.6948" y2="84.328" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.1604" y1="94.3102" x2="67.4116" y2="90.5256" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="61.6712" y1="97.3836" x2="64.1604" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="95.6564" x2="61.6712" y2="97.3836" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7100,11 +7085,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="16.764" y1="52.2732" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="53.594" x2="15.24" y2="52.197" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.8808" y1="67.5132" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3886" y1="24.7142" x2="15.3924" y2="30.4038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.9314" y1="24.7142" x2="15.3924" y2="30.4038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="5.0686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.2356" y1="3.7592" x2="52.6034" y2="3.683" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="3.7592" x2="56.2356" y2="3.7592" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="16.8656" x2="10.3886" y2="24.7142" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="16.8656" x2="9.9314" y2="24.7142" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="13.8176" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="12.1412" x2="10.3124" y2="13.8176" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.1234" y1="17.2212" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7184,14 +7169,13 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="68.1736" y="66.4464" extent="1-16" drill="0.3"/>
|
||||
<contactref element="IC7" pad="16"/>
|
||||
<wire x1="64.6416" y1="88.3172" x2="51.7896" y2="88.3172" width="0.1524" layer="1"/>
|
||||
<wire x1="64.6416" y1="88.3172" x2="67.9196" y2="85.0392" width="0.1524" layer="1"/>
|
||||
<wire x1="67.9196" y1="85.0392" x2="67.9196" y2="66.7004" width="0.1524" layer="1"/>
|
||||
<wire x1="67.9196" y1="66.7004" x2="68.1736" y2="66.4464" width="0.1524" layer="1"/>
|
||||
<contactref element="X1" pad="C23"/>
|
||||
<contactref element="RN2" pad="3"/>
|
||||
<wire x1="80.023" y1="68.5228" x2="80.4608" y2="68.5228" width="0.1524" layer="1"/>
|
||||
<wire x1="80.4608" y1="68.5228" x2="81.2292" y2="69.2912" width="0.1524" layer="1"/>
|
||||
<wire x1="81.2292" y1="69.2912" x2="82.55" y2="69.2912" width="0.1524" layer="1"/>
|
||||
<wire x1="64.6416" y1="88.3172" x2="68.1736" y2="84.7852" width="0.1524" layer="1"/>
|
||||
<wire x1="68.1736" y1="84.7852" x2="68.1736" y2="66.4464" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="OSZI_OUT">
|
||||
<contactref element="QG1" pad="8"/>
|
||||
|
|
@ -7206,13 +7190,13 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="76.8096" y1="28.3464" x2="78.0288" y2="29.5656" width="0.1524" layer="1"/>
|
||||
<wire x1="78.0288" y1="29.5656" x2="78.0288" y2="43.1292" width="0.1524" layer="1"/>
|
||||
<contactref element="IC7" pad="20"/>
|
||||
<wire x1="78.0288" y1="61.8744" x2="69.7484" y2="70.1548" width="0.1524" layer="1"/>
|
||||
<wire x1="69.7484" y1="70.1548" x2="69.7484" y2="85.8012" width="0.1524" layer="1"/>
|
||||
<wire x1="69.7484" y1="85.8012" x2="65.2324" y2="90.3172" width="0.1524" layer="1"/>
|
||||
<wire x1="78.0288" y1="54.5592" x2="70.8152" y2="61.7728" width="0.1524" layer="1"/>
|
||||
<wire x1="70.8152" y1="61.7728" x2="70.8152" y2="84.7344" width="0.1524" layer="1"/>
|
||||
<wire x1="70.8152" y1="84.7344" x2="65.2324" y2="90.3172" width="0.1524" layer="1"/>
|
||||
<wire x1="65.2324" y1="90.3172" x2="51.7896" y2="90.3172" width="0.1524" layer="1"/>
|
||||
<wire x1="75.3872" y1="43.3832" x2="77.7748" y2="43.3832" width="0.1524" layer="1"/>
|
||||
<wire x1="77.7748" y1="43.3832" x2="78.0288" y2="43.1292" width="0.1524" layer="1"/>
|
||||
<wire x1="78.0288" y1="61.8744" x2="78.0288" y2="43.6372" width="0.1524" layer="1"/>
|
||||
<wire x1="78.0288" y1="54.5592" x2="78.0288" y2="43.6372" width="0.1524" layer="1"/>
|
||||
<wire x1="78.0288" y1="43.6372" x2="77.7748" y2="43.3832" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="TCK">
|
||||
|
|
@ -7458,18 +7442,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="63.0936" y1="44.196" x2="60.8076" y2="44.196" width="0.1524" layer="16"/>
|
||||
<wire x1="60.8076" y1="44.196" x2="60.5028" y2="43.8912" width="0.1524" layer="16"/>
|
||||
<wire x1="51.9684" y1="43.8912" x2="51.2064" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<wire x1="51.2064" y1="43.1292" x2="43.7642" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<wire x1="43.7642" y1="43.1292" x2="41.6306" y2="40.9956" width="0.1524" layer="16"/>
|
||||
<wire x1="51.2064" y1="43.1292" x2="43.6118" y2="43.1292" width="0.1524" layer="16"/>
|
||||
<via x="12.8016" y="38.7096" extent="1-16" drill="0.3"/>
|
||||
<wire x1="41.6306" y1="40.9956" x2="40.9956" y2="40.9956" width="0.1524" layer="16"/>
|
||||
<wire x1="40.9956" y1="40.9956" x2="40.6908" y2="40.6908" width="0.1524" layer="16"/>
|
||||
<wire x1="40.6908" y1="40.6908" x2="40.6908" y2="36.7284" width="0.1524" layer="16"/>
|
||||
<wire x1="40.6908" y1="36.7284" x2="40.386" y2="36.4236" width="0.1524" layer="16"/>
|
||||
<wire x1="40.386" y1="36.4236" x2="36.576" y2="36.4236" width="0.1524" layer="16"/>
|
||||
<wire x1="36.576" y1="36.4236" x2="35.6616" y2="37.338" width="0.1524" layer="16"/>
|
||||
<wire x1="35.6616" y1="37.338" x2="35.6616" y2="37.6428" width="0.1524" layer="16"/>
|
||||
<wire x1="35.6616" y1="37.6428" x2="34.7472" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="34.7472" y1="38.5572" x2="28.6512" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="39.0398" y1="38.5572" x2="28.6512" y2="38.5572" width="0.1524" layer="16"/>
|
||||
<wire x1="28.6512" y1="38.5572" x2="28.4988" y2="38.7096" width="0.1524" layer="16"/>
|
||||
<wire x1="28.4988" y1="38.7096" x2="12.8016" y2="38.7096" width="0.1524" layer="16"/>
|
||||
<wire x1="65.3288" y1="29.6164" x2="65.4304" y2="29.718" width="0.1524" layer="1"/>
|
||||
|
|
@ -7482,6 +7457,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="69.9516" y1="46.482" x2="65.6844" y2="46.482" width="0.1524" layer="16"/>
|
||||
<wire x1="65.6844" y1="46.482" x2="65.2272" y2="46.0248" width="0.1524" layer="16"/>
|
||||
<wire x1="51.9684" y1="43.8912" x2="60.5028" y2="43.8912" width="0.1524" layer="16"/>
|
||||
<wire x1="43.6118" y1="43.1292" x2="39.0398" y2="38.5572" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="R/W_00">
|
||||
<contactref element="IC2" pad="9"/>
|
||||
|
|
@ -7500,11 +7476,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="22.5552" y1="43.5864" x2="23.1648" y2="44.196" width="0.1524" layer="16"/>
|
||||
<wire x1="23.1648" y1="44.196" x2="25.908" y2="44.196" width="0.1524" layer="16"/>
|
||||
<wire x1="25.908" y1="44.196" x2="28.6512" y2="46.9392" width="0.1524" layer="16"/>
|
||||
<wire x1="28.6512" y1="46.9392" x2="30.3276" y2="46.9392" width="0.1524" layer="16"/>
|
||||
<wire x1="30.3276" y1="46.9392" x2="30.6324" y2="47.244" width="0.1524" layer="16"/>
|
||||
<wire x1="30.6324" y1="47.244" x2="30.6324" y2="48.006" width="0.1524" layer="16"/>
|
||||
<wire x1="30.6324" y1="48.006" x2="31.3944" y2="48.768" width="0.1524" layer="16"/>
|
||||
<wire x1="31.3944" y1="48.768" x2="37.4904" y2="48.768" width="0.1524" layer="16"/>
|
||||
<wire x1="28.6512" y1="46.9392" x2="29.718" y2="46.9392" width="0.1524" layer="16"/>
|
||||
<wire x1="29.718" y1="46.9392" x2="31.5468" y2="48.768" width="0.1524" layer="16"/>
|
||||
<wire x1="31.5468" y1="48.768" x2="37.4904" y2="48.768" width="0.1524" layer="16"/>
|
||||
<wire x1="37.4904" y1="48.768" x2="37.7952" y2="48.4632" width="0.1524" layer="16"/>
|
||||
<wire x1="37.7952" y1="48.4632" x2="38.862" y2="48.4632" width="0.1524" layer="16"/>
|
||||
<via x="38.862" y="48.4632" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -7934,7 +7908,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="6.858" y="21.4884" extent="1-16" drill="0.3"/>
|
||||
<wire x1="6.858" y1="21.4884" x2="4.8768" y2="21.4884" width="0.1524" layer="16"/>
|
||||
<wire x1="4.8768" y1="21.4884" x2="4.4196" y2="21.0312" width="0.1524" layer="16"/>
|
||||
<wire x1="4.4196" y1="21.0312" x2="4.4196" y2="14.3256" width="0.1524" layer="16"/>
|
||||
<wire x1="4.4196" y1="21.0312" x2="4.4196" y2="12.3698" width="0.1524" layer="16"/>
|
||||
<contactref element="IC6" pad="18"/>
|
||||
<wire x1="75.3872" y1="27.0764" x2="72.7964" y2="27.0764" width="0.1524" layer="1"/>
|
||||
<wire x1="72.7964" y1="27.0764" x2="71.4756" y2="25.7556" width="0.1524" layer="1"/>
|
||||
|
|
@ -7947,9 +7921,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="26.0604" y1="16.002" x2="17.8308" y2="16.002" width="0.1524" layer="16"/>
|
||||
<wire x1="17.8308" y1="16.002" x2="12.3444" y2="21.4884" width="0.1524" layer="16"/>
|
||||
<wire x1="12.3444" y1="21.4884" x2="6.858" y2="21.4884" width="0.1524" layer="16"/>
|
||||
<wire x1="4.4196" y1="14.3256" x2="3.5052" y2="13.4112" width="0.1524" layer="16"/>
|
||||
<wire x1="3.5052" y1="13.4112" x2="3.5052" y2="11.4554" width="0.1524" layer="16"/>
|
||||
<wire x1="3.5052" y1="11.4554" x2="1.9304" y2="9.8806" width="0.1524" layer="16"/>
|
||||
<wire x1="4.4196" y1="12.3698" x2="1.9304" y2="9.8806" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="AMIGA_D9">
|
||||
<contactref element="IC2" pad="60"/>
|
||||
|
|
@ -7972,10 +7944,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="38.7096" y1="17.526" x2="27.1272" y2="17.526" width="0.1524" layer="16"/>
|
||||
<wire x1="27.1272" y1="17.526" x2="25.908" y2="16.3068" width="0.1524" layer="16"/>
|
||||
<wire x1="25.908" y1="16.3068" x2="18.288" y2="16.3068" width="0.1524" layer="16"/>
|
||||
<wire x1="18.288" y1="16.3068" x2="12.8016" y2="21.7932" width="0.1524" layer="16"/>
|
||||
<wire x1="12.8016" y1="21.7932" x2="12.8016" y2="22.4028" width="0.1524" layer="16"/>
|
||||
<wire x1="12.8016" y1="22.4028" x2="12.4968" y2="22.7076" width="0.1524" layer="16"/>
|
||||
<wire x1="12.4968" y1="22.7076" x2="6.858" y2="22.7076" width="0.1524" layer="16"/>
|
||||
<wire x1="18.288" y1="16.3068" x2="11.8872" y2="22.7076" width="0.1524" layer="16"/>
|
||||
<wire x1="11.8872" y1="22.7076" x2="6.858" y2="22.7076" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="AMIGA_D10">
|
||||
<contactref element="IC2" pad="59"/>
|
||||
|
|
@ -7998,10 +7968,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="38.7096" y1="17.9832" x2="27.1272" y2="17.9832" width="0.1524" layer="16"/>
|
||||
<wire x1="27.1272" y1="17.9832" x2="25.7556" y2="16.6116" width="0.1524" layer="16"/>
|
||||
<wire x1="25.7556" y1="16.6116" x2="18.5928" y2="16.6116" width="0.1524" layer="16"/>
|
||||
<wire x1="18.5928" y1="16.6116" x2="13.4112" y2="21.7932" width="0.1524" layer="16"/>
|
||||
<wire x1="13.4112" y1="21.7932" x2="13.4112" y2="23.7744" width="0.1524" layer="16"/>
|
||||
<wire x1="13.4112" y1="23.7744" x2="13.1064" y2="24.0792" width="0.1524" layer="16"/>
|
||||
<wire x1="13.1064" y1="24.0792" x2="6.858" y2="24.0792" width="0.1524" layer="16"/>
|
||||
<wire x1="18.5928" y1="16.6116" x2="11.1252" y2="24.0792" width="0.1524" layer="16"/>
|
||||
<wire x1="11.1252" y1="24.0792" x2="6.858" y2="24.0792" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="AMIGA_D11">
|
||||
<contactref element="IC2" pad="58"/>
|
||||
|
|
@ -8023,10 +7991,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="38.4048" y1="18.288" x2="26.3652" y2="18.288" width="0.1524" layer="16"/>
|
||||
<wire x1="26.3652" y1="18.288" x2="26.2128" y2="18.4404" width="0.1524" layer="16"/>
|
||||
<wire x1="26.2128" y1="18.4404" x2="17.3736" y2="18.4404" width="0.1524" layer="16"/>
|
||||
<wire x1="17.3736" y1="18.4404" x2="13.8684" y2="21.9456" width="0.1524" layer="16"/>
|
||||
<wire x1="13.8684" y1="21.9456" x2="13.8684" y2="24.8412" width="0.1524" layer="16"/>
|
||||
<wire x1="13.8684" y1="24.8412" x2="13.4112" y2="25.2984" width="0.1524" layer="16"/>
|
||||
<wire x1="13.4112" y1="25.2984" x2="6.858" y2="25.2984" width="0.1524" layer="16"/>
|
||||
<wire x1="17.3736" y1="18.4404" x2="10.5156" y2="25.2984" width="0.1524" layer="16"/>
|
||||
<wire x1="10.5156" y1="25.2984" x2="6.858" y2="25.2984" width="0.1524" layer="16"/>
|
||||
</signal>
|
||||
<signal name="AMIGA_D12">
|
||||
<contactref element="IC2" pad="57"/>
|
||||
|
|
@ -8040,21 +8006,17 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<contactref element="IC6" pad="14"/>
|
||||
<wire x1="70.7136" y1="21.4884" x2="70.7136" y2="24.2316" width="0.1524" layer="1"/>
|
||||
<via x="70.7136" y="24.2316" extent="1-16" drill="0.3"/>
|
||||
<wire x1="70.7136" y1="24.2316" x2="41.91" y2="24.2316" width="0.1524" layer="16"/>
|
||||
<wire x1="41.91" y1="24.2316" x2="37.0332" y2="19.3548" width="0.1524" layer="16"/>
|
||||
<wire x1="37.0332" y1="19.3548" x2="36.4236" y2="19.3548" width="0.1524" layer="16"/>
|
||||
<wire x1="36.4236" y1="19.3548" x2="36.1188" y2="19.6596" width="0.1524" layer="16"/>
|
||||
<wire x1="36.1188" y1="19.6596" x2="30.7848" y2="19.6596" width="0.1524" layer="16"/>
|
||||
<wire x1="30.7848" y1="19.6596" x2="30.3276" y2="20.1168" width="0.1524" layer="16"/>
|
||||
<wire x1="30.3276" y1="20.1168" x2="26.8224" y2="20.1168" width="0.1524" layer="16"/>
|
||||
<wire x1="26.8224" y1="20.1168" x2="25.908" y2="19.2024" width="0.1524" layer="16"/>
|
||||
<wire x1="25.908" y1="19.2024" x2="19.05" y2="19.2024" width="0.1524" layer="16"/>
|
||||
<wire x1="70.7136" y1="24.2316" x2="42.0624" y2="24.2316" width="0.1524" layer="16"/>
|
||||
<wire x1="42.0624" y1="24.2316" x2="37.1856" y2="19.3548" width="0.1524" layer="16"/>
|
||||
<wire x1="37.1856" y1="19.3548" x2="29.8704" y2="19.3548" width="0.1524" layer="16"/>
|
||||
<wire x1="29.8704" y1="19.3548" x2="29.1084" y2="20.1168" width="0.1524" layer="16"/>
|
||||
<wire x1="29.1084" y1="20.1168" x2="28.4988" y2="20.1168" width="0.1524" layer="16"/>
|
||||
<wire x1="28.4988" y1="20.1168" x2="27.5844" y2="19.2024" width="0.1524" layer="16"/>
|
||||
<wire x1="27.5844" y1="19.2024" x2="19.05" y2="19.2024" width="0.1524" layer="16"/>
|
||||
<wire x1="19.05" y1="19.2024" x2="17.3736" y2="20.8788" width="0.1524" layer="16"/>
|
||||
<wire x1="17.3736" y1="20.8788" x2="16.6116" y2="20.8788" width="0.1524" layer="16"/>
|
||||
<wire x1="16.6116" y1="20.8788" x2="14.3256" y2="23.1648" width="0.1524" layer="16"/>
|
||||
<wire x1="14.3256" y1="23.1648" x2="14.3256" y2="25.908" width="0.1524" layer="16"/>
|
||||
<wire x1="14.3256" y1="25.908" x2="13.5636" y2="26.67" width="0.1524" layer="16"/>
|
||||
<wire x1="13.5636" y1="26.67" x2="6.858" y2="26.67" width="0.1524" layer="16"/>
|
||||
<wire x1="16.6116" y1="20.8788" x2="10.8204" y2="26.67" width="0.1524" layer="16"/>
|
||||
<wire x1="10.8204" y1="26.67" x2="6.858" y2="26.67" width="0.1524" layer="16"/>
|
||||
<via x="6.858" y="26.67" extent="1-16" drill="0.3"/>
|
||||
<wire x1="6.858" y1="26.67" x2="5.4102" y2="26.67" width="0.1524" layer="1"/>
|
||||
<wire x1="5.4102" y1="26.67" x2="5.334" y2="26.5938" width="0.1524" layer="1"/>
|
||||
|
|
@ -8086,10 +8048,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="18.8976" y1="22.86" x2="17.9832" y2="22.86" width="0.1524" layer="16"/>
|
||||
<wire x1="17.9832" y1="22.86" x2="17.526" y2="23.3172" width="0.1524" layer="16"/>
|
||||
<wire x1="17.526" y1="23.3172" x2="16.764" y2="23.3172" width="0.1524" layer="16"/>
|
||||
<wire x1="16.764" y1="23.3172" x2="14.7828" y2="25.2984" width="0.1524" layer="16"/>
|
||||
<wire x1="14.7828" y1="25.2984" x2="14.7828" y2="27.432" width="0.1524" layer="16"/>
|
||||
<wire x1="14.7828" y1="27.432" x2="14.3256" y2="27.8892" width="0.1524" layer="16"/>
|
||||
<wire x1="14.3256" y1="27.8892" x2="6.858" y2="27.8892" width="0.1524" layer="16"/>
|
||||
<wire x1="16.764" y1="23.3172" x2="12.192" y2="27.8892" width="0.1524" layer="16"/>
|
||||
<wire x1="12.192" y1="27.8892" x2="6.858" y2="27.8892" width="0.1524" layer="16"/>
|
||||
<via x="6.858" y="27.8892" extent="1-16" drill="0.3"/>
|
||||
<wire x1="6.858" y1="27.8892" x2="5.3594" y2="27.8892" width="0.1524" layer="1"/>
|
||||
<wire x1="5.3594" y1="27.8892" x2="5.334" y2="27.8638" width="0.1524" layer="1"/>
|
||||
|
|
@ -8113,10 +8073,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="23.1648" y1="23.4696" x2="18.7452" y2="23.4696" width="0.1524" layer="16"/>
|
||||
<wire x1="18.7452" y1="23.4696" x2="17.526" y2="24.6888" width="0.1524" layer="16"/>
|
||||
<wire x1="17.526" y1="24.6888" x2="16.6116" y2="24.6888" width="0.1524" layer="16"/>
|
||||
<wire x1="16.6116" y1="24.6888" x2="15.24" y2="26.0604" width="0.1524" layer="16"/>
|
||||
<wire x1="15.24" y1="26.0604" x2="15.24" y2="28.6512" width="0.1524" layer="16"/>
|
||||
<wire x1="15.24" y1="28.6512" x2="14.7828" y2="29.1084" width="0.1524" layer="16"/>
|
||||
<wire x1="14.7828" y1="29.1084" x2="6.858" y2="29.1084" width="0.1524" layer="16"/>
|
||||
<wire x1="16.6116" y1="24.6888" x2="12.192" y2="29.1084" width="0.1524" layer="16"/>
|
||||
<wire x1="12.192" y1="29.1084" x2="6.858" y2="29.1084" width="0.1524" layer="16"/>
|
||||
<via x="6.858" y="29.1084" extent="1-16" drill="0.3"/>
|
||||
<wire x1="6.858" y1="29.1084" x2="5.3594" y2="29.1084" width="0.1524" layer="1"/>
|
||||
<wire x1="5.3594" y1="29.1084" x2="5.334" y2="29.1338" width="0.1524" layer="1"/>
|
||||
|
|
@ -8140,10 +8098,8 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="22.5552" y1="25.4508" x2="21.1836" y2="25.4508" width="0.1524" layer="16"/>
|
||||
<wire x1="21.1836" y1="25.4508" x2="20.7264" y2="25.908" width="0.1524" layer="16"/>
|
||||
<wire x1="20.7264" y1="25.908" x2="16.6116" y2="25.908" width="0.1524" layer="16"/>
|
||||
<wire x1="16.6116" y1="25.908" x2="15.8496" y2="26.67" width="0.1524" layer="16"/>
|
||||
<wire x1="15.8496" y1="26.67" x2="15.8496" y2="29.8704" width="0.1524" layer="16"/>
|
||||
<wire x1="15.8496" y1="29.8704" x2="15.3924" y2="30.3276" width="0.1524" layer="16"/>
|
||||
<wire x1="15.3924" y1="30.3276" x2="6.858" y2="30.3276" width="0.1524" layer="16"/>
|
||||
<wire x1="16.6116" y1="25.908" x2="12.192" y2="30.3276" width="0.1524" layer="16"/>
|
||||
<wire x1="12.192" y1="30.3276" x2="6.858" y2="30.3276" width="0.1524" layer="16"/>
|
||||
<via x="6.858" y="30.3276" extent="1-16" drill="0.3"/>
|
||||
<wire x1="6.858" y1="30.3276" x2="5.4102" y2="30.3276" width="0.1524" layer="1"/>
|
||||
<wire x1="5.4102" y1="30.3276" x2="5.334" y2="30.4038" width="0.1524" layer="1"/>
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.4">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="yes"/>
|
||||
|
|
@ -2839,19 +2839,19 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<element name="C28" library="rcl" package="C0603K" value="100nF" x="6.096" y="69.0372" smashed="yes">
|
||||
<attribute name="NAME" x="7.8868" y="68.6204" size="0.8128" layer="25"/>
|
||||
</element>
|
||||
<element name="R10" library="rcl" package="R0603" value="" x="31.496" y="78.8162" smashed="yes" rot="R270">
|
||||
<element name="R10" library="rcl" package="R0603" value="68" x="31.496" y="78.8162" smashed="yes" rot="R270">
|
||||
<attribute name="NAME" x="29.3878" y="79.2988" size="0.8128" layer="25" rot="R270"/>
|
||||
<attribute name="VALUE" x="29.591" y="79.4512" size="1.27" layer="27" rot="R270"/>
|
||||
</element>
|
||||
<element name="R11" library="rcl" package="R0603" value="" x="30.6832" y="81.8134" smashed="yes" rot="R270">
|
||||
<element name="R11" library="rcl" package="R0603" value="68" x="30.6832" y="81.8134" smashed="yes" rot="R270">
|
||||
<attribute name="NAME" x="28.7274" y="82.9056" size="0.8128" layer="25" rot="R270"/>
|
||||
<attribute name="VALUE" x="28.7782" y="82.4484" size="1.27" layer="27" rot="R270"/>
|
||||
</element>
|
||||
<element name="R14" library="rcl" package="R0603" value="" x="58.674" y="85.6488" smashed="yes" rot="R180">
|
||||
<element name="R14" library="rcl" package="R0603" value="68" x="58.674" y="85.6488" smashed="yes" rot="R180">
|
||||
<attribute name="NAME" x="59.309" y="85.0138" size="0.8128" layer="25" rot="R180"/>
|
||||
<attribute name="VALUE" x="59.309" y="87.5538" size="1.27" layer="27" rot="R180"/>
|
||||
</element>
|
||||
<element name="R16" library="rcl" package="R0603" value="" x="25.4508" y="89.3064" smashed="yes" rot="R90">
|
||||
<element name="R16" library="rcl" package="R0603" value="10" x="25.4508" y="89.3064" smashed="yes" rot="R90">
|
||||
<attribute name="NAME" x="27.559" y="88.9762" size="1.27" layer="25" rot="R90"/>
|
||||
<attribute name="VALUE" x="27.3558" y="88.6714" size="1.27" layer="27" rot="R90"/>
|
||||
</element>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -10124,6 +10124,7 @@ Source: RS Component / Phycomp</description>
|
|||
<part name="R9" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R22" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R23" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R24" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
</parts>
|
||||
<sheets>
|
||||
<sheet>
|
||||
|
|
@ -10163,6 +10164,7 @@ Source: RS Component / Phycomp</description>
|
|||
<instance part="R9" gate="G$1" x="-2.54" y="137.16"/>
|
||||
<instance part="R22" gate="G$1" x="-2.54" y="132.08"/>
|
||||
<instance part="R23" gate="G$1" x="-2.54" y="142.24"/>
|
||||
<instance part="R24" gate="G$1" x="-25.4" y="83.82"/>
|
||||
</instances>
|
||||
<busses>
|
||||
<bus name="A[0..31]">
|
||||
|
|
@ -10994,6 +10996,11 @@ Source: RS Component / Phycomp</description>
|
|||
<wire x1="132.08" y1="111.76" x2="137.16" y2="111.76" width="0.1524" layer="91"/>
|
||||
<label x="137.16" y="111.76" size="1.27" layer="95" xref="yes"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="R24" gate="G$1" pin="1"/>
|
||||
<wire x1="-30.48" y1="83.82" x2="-33.02" y2="83.82" width="0.1524" layer="91"/>
|
||||
<label x="-33.02" y="83.82" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="STATUS" class="0">
|
||||
<segment>
|
||||
|
|
@ -11530,6 +11537,12 @@ Source: RS Component / Phycomp</description>
|
|||
<wire x1="-7.62" y1="66.04" x2="7.62" y2="66.04" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="66.04" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="R24" gate="G$1" pin="2"/>
|
||||
<wire x1="-20.32" y1="83.82" x2="-15.24" y2="83.82" width="0.1524" layer="91"/>
|
||||
<wire x1="-15.24" y1="83.82" x2="-15.24" y2="81.28" width="0.1524" layer="91"/>
|
||||
<label x="-15.24" y="81.28" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A27" class="0">
|
||||
<segment>
|
||||
|
|
|
|||
|
|
@ -10078,8 +10078,8 @@ Source: RS Component / Phycomp</description>
|
|||
<part name="R19" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R20" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R21" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="RN1" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN2" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN1" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="C8" library="rcl" deviceset="C-EU" device="C1210" value="10µF"/>
|
||||
<part name="IC7" library="amd-mach-Small-pad" deviceset="M4-128T100" device=""/>
|
||||
<part name="C9" library="rcl" deviceset="C-EU" device="C0603K" value="100nF"/>
|
||||
|
|
@ -10096,7 +10096,6 @@ Source: RS Component / Phycomp</description>
|
|||
<part name="C21" library="rcl" deviceset="C-EU" device="C0603K" value="100nF"/>
|
||||
<part name="C22" library="rcl" deviceset="C-EU" device="C0603K" value="100nF"/>
|
||||
<part name="C23" library="rcl" deviceset="C-EU" device="C0603K" value="100nF"/>
|
||||
<part name="RN3" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="R8" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="X1" library="con-vg" deviceset="FABC96R" device=""/>
|
||||
<part name="IC4" library="74xx-eu" deviceset="74*245" device="DW" technology="HCT"/>
|
||||
|
|
@ -10115,12 +10114,16 @@ Source: RS Component / Phycomp</description>
|
|||
<part name="R14" library="rcl" deviceset="R-EU_" device="R0603"/>
|
||||
<part name="R16" library="rcl" deviceset="R-EU_" device="R0603"/>
|
||||
<part name="R17" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="RN3" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN4" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN5" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN6" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN7" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN8" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN9" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="R3" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R9" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R22" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R23" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
</parts>
|
||||
<sheets>
|
||||
<sheet>
|
||||
|
|
@ -10154,12 +10157,12 @@ Source: RS Component / Phycomp</description>
|
|||
<instance part="C21" gate="G$1" x="-7.62" y="50.8"/>
|
||||
<instance part="C22" gate="G$1" x="-15.24" y="50.8"/>
|
||||
<instance part="C23" gate="G$1" x="-7.62" y="71.12"/>
|
||||
<instance part="RN3" gate="A" x="-2.54" y="147.32"/>
|
||||
<instance part="RN3" gate="B" x="-2.54" y="142.24"/>
|
||||
<instance part="RN3" gate="C" x="-2.54" y="137.16"/>
|
||||
<instance part="RN3" gate="D" x="-2.54" y="132.08"/>
|
||||
<instance part="R8" gate="G$1" x="-2.54" y="121.92"/>
|
||||
<instance part="R17" gate="G$1" x="-2.54" y="93.98"/>
|
||||
<instance part="R3" gate="G$1" x="-2.54" y="147.32"/>
|
||||
<instance part="R9" gate="G$1" x="-2.54" y="137.16"/>
|
||||
<instance part="R22" gate="G$1" x="-2.54" y="132.08"/>
|
||||
<instance part="R23" gate="G$1" x="-2.54" y="142.24"/>
|
||||
</instances>
|
||||
<busses>
|
||||
<bus name="A[0..31]">
|
||||
|
|
@ -11018,9 +11021,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="76.2" y="134.62" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN3" gate="B" pin="2"/>
|
||||
<wire x1="2.54" y1="142.24" x2="7.62" y2="142.24" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="142.24" size="1.27" layer="95"/>
|
||||
<pinref part="R23" gate="G$1" pin="2"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="DSACK0" class="0">
|
||||
|
|
@ -11035,9 +11038,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="76.2" y="139.7" size="1.27" layer="95" xref="yes"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN3" gate="D" pin="2"/>
|
||||
<wire x1="2.54" y1="132.08" x2="7.62" y2="132.08" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="132.08" size="1.27" layer="95"/>
|
||||
<pinref part="R22" gate="G$1" pin="2"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="SIZ0" class="0">
|
||||
|
|
@ -11092,9 +11095,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="33.02" y="124.46" size="1.27" layer="95" rot="R180" xref="yes"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN3" gate="C" pin="2"/>
|
||||
<wire x1="2.54" y1="137.16" x2="7.62" y2="137.16" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="137.16" size="1.27" layer="95"/>
|
||||
<pinref part="R9" gate="G$1" pin="2"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="DS_30" class="0">
|
||||
|
|
@ -11109,9 +11112,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="33.02" y="121.92" size="1.27" layer="95" rot="R180" xref="yes"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN3" gate="A" pin="2"/>
|
||||
<wire x1="2.54" y1="147.32" x2="7.62" y2="147.32" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="147.32" size="1.27" layer="95"/>
|
||||
<pinref part="R3" gate="G$1" pin="2"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="DBEN" class="0">
|
||||
|
|
@ -11320,19 +11323,15 @@ Source: RS Component / Phycomp</description>
|
|||
<junction x="-20.32" y="127"/>
|
||||
<pinref part="R18" gate="G$1" pin="1"/>
|
||||
<pinref part="R19" gate="G$1" pin="1"/>
|
||||
<pinref part="RN3" gate="A" pin="1"/>
|
||||
<wire x1="-7.62" y1="147.32" x2="-20.32" y2="147.32" width="0.1524" layer="91"/>
|
||||
<wire x1="-20.32" y1="147.32" x2="-20.32" y2="142.24" width="0.1524" layer="91"/>
|
||||
<pinref part="RN3" gate="B" pin="1"/>
|
||||
<wire x1="-20.32" y1="142.24" x2="-20.32" y2="137.16" width="0.1524" layer="91"/>
|
||||
<wire x1="-20.32" y1="137.16" x2="-20.32" y2="132.08" width="0.1524" layer="91"/>
|
||||
<wire x1="-20.32" y1="132.08" x2="-20.32" y2="127" width="0.1524" layer="91"/>
|
||||
<wire x1="-7.62" y1="142.24" x2="-20.32" y2="142.24" width="0.1524" layer="91"/>
|
||||
<junction x="-20.32" y="142.24"/>
|
||||
<pinref part="RN3" gate="C" pin="1"/>
|
||||
<wire x1="-7.62" y1="137.16" x2="-20.32" y2="137.16" width="0.1524" layer="91"/>
|
||||
<junction x="-20.32" y="137.16"/>
|
||||
<pinref part="RN3" gate="D" pin="1"/>
|
||||
<wire x1="-7.62" y1="132.08" x2="-20.32" y2="132.08" width="0.1524" layer="91"/>
|
||||
<junction x="-20.32" y="132.08"/>
|
||||
<pinref part="R8" gate="G$1" pin="1"/>
|
||||
|
|
@ -11344,6 +11343,10 @@ Source: RS Component / Phycomp</description>
|
|||
<wire x1="-20.32" y1="93.98" x2="-20.32" y2="101.6" width="0.1524" layer="91"/>
|
||||
<wire x1="-7.62" y1="93.98" x2="-20.32" y2="93.98" width="0.1524" layer="91"/>
|
||||
<junction x="-20.32" y="93.98"/>
|
||||
<pinref part="R9" gate="G$1" pin="1"/>
|
||||
<pinref part="R22" gate="G$1" pin="1"/>
|
||||
<pinref part="R23" gate="G$1" pin="1"/>
|
||||
<pinref part="R3" gate="G$1" pin="1"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="C19" gate="G$1" pin="1"/>
|
||||
|
|
@ -13368,38 +13371,38 @@ Source: RS Component / Phycomp</description>
|
|||
<instance part="C26" gate="G$1" x="185.42" y="116.84"/>
|
||||
<instance part="C27" gate="G$1" x="175.26" y="116.84"/>
|
||||
<instance part="C28" gate="G$1" x="165.1" y="116.84"/>
|
||||
<instance part="RN1" gate="A" x="96.52" y="45.72"/>
|
||||
<instance part="RN1" gate="B" x="96.52" y="40.64"/>
|
||||
<instance part="RN1" gate="C" x="96.52" y="35.56"/>
|
||||
<instance part="RN1" gate="D" x="96.52" y="30.48"/>
|
||||
<instance part="RN2" gate="A" x="96.52" y="25.4"/>
|
||||
<instance part="RN2" gate="B" x="96.52" y="20.32"/>
|
||||
<instance part="RN2" gate="C" x="96.52" y="15.24"/>
|
||||
<instance part="RN2" gate="D" x="96.52" y="10.16"/>
|
||||
<instance part="RN4" gate="A" x="96.52" y="66.04"/>
|
||||
<instance part="RN4" gate="B" x="96.52" y="60.96"/>
|
||||
<instance part="RN4" gate="C" x="96.52" y="55.88"/>
|
||||
<instance part="RN4" gate="D" x="96.52" y="50.8"/>
|
||||
<instance part="RN5" gate="A" x="96.52" y="86.36"/>
|
||||
<instance part="RN5" gate="B" x="96.52" y="81.28"/>
|
||||
<instance part="RN5" gate="C" x="96.52" y="76.2"/>
|
||||
<instance part="RN5" gate="D" x="96.52" y="71.12"/>
|
||||
<instance part="RN6" gate="A" x="96.52" y="106.68"/>
|
||||
<instance part="RN6" gate="B" x="96.52" y="101.6"/>
|
||||
<instance part="RN6" gate="C" x="96.52" y="96.52"/>
|
||||
<instance part="RN6" gate="D" x="96.52" y="91.44"/>
|
||||
<instance part="RN7" gate="A" x="96.52" y="127"/>
|
||||
<instance part="RN7" gate="B" x="96.52" y="121.92"/>
|
||||
<instance part="RN7" gate="C" x="96.52" y="116.84"/>
|
||||
<instance part="RN7" gate="D" x="96.52" y="111.76"/>
|
||||
<instance part="RN8" gate="A" x="96.52" y="147.32"/>
|
||||
<instance part="RN8" gate="B" x="96.52" y="142.24"/>
|
||||
<instance part="RN8" gate="C" x="96.52" y="137.16"/>
|
||||
<instance part="RN8" gate="D" x="96.52" y="132.08"/>
|
||||
<instance part="RN9" gate="A" x="96.52" y="167.64"/>
|
||||
<instance part="RN9" gate="B" x="96.52" y="162.56"/>
|
||||
<instance part="RN9" gate="C" x="96.52" y="157.48"/>
|
||||
<instance part="RN9" gate="D" x="96.52" y="152.4"/>
|
||||
<instance part="RN2" gate="A" x="96.52" y="45.72"/>
|
||||
<instance part="RN2" gate="B" x="96.52" y="40.64"/>
|
||||
<instance part="RN2" gate="C" x="96.52" y="35.56"/>
|
||||
<instance part="RN2" gate="D" x="96.52" y="30.48"/>
|
||||
<instance part="RN1" gate="A" x="96.52" y="25.4"/>
|
||||
<instance part="RN1" gate="B" x="96.52" y="20.32"/>
|
||||
<instance part="RN1" gate="C" x="96.52" y="15.24"/>
|
||||
<instance part="RN1" gate="D" x="96.52" y="10.16"/>
|
||||
<instance part="RN3" gate="A" x="96.52" y="66.04"/>
|
||||
<instance part="RN3" gate="B" x="96.52" y="60.96"/>
|
||||
<instance part="RN3" gate="C" x="96.52" y="55.88"/>
|
||||
<instance part="RN3" gate="D" x="96.52" y="50.8"/>
|
||||
<instance part="RN4" gate="A" x="96.52" y="86.36"/>
|
||||
<instance part="RN4" gate="B" x="96.52" y="81.28"/>
|
||||
<instance part="RN4" gate="C" x="96.52" y="76.2"/>
|
||||
<instance part="RN4" gate="D" x="96.52" y="71.12"/>
|
||||
<instance part="RN5" gate="A" x="96.52" y="106.68"/>
|
||||
<instance part="RN5" gate="B" x="96.52" y="101.6"/>
|
||||
<instance part="RN5" gate="C" x="96.52" y="96.52"/>
|
||||
<instance part="RN5" gate="D" x="96.52" y="91.44"/>
|
||||
<instance part="RN6" gate="A" x="96.52" y="127"/>
|
||||
<instance part="RN6" gate="B" x="96.52" y="121.92"/>
|
||||
<instance part="RN6" gate="C" x="96.52" y="116.84"/>
|
||||
<instance part="RN6" gate="D" x="96.52" y="111.76"/>
|
||||
<instance part="RN7" gate="A" x="96.52" y="147.32"/>
|
||||
<instance part="RN7" gate="B" x="96.52" y="142.24"/>
|
||||
<instance part="RN7" gate="C" x="96.52" y="137.16"/>
|
||||
<instance part="RN7" gate="D" x="96.52" y="132.08"/>
|
||||
<instance part="RN8" gate="A" x="96.52" y="167.64"/>
|
||||
<instance part="RN8" gate="B" x="96.52" y="162.56"/>
|
||||
<instance part="RN8" gate="C" x="96.52" y="157.48"/>
|
||||
<instance part="RN8" gate="D" x="96.52" y="152.4"/>
|
||||
</instances>
|
||||
<busses>
|
||||
<bus name="A[0..31]">
|
||||
|
|
@ -13715,98 +13718,98 @@ Source: RS Component / Phycomp</description>
|
|||
<segment>
|
||||
<label x="101.6" y="5.08" size="1.27" layer="95" xref="yes"/>
|
||||
<wire x1="101.6" y1="50.8" x2="101.6" y2="45.72" width="0.1524" layer="91"/>
|
||||
<pinref part="RN1" gate="A" pin="2"/>
|
||||
<pinref part="RN2" gate="A" pin="2"/>
|
||||
<wire x1="101.6" y1="45.72" x2="101.6" y2="40.64" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="45.72"/>
|
||||
<pinref part="RN1" gate="B" pin="2"/>
|
||||
<pinref part="RN2" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="40.64" x2="101.6" y2="35.56" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="40.64"/>
|
||||
<pinref part="RN1" gate="C" pin="2"/>
|
||||
<pinref part="RN2" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="35.56" x2="101.6" y2="30.48" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="35.56"/>
|
||||
<pinref part="RN1" gate="D" pin="2"/>
|
||||
<pinref part="RN2" gate="D" pin="2"/>
|
||||
<wire x1="101.6" y1="30.48" x2="101.6" y2="25.4" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="30.48"/>
|
||||
<pinref part="RN2" gate="A" pin="2"/>
|
||||
<pinref part="RN1" gate="A" pin="2"/>
|
||||
<wire x1="101.6" y1="25.4" x2="101.6" y2="20.32" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="25.4"/>
|
||||
<pinref part="RN2" gate="B" pin="2"/>
|
||||
<pinref part="RN1" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="20.32" x2="101.6" y2="15.24" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="20.32"/>
|
||||
<pinref part="RN2" gate="C" pin="2"/>
|
||||
<pinref part="RN1" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="15.24" x2="101.6" y2="10.16" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="15.24"/>
|
||||
<pinref part="RN2" gate="D" pin="2"/>
|
||||
<pinref part="RN1" gate="D" pin="2"/>
|
||||
<wire x1="101.6" y1="10.16" x2="101.6" y2="5.08" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="10.16"/>
|
||||
<pinref part="RN4" gate="D" pin="2"/>
|
||||
<pinref part="RN4" gate="C" pin="2"/>
|
||||
<pinref part="RN3" gate="D" pin="2"/>
|
||||
<pinref part="RN3" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="50.8" x2="101.6" y2="55.88" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="50.8"/>
|
||||
<pinref part="RN4" gate="B" pin="2"/>
|
||||
<pinref part="RN3" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="55.88" x2="101.6" y2="60.96" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="55.88"/>
|
||||
<pinref part="RN4" gate="A" pin="2"/>
|
||||
<pinref part="RN3" gate="A" pin="2"/>
|
||||
<wire x1="101.6" y1="60.96" x2="101.6" y2="66.04" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="60.96"/>
|
||||
<pinref part="RN7" gate="A" pin="2"/>
|
||||
<pinref part="RN7" gate="B" pin="2"/>
|
||||
<pinref part="RN6" gate="A" pin="2"/>
|
||||
<pinref part="RN6" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="127" x2="101.6" y2="121.92" width="0.1524" layer="91"/>
|
||||
<pinref part="RN7" gate="C" pin="2"/>
|
||||
<pinref part="RN6" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="121.92" x2="101.6" y2="116.84" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="121.92"/>
|
||||
<pinref part="RN7" gate="D" pin="2"/>
|
||||
<pinref part="RN6" gate="D" pin="2"/>
|
||||
<wire x1="101.6" y1="116.84" x2="101.6" y2="111.76" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="116.84"/>
|
||||
<pinref part="RN6" gate="A" pin="2"/>
|
||||
<pinref part="RN5" gate="A" pin="2"/>
|
||||
<wire x1="101.6" y1="111.76" x2="101.6" y2="106.68" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="111.76"/>
|
||||
<pinref part="RN6" gate="B" pin="2"/>
|
||||
<pinref part="RN5" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="106.68" x2="101.6" y2="101.6" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="106.68"/>
|
||||
<pinref part="RN6" gate="C" pin="2"/>
|
||||
<pinref part="RN5" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="101.6" x2="101.6" y2="96.52" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="101.6"/>
|
||||
<pinref part="RN6" gate="D" pin="2"/>
|
||||
<pinref part="RN5" gate="D" pin="2"/>
|
||||
<wire x1="101.6" y1="96.52" x2="101.6" y2="91.44" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="96.52"/>
|
||||
<pinref part="RN5" gate="A" pin="2"/>
|
||||
<pinref part="RN4" gate="A" pin="2"/>
|
||||
<wire x1="101.6" y1="91.44" x2="101.6" y2="86.36" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="91.44"/>
|
||||
<pinref part="RN5" gate="B" pin="2"/>
|
||||
<pinref part="RN4" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="86.36" x2="101.6" y2="81.28" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="86.36"/>
|
||||
<pinref part="RN5" gate="C" pin="2"/>
|
||||
<pinref part="RN4" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="81.28" x2="101.6" y2="76.2" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="81.28"/>
|
||||
<pinref part="RN5" gate="D" pin="2"/>
|
||||
<pinref part="RN4" gate="D" pin="2"/>
|
||||
<wire x1="101.6" y1="76.2" x2="101.6" y2="71.12" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="76.2"/>
|
||||
<wire x1="101.6" y1="71.12" x2="101.6" y2="66.04" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="71.12"/>
|
||||
<junction x="101.6" y="66.04"/>
|
||||
<pinref part="RN8" gate="D" pin="2"/>
|
||||
<pinref part="RN7" gate="D" pin="2"/>
|
||||
<wire x1="101.6" y1="127" x2="101.6" y2="132.08" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="127"/>
|
||||
<pinref part="RN8" gate="C" pin="2"/>
|
||||
<pinref part="RN7" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="132.08" x2="101.6" y2="137.16" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="132.08"/>
|
||||
<pinref part="RN8" gate="B" pin="2"/>
|
||||
<pinref part="RN7" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="137.16" x2="101.6" y2="142.24" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="137.16"/>
|
||||
<pinref part="RN8" gate="A" pin="2"/>
|
||||
<pinref part="RN7" gate="A" pin="2"/>
|
||||
<wire x1="101.6" y1="142.24" x2="101.6" y2="147.32" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="142.24"/>
|
||||
<pinref part="RN9" gate="D" pin="2"/>
|
||||
<pinref part="RN8" gate="D" pin="2"/>
|
||||
<wire x1="101.6" y1="147.32" x2="101.6" y2="152.4" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="147.32"/>
|
||||
<pinref part="RN9" gate="C" pin="2"/>
|
||||
<pinref part="RN8" gate="C" pin="2"/>
|
||||
<wire x1="101.6" y1="152.4" x2="101.6" y2="157.48" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="152.4"/>
|
||||
<pinref part="RN9" gate="B" pin="2"/>
|
||||
<pinref part="RN8" gate="B" pin="2"/>
|
||||
<wire x1="101.6" y1="157.48" x2="101.6" y2="162.56" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="157.48"/>
|
||||
<pinref part="RN9" gate="A" pin="2"/>
|
||||
<pinref part="RN8" gate="A" pin="2"/>
|
||||
<wire x1="101.6" y1="162.56" x2="101.6" y2="167.64" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="162.56"/>
|
||||
</segment>
|
||||
|
|
@ -13924,7 +13927,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="83.82" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN4" gate="C" pin="1"/>
|
||||
<pinref part="RN3" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="55.88" x2="86.36" y2="55.88" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="55.88" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -13936,7 +13939,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="81.28" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN4" gate="B" pin="1"/>
|
||||
<pinref part="RN3" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="60.96" x2="86.36" y2="60.96" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="60.96" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -13948,7 +13951,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="78.74" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN4" gate="A" pin="1"/>
|
||||
<pinref part="RN3" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="66.04" x2="86.36" y2="66.04" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="66.04" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -13960,7 +13963,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="76.2" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN5" gate="B" pin="1"/>
|
||||
<pinref part="RN4" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="81.28" x2="86.36" y2="81.28" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="81.28" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -13972,7 +13975,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="73.66" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN5" gate="A" pin="1"/>
|
||||
<pinref part="RN4" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="86.36" x2="86.36" y2="86.36" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="86.36" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -13984,7 +13987,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="71.12" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN4" gate="D" pin="1"/>
|
||||
<pinref part="RN3" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="50.8" x2="86.36" y2="50.8" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="50.8" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -13996,7 +13999,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="68.58" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN6" gate="A" pin="1"/>
|
||||
<pinref part="RN5" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="106.68" x2="86.36" y2="106.68" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="106.68" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14057,7 +14060,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="124.46" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN5" gate="D" pin="1"/>
|
||||
<pinref part="RN4" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="71.12" x2="86.36" y2="71.12" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="71.12" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14069,7 +14072,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="121.92" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN5" gate="C" pin="1"/>
|
||||
<pinref part="RN4" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="76.2" x2="86.36" y2="76.2" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="76.2" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14081,7 +14084,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="119.38" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN6" gate="D" pin="1"/>
|
||||
<pinref part="RN5" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="91.44" x2="86.36" y2="91.44" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="91.44" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14093,7 +14096,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="116.84" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN6" gate="C" pin="1"/>
|
||||
<pinref part="RN5" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="96.52" x2="86.36" y2="96.52" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="96.52" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14105,7 +14108,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="114.3" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN6" gate="B" pin="1"/>
|
||||
<pinref part="RN5" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="101.6" x2="86.36" y2="101.6" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="101.6" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14117,7 +14120,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="111.76" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN7" gate="C" pin="1"/>
|
||||
<pinref part="RN6" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="116.84" x2="86.36" y2="116.84" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="116.84" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14129,7 +14132,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="109.22" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN7" gate="B" pin="1"/>
|
||||
<pinref part="RN6" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="121.92" x2="86.36" y2="121.92" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="121.92" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14141,7 +14144,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="106.68" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN7" gate="A" pin="1"/>
|
||||
<pinref part="RN6" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="127" x2="86.36" y2="127" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="127" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14153,7 +14156,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="147.32" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN9" gate="C" pin="1"/>
|
||||
<pinref part="RN8" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="157.48" x2="86.36" y2="157.48" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="157.48" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14165,7 +14168,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="149.86" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN7" gate="D" pin="1"/>
|
||||
<pinref part="RN6" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="111.76" x2="86.36" y2="111.76" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="111.76" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14177,7 +14180,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="152.4" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN8" gate="A" pin="1"/>
|
||||
<pinref part="RN7" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="147.32" x2="86.36" y2="147.32" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="147.32" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14189,7 +14192,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="154.94" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN8" gate="B" pin="1"/>
|
||||
<pinref part="RN7" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="142.24" x2="86.36" y2="142.24" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="142.24" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14441,7 +14444,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="157.48" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN8" gate="D" pin="1"/>
|
||||
<pinref part="RN7" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="132.08" x2="86.36" y2="132.08" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="132.08" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14453,7 +14456,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="160.02" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN8" gate="C" pin="1"/>
|
||||
<pinref part="RN7" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="137.16" x2="86.36" y2="137.16" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="137.16" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14465,7 +14468,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="162.56" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN9" gate="D" pin="1"/>
|
||||
<pinref part="RN8" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="152.4" x2="86.36" y2="152.4" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="152.4" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14477,7 +14480,7 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="165.1" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN9" gate="B" pin="1"/>
|
||||
<pinref part="RN8" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="162.56" x2="86.36" y2="162.56" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="162.56" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
@ -14565,63 +14568,63 @@ Source: RS Component / Phycomp</description>
|
|||
</net>
|
||||
<net name="A0" class="0">
|
||||
<segment>
|
||||
<pinref part="RN9" gate="A" pin="1"/>
|
||||
<pinref part="RN8" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="167.64" x2="86.36" y2="167.64" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="167.64" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A26" class="0">
|
||||
<segment>
|
||||
<pinref part="RN1" gate="D" pin="1"/>
|
||||
<pinref part="RN2" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="30.48" x2="86.36" y2="30.48" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="30.48" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A25" class="0">
|
||||
<segment>
|
||||
<pinref part="RN1" gate="C" pin="1"/>
|
||||
<pinref part="RN2" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="35.56" x2="86.36" y2="35.56" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="35.56" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A24" class="0">
|
||||
<segment>
|
||||
<pinref part="RN1" gate="B" pin="1"/>
|
||||
<pinref part="RN2" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="40.64" x2="86.36" y2="40.64" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="40.64" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A29" class="0">
|
||||
<segment>
|
||||
<pinref part="RN1" gate="A" pin="1"/>
|
||||
<pinref part="RN2" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="45.72" x2="86.36" y2="45.72" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="45.72" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A28" class="0">
|
||||
<segment>
|
||||
<pinref part="RN2" gate="D" pin="1"/>
|
||||
<pinref part="RN1" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="10.16" x2="86.36" y2="10.16" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="10.16" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A27" class="0">
|
||||
<segment>
|
||||
<pinref part="RN2" gate="C" pin="1"/>
|
||||
<pinref part="RN1" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="15.24" x2="86.36" y2="15.24" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="15.24" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A31" class="0">
|
||||
<segment>
|
||||
<pinref part="RN2" gate="B" pin="1"/>
|
||||
<pinref part="RN1" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="20.32" x2="86.36" y2="20.32" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="20.32" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A30" class="0">
|
||||
<segment>
|
||||
<pinref part="RN2" gate="A" pin="1"/>
|
||||
<pinref part="RN1" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="25.4" x2="86.36" y2="25.4" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="25.4" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
|
|
|
|||
|
|
@ -11018,9 +11018,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="76.2" y="134.62" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN3" gate="D" pin="2"/>
|
||||
<wire x1="2.54" y1="132.08" x2="7.62" y2="132.08" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="132.08" size="1.27" layer="95"/>
|
||||
<pinref part="RN3" gate="B" pin="2"/>
|
||||
<wire x1="2.54" y1="142.24" x2="7.62" y2="142.24" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="142.24" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="DSACK0" class="0">
|
||||
|
|
@ -11035,9 +11035,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="76.2" y="139.7" size="1.27" layer="95" xref="yes"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN3" gate="C" pin="2"/>
|
||||
<wire x1="2.54" y1="137.16" x2="7.62" y2="137.16" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="137.16" size="1.27" layer="95"/>
|
||||
<pinref part="RN3" gate="D" pin="2"/>
|
||||
<wire x1="2.54" y1="132.08" x2="7.62" y2="132.08" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="132.08" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="SIZ0" class="0">
|
||||
|
|
@ -11092,9 +11092,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="33.02" y="124.46" size="1.27" layer="95" rot="R180" xref="yes"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN3" gate="B" pin="2"/>
|
||||
<wire x1="2.54" y1="142.24" x2="7.62" y2="142.24" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="142.24" size="1.27" layer="95"/>
|
||||
<pinref part="RN3" gate="C" pin="2"/>
|
||||
<wire x1="2.54" y1="137.16" x2="7.62" y2="137.16" width="0.1524" layer="91"/>
|
||||
<label x="7.62" y="137.16" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="DS_30" class="0">
|
||||
|
|
@ -12680,11 +12680,6 @@ Source: RS Component / Phycomp</description>
|
|||
<pinref part="X1" gate="-A9" pin="B"/>
|
||||
<wire x1="236.22" y1="86.36" x2="238.76" y2="86.36" width="0.1524" layer="91"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="IC7" gate="G$1" pin="IO58"/>
|
||||
<wire x1="134.62" y1="116.84" x2="134.62" y2="121.92" width="0.1524" layer="91"/>
|
||||
<label x="134.62" y="121.92" size="1.016" layer="95" rot="R90"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="BR_30" class="0">
|
||||
<segment>
|
||||
|
|
@ -13338,6 +13333,13 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="124.46" y="27.94" size="1.27" layer="95" rot="R270"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="R/W_00" class="0">
|
||||
<segment>
|
||||
<pinref part="IC7" gate="G$1" pin="IO58"/>
|
||||
<wire x1="134.62" y1="116.84" x2="134.62" y2="121.92" width="0.1524" layer="91"/>
|
||||
<label x="134.62" y="121.92" size="1.016" layer="95" rot="R90"/>
|
||||
</segment>
|
||||
</net>
|
||||
</nets>
|
||||
</sheet>
|
||||
<sheet>
|
||||
|
|
@ -13808,6 +13810,11 @@ Source: RS Component / Phycomp</description>
|
|||
<wire x1="101.6" y1="162.56" x2="101.6" y2="167.64" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="162.56"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="IC9" gate="A" pin="A1"/>
|
||||
<wire x1="40.64" y1="86.36" x2="43.18" y2="86.36" width="0.1524" layer="91"/>
|
||||
<label x="43.18" y="86.36" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="VCC" class="0">
|
||||
<segment>
|
||||
|
|
@ -13994,13 +14001,6 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="88.9" y="106.68" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="R/W_00" class="0">
|
||||
<segment>
|
||||
<pinref part="IC9" gate="A" pin="B1"/>
|
||||
<wire x1="15.24" y1="86.36" x2="12.7" y2="86.36" width="0.1524" layer="91"/>
|
||||
<label x="12.7" y="86.36" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="AMIGA_A23" class="0">
|
||||
<segment>
|
||||
<pinref part="IC9" gate="A" pin="B2"/>
|
||||
|
|
@ -14563,13 +14563,6 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="45.72" y="60.96" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="R/W" class="0">
|
||||
<segment>
|
||||
<pinref part="IC9" gate="A" pin="A1"/>
|
||||
<wire x1="40.64" y1="86.36" x2="45.72" y2="86.36" width="0.1524" layer="91"/>
|
||||
<label x="45.72" y="86.36" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A0" class="0">
|
||||
<segment>
|
||||
<pinref part="RN9" gate="A" pin="1"/>
|
||||
|
|
|
|||
|
|
@ -13917,9 +13917,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="83.82" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN4" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="66.04" x2="86.36" y2="66.04" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="66.04" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN4" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="55.88" x2="86.36" y2="55.88" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="55.88" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A22" class="0">
|
||||
|
|
@ -13941,9 +13941,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="78.74" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN4" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="55.88" x2="86.36" y2="55.88" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="55.88" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN4" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="66.04" x2="86.36" y2="66.04" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="66.04" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A20" class="0">
|
||||
|
|
@ -13953,9 +13953,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="76.2" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN4" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="50.8" x2="86.36" y2="50.8" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="50.8" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN5" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="81.28" x2="86.36" y2="81.28" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="81.28" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A19" class="0">
|
||||
|
|
@ -13977,9 +13977,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="71.12" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN5" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="81.28" x2="86.36" y2="81.28" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="81.28" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN4" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="50.8" x2="86.36" y2="50.8" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="50.8" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A17" class="0">
|
||||
|
|
@ -13989,9 +13989,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="68.58" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN5" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="76.2" x2="86.36" y2="76.2" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="76.2" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN6" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="106.68" x2="86.36" y2="106.68" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="106.68" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="R/W_00" class="0">
|
||||
|
|
@ -14069,9 +14069,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="121.92" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN6" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="106.68" x2="86.36" y2="106.68" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="106.68" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN5" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="76.2" x2="86.36" y2="76.2" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="76.2" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A14" class="0">
|
||||
|
|
@ -14081,9 +14081,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="119.38" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN6" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="101.6" x2="86.36" y2="101.6" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="101.6" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN6" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="91.44" x2="86.36" y2="91.44" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="91.44" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A13" class="0">
|
||||
|
|
@ -14105,9 +14105,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="114.3" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN6" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="91.44" x2="86.36" y2="91.44" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="91.44" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN6" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="101.6" x2="86.36" y2="101.6" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="101.6" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A11" class="0">
|
||||
|
|
@ -14117,9 +14117,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="111.76" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN7" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="127" x2="86.36" y2="127" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="127" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN7" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="116.84" x2="86.36" y2="116.84" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="116.84" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A10" class="0">
|
||||
|
|
@ -14141,9 +14141,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="106.68" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN7" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="116.84" x2="86.36" y2="116.84" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="116.84" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN7" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="127" x2="86.36" y2="127" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="127" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A5" class="0">
|
||||
|
|
@ -14153,9 +14153,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="147.32" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN8" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="137.16" x2="86.36" y2="137.16" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="137.16" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN9" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="157.48" x2="86.36" y2="157.48" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="157.48" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A6" class="0">
|
||||
|
|
@ -14165,9 +14165,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="149.86" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN8" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="142.24" x2="86.36" y2="142.24" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="142.24" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN7" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="111.76" x2="86.36" y2="111.76" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="111.76" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A7" class="0">
|
||||
|
|
@ -14189,9 +14189,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="154.94" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN7" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="111.76" x2="86.36" y2="111.76" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="111.76" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN8" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="142.24" x2="86.36" y2="142.24" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="142.24" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="AMIGA_A4" class="0">
|
||||
|
|
@ -14453,9 +14453,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="160.02" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN9" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="167.64" x2="86.36" y2="167.64" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="167.64" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN8" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="137.16" x2="86.36" y2="137.16" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="137.16" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A2" class="0">
|
||||
|
|
@ -14465,9 +14465,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="162.56" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN9" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="162.56" x2="86.36" y2="162.56" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="162.56" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN9" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="152.4" x2="86.36" y2="152.4" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="152.4" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A1" class="0">
|
||||
|
|
@ -14477,9 +14477,9 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="53.34" y="165.1" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="RN9" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="157.48" x2="86.36" y2="157.48" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="157.48" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN9" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="162.56" x2="86.36" y2="162.56" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="162.56" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="AMIGA_D7" class="0">
|
||||
|
|
@ -14570,67 +14570,67 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="45.72" y="86.36" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A24" class="0">
|
||||
<net name="A0" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="45.72" x2="91.44" y2="45.72" width="0.1524" layer="91"/>
|
||||
<pinref part="RN1" gate="A" pin="1"/>
|
||||
<label x="88.9" y="45.72" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A25" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="40.64" x2="91.44" y2="40.64" width="0.1524" layer="91"/>
|
||||
<pinref part="RN1" gate="B" pin="1"/>
|
||||
<label x="88.9" y="40.64" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN9" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="167.64" x2="86.36" y2="167.64" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="167.64" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A26" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="35.56" x2="91.44" y2="35.56" width="0.1524" layer="91"/>
|
||||
<pinref part="RN1" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="30.48" x2="86.36" y2="30.48" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="30.48" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A25" class="0">
|
||||
<segment>
|
||||
<pinref part="RN1" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="35.56" x2="86.36" y2="35.56" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="35.56" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A28" class="0">
|
||||
<net name="A24" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="25.4" x2="91.44" y2="25.4" width="0.1524" layer="91"/>
|
||||
<pinref part="RN2" gate="A" pin="1"/>
|
||||
<label x="88.9" y="25.4" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN1" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="40.64" x2="86.36" y2="40.64" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="40.64" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A29" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="20.32" x2="91.44" y2="20.32" width="0.1524" layer="91"/>
|
||||
<pinref part="RN2" gate="B" pin="1"/>
|
||||
<label x="88.9" y="20.32" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN1" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="45.72" x2="86.36" y2="45.72" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="45.72" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A30" class="0">
|
||||
<net name="A28" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="15.24" x2="91.44" y2="15.24" width="0.1524" layer="91"/>
|
||||
<pinref part="RN2" gate="C" pin="1"/>
|
||||
<label x="88.9" y="15.24" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A31" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="10.16" x2="91.44" y2="10.16" width="0.1524" layer="91"/>
|
||||
<pinref part="RN2" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="10.16" x2="86.36" y2="10.16" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="10.16" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A27" class="0">
|
||||
<segment>
|
||||
<wire x1="86.36" y1="30.48" x2="91.44" y2="30.48" width="0.1524" layer="91"/>
|
||||
<pinref part="RN1" gate="D" pin="1"/>
|
||||
<label x="88.9" y="30.48" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN2" gate="C" pin="1"/>
|
||||
<wire x1="91.44" y1="15.24" x2="86.36" y2="15.24" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="15.24" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A0" class="0">
|
||||
<net name="A31" class="0">
|
||||
<segment>
|
||||
<pinref part="RN9" gate="D" pin="1"/>
|
||||
<wire x1="91.44" y1="152.4" x2="86.36" y2="152.4" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="152.4" size="1.27" layer="95" rot="R180"/>
|
||||
<pinref part="RN2" gate="B" pin="1"/>
|
||||
<wire x1="91.44" y1="20.32" x2="86.36" y2="20.32" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="20.32" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="A30" class="0">
|
||||
<segment>
|
||||
<pinref part="RN2" gate="A" pin="1"/>
|
||||
<wire x1="91.44" y1="25.4" x2="86.36" y2="25.4" width="0.1524" layer="91"/>
|
||||
<label x="88.9" y="25.4" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
</nets>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,6 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!DOCTYPE eagle SYSTEM "eagle.dtd">
|
||||
<eagle version="6.5.0">
|
||||
<eagle version="6.6.0">
|
||||
<drawing>
|
||||
<settings>
|
||||
<setting alwaysvectorfont="no"/>
|
||||
|
|
@ -10109,10 +10109,10 @@ Source: RS Component / Phycomp</description>
|
|||
<part name="C26" library="rcl" deviceset="C-EU" device="C0603K" value="100nF"/>
|
||||
<part name="C27" library="rcl" deviceset="C-EU" device="C0603K" value="100nF"/>
|
||||
<part name="C28" library="rcl" deviceset="C-EU" device="C0603K" value="100nF"/>
|
||||
<part name="R10" library="rcl" deviceset="R-EU_" device="R0603"/>
|
||||
<part name="R11" library="rcl" deviceset="R-EU_" device="R0603"/>
|
||||
<part name="R14" library="rcl" deviceset="R-EU_" device="R0603"/>
|
||||
<part name="R16" library="rcl" deviceset="R-EU_" device="R0603"/>
|
||||
<part name="R10" library="rcl" deviceset="R-EU_" device="R0603" value="68"/>
|
||||
<part name="R11" library="rcl" deviceset="R-EU_" device="R0603" value="68"/>
|
||||
<part name="R14" library="rcl" deviceset="R-EU_" device="R0603" value="68"/>
|
||||
<part name="R16" library="rcl" deviceset="R-EU_" device="R0603" value="10"/>
|
||||
<part name="R17" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="RN3" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
<part name="RN4" library="resistor-dil" deviceset="4R-N" device="EXBV8V" value="4,7k"/>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -18,7 +18,7 @@
|
|||
<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="no" active="yes"/>
|
||||
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
|
||||
|
|
@ -2816,7 +2816,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<attribute name="NAME" x="13.3858" y="54.5592" size="0.8128" layer="25" ratio="10" rot="R180"/>
|
||||
</element>
|
||||
<element name="IC9" library="74xx-eu" package="SO20W" value="74HCT245DW" x="10.2108" y="46.482" smashed="yes" rot="R90">
|
||||
<attribute name="NAME" x="15.2146" y="39.7764" size="0.8128" layer="25" ratio="10" rot="R180"/>
|
||||
<attribute name="NAME" x="13.5382" y="39.7764" size="0.8128" layer="25" ratio="10" rot="R180"/>
|
||||
</element>
|
||||
<element name="IC10" library="74xx-eu" package="SO20W" value="74HCT245DW" x="10.3632" y="24.6888" smashed="yes" rot="R90">
|
||||
<attribute name="NAME" x="13.5382" y="17.8308" size="0.8128" layer="25" ratio="10" rot="R180"/>
|
||||
|
|
@ -2918,6 +2918,14 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<element name="R25" library="rcl" package="R0603" value="4,7k" x="74.4982" y="54.61" smashed="yes">
|
||||
<attribute name="NAME" x="73.7108" y="55.3974" size="0.8128" layer="25"/>
|
||||
</element>
|
||||
<element name="R26" library="rcl" package="R0603" value="4,7K" x="5.9436" y="35.2044" smashed="yes">
|
||||
<attribute name="NAME" x="5.0038" y="33.5534" size="0.8128" layer="25"/>
|
||||
<attribute name="VALUE" x="5.3086" y="33.2994" size="1.27" layer="27"/>
|
||||
</element>
|
||||
<element name="R27" library="rcl" package="R0603" value="4,7K" x="15.0876" y="38.2524" smashed="yes" rot="R180">
|
||||
<attribute name="NAME" x="18.923" y="38.6842" size="0.8128" layer="25" rot="R180"/>
|
||||
<attribute name="VALUE" x="15.7226" y="40.1574" size="1.27" layer="27" rot="R180"/>
|
||||
</element>
|
||||
</elements>
|
||||
<signals>
|
||||
<signal name="D0">
|
||||
|
|
@ -6481,6 +6489,10 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<contactref element="R25" pad="1"/>
|
||||
<wire x1="73.6482" y1="54.61" x2="72.2376" y2="53.1994" width="0.1524" layer="1"/>
|
||||
<wire x1="72.2376" y1="53.1994" x2="72.2376" y2="52.578" width="0.1524" layer="1"/>
|
||||
<contactref element="R26" pad="2"/>
|
||||
<contactref element="R27" pad="1"/>
|
||||
<wire x1="6.7936" y1="35.2044" x2="6.7936" y2="36.0308" width="0.1524" layer="1"/>
|
||||
<wire x1="6.7936" y1="36.0308" x2="5.1816" y2="37.6428" width="0.1524" layer="1"/>
|
||||
<wire x1="69.8246" y1="88.6596" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2328" y1="98.4504" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.6354" y1="96.608" x2="57.1754" y2="98.4788" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -6516,9 +6528,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="31.5976" y1="33.5788" x2="36.9062" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="35.2806" x2="31.5836" y2="33.5648" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="19.2786" x2="33.3134" y2="26.8986" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="34.3544" x2="24.7904" y2="35.2806" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="37.214" x2="15.3924" y2="34.3544" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="38.862" x2="10.9728" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="34.3544" x2="15.9376" y2="38.2524" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="38.862" x2="15.9376" y2="38.2524" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="6.7936" y1="36.0308" x2="10.9728" y2="37.214" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.9304" y1="40.3606" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="6.5786" x2="33.3134" y2="16.7386" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="55.513" y1="32.4612" x2="52.1462" y2="42.7228" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -6528,8 +6540,14 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="5.0686" y1="53.9496" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.221" y1="69.0372" x2="5.1816" y2="55.7022" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="4.9428" y1="84.582" x2="5.1816" y2="70.9422" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.334" y1="18.9738" x2="15.3924" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.334" y1="18.9738" x2="6.7936" y2="35.2044" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="5.4864" y1="3.429" x2="5.334" y2="16.1544" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.9376" y1="38.2524" x2="15.9376" y2="39.585" width="0.1524" layer="1"/>
|
||||
<wire x1="15.9376" y1="39.585" x2="15.9512" y2="39.5986" width="0.1524" layer="1"/>
|
||||
<via x="15.9512" y="39.5986" extent="1-16" drill="0.3"/>
|
||||
<wire x1="15.9512" y1="39.5986" x2="15.2654" y2="39.5986" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="15.2654" y1="39.5986" x2="15.0876" y2="39.7764" width="0" layer="19" extent="1-16"/>
|
||||
<wire x1="15.0876" y1="39.7764" x2="10.9728" y2="38.862" width="0" layer="19" extent="1-16"/>
|
||||
</signal>
|
||||
<signal name="GND">
|
||||
<contactref element="IC2" pad="16"/>
|
||||
|
|
@ -6855,7 +6873,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="24.7904" y="28.9052" extent="1-16" drill="0.3"/>
|
||||
<via x="19.9136" y="32.1056" extent="1-16" drill="0.3"/>
|
||||
<via x="19.7612" y="34.2392" extent="1-16" drill="0.3"/>
|
||||
<via x="14.2748" y="37.8968" extent="1-16" drill="0.3"/>
|
||||
<via x="13.5128" y="34.544" extent="1-16" drill="0.3"/>
|
||||
<via x="15.3416" y="32.1056" extent="1-16" drill="0.3"/>
|
||||
<via x="15.494" y="16.5608" extent="1-16" drill="0.3"/>
|
||||
<via x="19.9136" y="3.1496" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6976,7 +6994,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="83.1532" y1="95.7202" x2="83.9532" y2="95.7202" width="0.1524" layer="1"/>
|
||||
<wire x1="83.9532" y1="95.7202" x2="85.3062" y2="95.7202" width="0.1524" layer="1"/>
|
||||
<wire x1="85.3062" y1="95.7202" x2="85.7504" y2="96.1644" width="0.1524" layer="1"/>
|
||||
<contactref element="IC9" pad="2"/>
|
||||
<via x="29.21" y="49.022" extent="1-16" drill="0.3"/>
|
||||
<via x="20.9804" y="44.9072" extent="1-16" drill="0.3"/>
|
||||
<via x="20.9804" y="42.0116" extent="1-16" drill="0.3"/>
|
||||
|
|
@ -6986,9 +7003,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<via x="76.5556" y="56.9976" extent="1-16" drill="0.3"/>
|
||||
<via x="48.8188" y="47.3964" extent="1-16" drill="0.3"/>
|
||||
<via x="78.867" y="46.482" extent="1-16" drill="0.3"/>
|
||||
<via x="16.7894" y="42.0624" extent="1-16" drill="0.3"/>
|
||||
<wire x1="15.24" y1="42.037" x2="16.764" y2="42.037" width="0.1524" layer="1"/>
|
||||
<wire x1="16.764" y1="42.037" x2="16.7894" y2="42.0624" width="0.1524" layer="1"/>
|
||||
<contactref element="R24" pad="2"/>
|
||||
<wire x1="65.0104" y1="50.7492" x2="65.0104" y2="48.0704" width="0.1524" layer="1"/>
|
||||
<wire x1="65.0104" y1="48.0704" x2="66.1416" y2="46.9392" width="0.1524" layer="1"/>
|
||||
|
|
@ -7039,31 +7053,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="20.9804" y1="44.9072" x2="24.7904" y2="46.6852" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="20.9804" y1="42.0116" x2="20.9804" y2="44.9072" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="40.3606" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.7894" y1="42.0624" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="14.2748" y1="37.8968" x2="15.24" y2="42.037" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.21" y1="49.022" x2="24.7396" y2="49.276" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="40.1828" x2="41.7068" y2="43.688" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.0662" y1="40.1828" x2="44.5262" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.0314" y1="38.3286" x2="47.0662" y2="40.1828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="40.1828" x2="48.0314" y2="38.3286" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="34.414" x2="14.2748" y2="37.8968" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3416" y1="32.1056" x2="10.9728" y2="32.766" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="30.4038" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="32.1056" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.7612" y1="34.2392" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="31.496" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="28.9052" x2="24.7904" y2="31.496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="25.7302" y1="28.829" x2="24.7904" y2="28.9052" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.718" y1="31.3944" x2="25.7302" y2="28.829" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="37.6428" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.16" y1="41.2496" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.798" y1="30.1244" x2="29.8336" y2="31.51" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.0934" y1="30.1244" x2="34.8234" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3634" y1="28.4086" x2="36.0934" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.6334" y1="30.099" x2="37.3634" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.9034" y1="28.4086" x2="38.6334" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="24.3586" x2="34.8234" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="22.2504" x2="31.9278" y2="24.3586" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.4462" y1="60.5028" x2="36.9824" y2="55.4228" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.5262" y1="60.5028" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.2976" y1="57.9628" x2="44.5262" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7071,34 +7065,12 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="48.3616" y1="57.9628" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="47.766" y1="55.3212" x2="47.4472" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="49.6062" y1="60.5028" x2="48.3616" y2="57.9628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.956" y1="16.3462" x2="31.623" y2="21.8186" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.608" y1="11.9888" x2="33.3134" y2="15.4686" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.4688" y1="14.1224" x2="38.6334" y2="11.9634" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="14.1224" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="14.1224" x2="43.688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.228" y1="14.1224" x2="44.958" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.1076" y1="14.1224" x2="46.228" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.418" y1="19.8628" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="19.9136" x2="42.418" y2="19.8628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="19.9136" x2="43.688" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.2788" y1="19.9136" x2="44.958" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.102" y1="12.6492" x2="48.1076" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="15.4686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.1952" y1="17.1704" x2="61.214" y2="15.4572" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="18.1864" x2="63.1952" y2="17.1704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="16.7132" x2="65.3288" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="19.9136" x2="63.8048" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.7672" y1="15.2908" x2="65.5828" y2="15.3192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.5216" y1="19.9644" x2="62.992" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="16.764" y1="52.2732" x2="23.876" y2="51.7652" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.1892" y1="53.594" x2="15.24" y2="52.197" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="77.1906" y1="39.5224" x2="78.867" y2="46.482" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="80.1624" y1="34.5948" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="76.7956" y1="31.75" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.8808" y1="67.5132" x2="39.4462" y2="60.5028" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="5.0686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.2356" y1="3.7592" x2="52.6034" y2="3.683" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="3.7592" x2="56.2356" y2="3.7592" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.4116" y1="90.5256" x2="74.3204" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="64.1604" y1="94.3102" x2="67.4116" y2="90.5256" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="61.6712" y1="97.3836" x2="64.1604" y2="94.3102" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7127,6 +7099,47 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="31.383" y1="86.7664" x2="34.4424" y2="86.5632" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.2896" y1="78.8172" x2="43.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="35.8762" y1="79.0956" x2="37.7896" y2="78.8172" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.7612" y1="34.2392" x2="20.9804" y2="42.0116" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="19.9136" y1="32.1056" x2="19.7612" y2="34.2392" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3416" y1="32.1056" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="15.3924" y1="30.4038" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.9728" y1="32.766" x2="15.3416" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="13.5128" y1="34.544" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="31.496" x2="19.9136" y2="32.1056" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="24.7904" y1="28.9052" x2="24.7904" y2="31.496" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="25.7302" y1="28.829" x2="24.7904" y2="28.9052" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="29.718" y1="31.3944" x2="25.7302" y2="28.829" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="7.0104" y1="37.6428" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.16" y1="41.2496" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="34.798" y1="30.1244" x2="29.8336" y2="31.51" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="36.0934" y1="30.1244" x2="34.8234" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="37.3634" y1="28.4086" x2="36.0934" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.6334" y1="30.099" x2="37.3634" y2="30.099" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="39.9034" y1="28.4086" x2="38.6334" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="33.3134" y1="24.3586" x2="34.8234" y2="28.4086" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="31.1912" y1="22.2504" x2="31.9278" y2="24.3586" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="28.956" y1="16.3462" x2="31.623" y2="21.8186" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="38.608" y1="11.9888" x2="33.3134" y2="15.4686" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.4688" y1="14.1224" x2="38.6334" y2="11.9634" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="14.1224" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="14.1224" x2="43.688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.228" y1="14.1224" x2="44.958" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="48.1076" y1="14.1224" x2="46.228" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="42.418" y1="19.8628" x2="42.4688" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="43.688" y1="19.9136" x2="42.418" y2="19.8628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="44.958" y1="19.9136" x2="43.688" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="46.2788" y1="19.9136" x2="44.958" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="54.102" y1="12.6492" x2="48.1076" y2="14.1224" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.6534" y1="15.4686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.1952" y1="17.1704" x2="61.214" y2="15.4572" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="18.1864" x2="63.1952" y2="17.1704" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="65.5828" y1="16.7132" x2="65.3288" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="62.992" y1="19.9136" x2="63.8048" y2="18.1864" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="67.7672" y1="15.2908" x2="65.5828" y2="15.3192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="58.5216" y1="19.9644" x2="62.992" y2="19.9136" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="52.6034" y1="5.0686" x2="54.102" y2="12.6492" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="56.2356" y1="3.7592" x2="52.6034" y2="3.683" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="59.2836" y1="3.7592" x2="56.2356" y2="3.7592" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="9.9314" y1="24.7142" x2="15.3924" y2="30.4038" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="16.8656" x2="9.9314" y2="24.7142" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="10.3124" y1="13.8176" x2="10.3124" y2="16.8656" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7169,12 +7182,7 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="63.3476" y1="33.4772" x2="62.4332" y2="35.1536" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="63.8048" y1="31.1912" x2="63.6016" y2="33.2232" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.3412" y1="83.2104" x2="78.473" y2="83.3436" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.8652" y1="72.9996" x2="78.473" y2="72.828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.5604" y1="62.9412" x2="89.8652" y2="72.9996" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="62.7888" x2="89.5604" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.8652" y1="52.8828" x2="89.5604" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.5604" y1="42.672" x2="89.8652" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.5604" y1="22.2504" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.5604" y1="22.2504" x2="91.5416" y2="32.3088" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="15.9512" x2="89.5604" y2="22.2504" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="87.63" y1="13.4112" x2="87.63" y2="15.9512" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="88.3412" y1="12.192" x2="87.63" y2="13.4112" width="0" layer="19" extent="1-1"/>
|
||||
|
|
@ -7182,6 +7190,11 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="91.6432" y1="2.3368" x2="91.694" y2="12.3444" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.6432" y1="1.2192" x2="91.6432" y2="2.3368" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="90.2716" y1="1.2192" x2="91.6432" y2="1.2192" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.5604" y1="42.672" x2="88.1888" y2="32.4612" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.8652" y1="52.8828" x2="89.5604" y2="42.672" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="91.5416" y1="62.7888" x2="89.8652" y2="52.8828" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.5604" y1="62.9412" x2="91.5416" y2="62.7888" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="89.8652" y1="72.9996" x2="89.5604" y2="62.9412" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="97.9932" x2="1.8288" y2="83.3628" width="0" layer="19" extent="1-1"/>
|
||||
<wire x1="1.016" y1="98.9076" x2="1.016" y2="97.9932" width="0" layer="19" extent="1-1"/>
|
||||
</signal>
|
||||
|
|
@ -7723,9 +7736,9 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<signal name="AMIGA_A23">
|
||||
<contactref element="IC2" pad="52"/>
|
||||
<contactref element="IC9" pad="17"/>
|
||||
<wire x1="1.9304" y1="32.7406" x2="3.81" y2="34.6202" width="0.1524" layer="1"/>
|
||||
<wire x1="3.81" y1="34.6202" x2="3.81" y2="43.8912" width="0.1524" layer="1"/>
|
||||
<wire x1="3.81" y1="43.8912" x2="4.4958" y2="44.577" width="0.1524" layer="1"/>
|
||||
<wire x1="1.9304" y1="32.7406" x2="3.5052" y2="34.3154" width="0.1524" layer="1"/>
|
||||
<wire x1="3.5052" y1="34.3154" x2="3.5052" y2="43.5864" width="0.1524" layer="1"/>
|
||||
<wire x1="3.5052" y1="43.5864" x2="4.4958" y2="44.577" width="0.1524" layer="1"/>
|
||||
<wire x1="4.4958" y1="44.577" x2="5.1816" y2="44.577" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="AMIGA_D0">
|
||||
|
|
@ -8256,6 +8269,22 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
|
|||
<wire x1="7.1628" y1="72.6948" x2="6.5532" y2="72.6948" width="0.1524" layer="1"/>
|
||||
<wire x1="6.5532" y1="72.6948" x2="6.096" y2="72.2376" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="N$3">
|
||||
<contactref element="IC9" pad="18"/>
|
||||
<contactref element="R26" pad="1"/>
|
||||
<wire x1="5.1816" y1="43.307" x2="4.2926" y2="43.307" width="0.1524" layer="1"/>
|
||||
<wire x1="4.2926" y1="43.307" x2="3.81" y2="42.8244" width="0.1524" layer="1"/>
|
||||
<wire x1="3.81" y1="42.8244" x2="3.81" y2="36.488" width="0.1524" layer="1"/>
|
||||
<wire x1="3.81" y1="36.488" x2="5.0936" y2="35.2044" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
<signal name="N$4">
|
||||
<contactref element="R27" pad="2"/>
|
||||
<contactref element="IC9" pad="2"/>
|
||||
<wire x1="15.24" y1="42.037" x2="13.9954" y2="42.037" width="0.1524" layer="1"/>
|
||||
<wire x1="13.9954" y1="42.037" x2="13.716" y2="41.7576" width="0.1524" layer="1"/>
|
||||
<wire x1="13.716" y1="41.7576" x2="13.716" y2="38.774" width="0.1524" layer="1"/>
|
||||
<wire x1="13.716" y1="38.774" x2="14.2376" y2="38.2524" width="0.1524" layer="1"/>
|
||||
</signal>
|
||||
</signals>
|
||||
</board>
|
||||
</drawing>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -10126,6 +10126,8 @@ Source: RS Component / Phycomp</description>
|
|||
<part name="R23" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R24" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R25" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
|
||||
<part name="R26" library="rcl" deviceset="R-EU_" device="R0603" value="4,7K"/>
|
||||
<part name="R27" library="rcl" deviceset="R-EU_" device="R0603" value="4,7K"/>
|
||||
</parts>
|
||||
<sheets>
|
||||
<sheet>
|
||||
|
|
@ -13425,6 +13427,8 @@ Source: RS Component / Phycomp</description>
|
|||
<instance part="RN8" gate="B" x="96.52" y="162.56"/>
|
||||
<instance part="RN8" gate="C" x="96.52" y="157.48"/>
|
||||
<instance part="RN8" gate="D" x="96.52" y="152.4"/>
|
||||
<instance part="R26" gate="G$1" x="20.32" y="91.44"/>
|
||||
<instance part="R27" gate="G$1" x="35.56" y="91.44"/>
|
||||
</instances>
|
||||
<busses>
|
||||
<bus name="A[0..31]">
|
||||
|
|
@ -13835,11 +13839,6 @@ Source: RS Component / Phycomp</description>
|
|||
<wire x1="101.6" y1="162.56" x2="101.6" y2="167.64" width="0.1524" layer="91"/>
|
||||
<junction x="101.6" y="162.56"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="IC9" gate="A" pin="A1"/>
|
||||
<wire x1="40.64" y1="86.36" x2="43.18" y2="86.36" width="0.1524" layer="91"/>
|
||||
<label x="43.18" y="86.36" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="VCC" class="0">
|
||||
<segment>
|
||||
|
|
@ -13891,6 +13890,15 @@ Source: RS Component / Phycomp</description>
|
|||
<wire x1="208.28" y1="119.38" x2="208.28" y2="124.46" width="0.1524" layer="91"/>
|
||||
<junction x="208.28" y="124.46"/>
|
||||
</segment>
|
||||
<segment>
|
||||
<pinref part="R26" gate="G$1" pin="2"/>
|
||||
<pinref part="R27" gate="G$1" pin="1"/>
|
||||
<wire x1="25.4" y1="91.44" x2="27.94" y2="91.44" width="0.1524" layer="91"/>
|
||||
<wire x1="27.94" y1="91.44" x2="30.48" y2="91.44" width="0.1524" layer="91"/>
|
||||
<wire x1="27.94" y1="91.44" x2="27.94" y2="93.98" width="0.1524" layer="91"/>
|
||||
<junction x="27.94" y="91.44"/>
|
||||
<label x="27.94" y="93.98" size="1.27" layer="95"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="AMIGA_BUS_ENABLE_HIGH" class="0">
|
||||
<segment>
|
||||
|
|
@ -14651,6 +14659,20 @@ Source: RS Component / Phycomp</description>
|
|||
<label x="88.9" y="25.4" size="1.27" layer="95" rot="R180"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="N$3" class="0">
|
||||
<segment>
|
||||
<pinref part="IC9" gate="A" pin="B1"/>
|
||||
<pinref part="R26" gate="G$1" pin="1"/>
|
||||
<wire x1="15.24" y1="86.36" x2="15.24" y2="91.44" width="0.1524" layer="91"/>
|
||||
</segment>
|
||||
</net>
|
||||
<net name="N$4" class="0">
|
||||
<segment>
|
||||
<pinref part="R27" gate="G$1" pin="2"/>
|
||||
<pinref part="IC9" gate="A" pin="A1"/>
|
||||
<wire x1="40.64" y1="91.44" x2="40.64" y2="86.36" width="0.1524" layer="91"/>
|
||||
</segment>
|
||||
</net>
|
||||
</nets>
|
||||
</sheet>
|
||||
</sheets>
|
||||
|
|
|
|||
|
|
@ -1,636 +0,0 @@
|
|||
-- Copyright: Matthias Heinrichs 2014
|
||||
-- Free for non-comercial use
|
||||
-- No warranty just for fun
|
||||
-- If you want to earn money with this code, ask me first!
|
||||
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
RW_000: inout std_logic ;
|
||||
DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: in std_logic_vector ( 31 downto 16 );
|
||||
A0: inout std_logic;
|
||||
A1: in std_logic;
|
||||
nEXP_SPACE: in std_logic ;
|
||||
BERR: inout std_logic ;
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
FPU_SENSE: in std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK1: inout std_logic;
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: inout std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_ADDR_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
AMIGA_BUS_ENABLE_HIGH: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||
|
||||
constant IDLE_P : AMIGA_STATE := "000";
|
||||
constant IDLE_N : AMIGA_STATE := "001";
|
||||
constant AS_SET_P : AMIGA_STATE := "010";
|
||||
constant AS_SET_N : AMIGA_STATE := "011";
|
||||
constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
|
||||
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||
constant DATA_FETCH_P : AMIGA_STATE := "110";
|
||||
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE;
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal AS_000_INT:STD_LOGIC := '1';
|
||||
signal RW_000_INT:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1';
|
||||
signal AS_030_D0:STD_LOGIC := '1';
|
||||
signal nEXP_SPACE_D0:STD_LOGIC := '1';
|
||||
signal DS_030_D0:STD_LOGIC := '1';
|
||||
signal AS_030_000_SYNC:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT_D:STD_LOGIC := '1';
|
||||
signal AS_000_DMA:STD_LOGIC := '1';
|
||||
signal DS_000_DMA:STD_LOGIC := '1';
|
||||
signal RW_000_DMA:STD_LOGIC := '1';
|
||||
signal CYCLE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
|
||||
signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal A0_DMA: STD_LOGIC := '1';
|
||||
signal VMA_INT: STD_LOGIC := '1';
|
||||
signal VPA_D: STD_LOGIC := '1';
|
||||
signal UDS_000_INT: STD_LOGIC := '1';
|
||||
signal LDS_000_INT: STD_LOGIC := '1';
|
||||
signal DS_000_ENABLE: STD_LOGIC := '0';
|
||||
signal DSACK1_INT: STD_LOGIC := '1';
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE_50: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_50_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_25: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33_D: STD_LOGIC := '1';
|
||||
signal CLK_PRE_66:STD_LOGIC := '0';
|
||||
signal CLK_OUT_PRE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_NE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_INT: STD_LOGIC := '1';
|
||||
signal CLK_030_H: STD_LOGIC := '1';
|
||||
signal CLK_000_D0: STD_LOGIC := '1';
|
||||
signal CLK_000_D1: STD_LOGIC := '1';
|
||||
signal CLK_000_D2: STD_LOGIC := '1';
|
||||
signal CLK_000_D3: STD_LOGIC := '1';
|
||||
signal CLK_000_D4: STD_LOGIC := '1';
|
||||
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_PE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE_D0: STD_LOGIC := '0';
|
||||
signal DTACK_D0: STD_LOGIC := '1';
|
||||
signal RESET_DLY: STD_LOGIC_VECTOR ( 5 downto 0 ) := "000000";
|
||||
signal RESET_OUT: STD_LOGIC := '0';
|
||||
signal DS_DMA: STD_LOGIC := '0';
|
||||
signal CLK_030_D0: STD_LOGIC := '0';
|
||||
--signal NO_RESET: STD_LOGIC := '0';
|
||||
|
||||
begin
|
||||
|
||||
--pos edge clock
|
||||
pos_clk: process(CLK_OSZI)
|
||||
begin
|
||||
if(false ) then
|
||||
CLK_OUT_PRE_50 <= '0';
|
||||
CLK_OUT_PRE_50_D<= '0';
|
||||
--CLK_OUT_PRE_25 <= '0';
|
||||
--CLK_OUT_PRE <= '0';
|
||||
CLK_OUT_PRE_D <= '0';
|
||||
--CLK_OUT_NE <= '0';
|
||||
--CLK_OUT_INT <= '0';
|
||||
CLK_000_D0 <= '0';
|
||||
CLK_000_D1 <= '0';
|
||||
CLK_000_D2 <= '0';
|
||||
CLK_000_D3 <= '0';
|
||||
CLK_000_D4 <= '0';
|
||||
CLK_000_P_SYNC <= "0000000000000";
|
||||
CLK_000_N_SYNC <= "0000000000000";
|
||||
CLK_000_NE_D0 <= '0';
|
||||
cpu_est <= E20;
|
||||
CLK_030_D0 <='0';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--clk generation :
|
||||
CLK_030_D0 <=CLK_030;
|
||||
CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_50_D<= CLK_OUT_PRE_50;
|
||||
|
||||
--if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
|
||||
-- CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25;
|
||||
--end if;
|
||||
|
||||
--here the clock is selected
|
||||
--CLK_OUT_PRE <= CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_D <= CLK_OUT_PRE_50;
|
||||
|
||||
--a negative edge is comming next cycle
|
||||
--if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then
|
||||
-- CLK_OUT_NE <= '1';
|
||||
--else
|
||||
-- CLK_OUT_NE <= '0';
|
||||
--end if;
|
||||
-- the external clock to the processor is generated here
|
||||
--CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
--delayed Clocks and signals for edge detection
|
||||
CLK_000_D0 <= CLK_000;
|
||||
CLK_000_D1 <= CLK_000_D0;
|
||||
CLK_000_D2 <= CLK_000_D1;
|
||||
CLK_000_D3 <= CLK_000_D2;
|
||||
CLK_000_D4 <= CLK_000_D3;
|
||||
|
||||
--shift registers for edge detection
|
||||
CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 );
|
||||
CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1;
|
||||
CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 );
|
||||
CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1;
|
||||
|
||||
-- values are determined empiracally for 7.09 MHz Clock
|
||||
-- since the clock is not symmetrically these values differ!
|
||||
CLK_000_PE <= CLK_000_P_SYNC(9);
|
||||
CLK_000_NE <= CLK_000_N_SYNC(11);
|
||||
CLK_000_NE_D0 <= CLK_000_NE;
|
||||
|
||||
-- e-clock is changed on the FALLING edge!
|
||||
|
||||
if(CLK_000_NE_D0 = '1' ) then
|
||||
--if(CLK_000_D0='0' AND CLK_000_D1='1') then
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process pos_clk;
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_PRE_D;
|
||||
CLK_EXP <= CLK_OUT_PRE_D;
|
||||
--NO_RESET <= '1';
|
||||
|
||||
-- i need to delay the board reset by some eclocks, so everything is synced fine afeter a soft reset!
|
||||
reset_delay_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
RESET_DLY <= "000000";
|
||||
RESET_OUT <= '0';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset delay: wait 128 E-Clocks!
|
||||
if(CLK_000_NE = '1' and cpu_est = E1) then
|
||||
RESET_DLY <= RESET_DLY +1;
|
||||
end if;
|
||||
end if;
|
||||
--reset buffer
|
||||
if(RESET_DLY="111111")then
|
||||
RESET_OUT <= '1';
|
||||
end if;
|
||||
end process reset_delay_machine;
|
||||
|
||||
--the state machine
|
||||
state_machine: process(RESET_OUT, CLK_OSZI)
|
||||
begin
|
||||
if(RESET_OUT = '0' ) then
|
||||
VPA_D <= '1';
|
||||
DTACK_D0 <= '1';
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
RW_000_DMA <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
CLK_REF <= "00";
|
||||
VMA_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
BGACK_030_INT_D <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
IPL_030 <= "111";
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
AS_030_D0 <= '1';
|
||||
nEXP_SPACE_D0 <= '1';
|
||||
DS_030_D0 <= '1';
|
||||
CLK_030_H <= '0';
|
||||
CYCLE_DMA <= "00";
|
||||
DS_DMA <= '1';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
|
||||
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
--buffering signals
|
||||
AS_030_D0 <= AS_030;
|
||||
nEXP_SPACE_D0 <= nEXP_SPACE;
|
||||
DS_030_D0 <= DS_030;
|
||||
DTACK_D0 <= DTACK;
|
||||
VPA_D <= VPA;
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif ( BGACK_000='1'
|
||||
AND CLK_000_PE='1'
|
||||
--AND CLK_000_D0='1' and CLK_000_D1='0'
|
||||
) then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
BGACK_030_INT_D <= BGACK_030_INT;
|
||||
|
||||
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
|
||||
and CLK_000_D0='1'
|
||||
--and CLK_000_D0='1' AND CLK_000_D1='0'
|
||||
) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
if(CLK_000_NE='1')then
|
||||
--if(CLK_000_D0='0' and CLK_000_D1='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
|
||||
if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
AS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
RW_000_INT <= '1';
|
||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030_D0 = '0' AND --as set
|
||||
BGACK_000='1' AND --no dma -cycle
|
||||
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
||||
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
|
||||
SM_AMIGA = IDLE_P --last amiga cycle terminated
|
||||
) then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
-- VMA generation
|
||||
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
--if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
--uds/lds precalculation
|
||||
if (DS_030_D0 = '0' AND SM_AMIGA = IDLE_N) then --DS: set udl/lds
|
||||
if(A0='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
--Amiga statemachine
|
||||
|
||||
if(BERR='0')then --"async" reset on errors
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
RW_000_INT <= '1';
|
||||
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||
SM_AMIGA<=IDLE_N; --go to s1
|
||||
else
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
if(CLK_000_PE='1')then --go to s2
|
||||
--if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
RW_000_INT <= RW;
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
if(CLK_000_NE='1')then --go to s3
|
||||
--if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||
|
||||
if(CLK_000_PE='1')then --go to s4
|
||||
--if(CLK_000_D0='1')then --go to s4
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
if( CLK_000_NE='1' and --falling edge
|
||||
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
|
||||
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
|
||||
(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
|
||||
)then --go to s5
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000_PE = '1')then --go to s6
|
||||
--if(CLK_000_D0='1')then --go to s6
|
||||
SM_AMIGA<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( (CLK_000_N_SYNC( 9)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
|
||||
(CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
|
||||
DSACK1_INT <='0';
|
||||
end if;
|
||||
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
-- DSACK1_INT <='0';
|
||||
--end if;
|
||||
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--DSACK1_INT <='0';
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
|
||||
if(CLK_000_PE='1')then --go to s0
|
||||
--if(CLK_000_D0='1')then --go to s0
|
||||
SM_AMIGA<=IDLE_P;
|
||||
RW_000_INT <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
--DMA-Bus handling
|
||||
if(BGACK_030_INT='0')then
|
||||
--switch amiga bus on for DMA-Cycles
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;
|
||||
-- set some signals continuesly
|
||||
RW_000_DMA <= RW_000;
|
||||
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
|
||||
if(UDS_000='0' and LDS_000='0') then
|
||||
SIZE_DMA <= "10"; --16bit
|
||||
else
|
||||
SIZE_DMA <= "01"; --8 bit
|
||||
end if;
|
||||
|
||||
--now calculate the offset:
|
||||
--if uds is set low, a0 is so too.
|
||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
||||
|
||||
--A1 is set by the amiga side
|
||||
--here we determine the upper or lower half of the databus
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= A1;
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= not A1;
|
||||
|
||||
|
||||
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
AMIGA_BUS_ENABLE_INT <= '1' ;
|
||||
RW_000_DMA <= '1';
|
||||
SIZE_DMA <= "00";
|
||||
A0_DMA <= '0';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
end if;
|
||||
|
||||
if((UDS_000='0' or LDS_000='0') and BGACK_030_INT='0')then
|
||||
DS_DMA <= '0';
|
||||
else
|
||||
DS_DMA <= '1';
|
||||
end if;
|
||||
|
||||
|
||||
if(BGACK_030_INT='0' and AS_000='0')then
|
||||
-- an 68000-memory cycle is three positive edges long!
|
||||
if(CLK_000_P_SYNC(10)='1')then
|
||||
CYCLE_DMA <= CYCLE_DMA+1;
|
||||
end if;
|
||||
else
|
||||
CYCLE_DMA <= "00";
|
||||
end if;
|
||||
|
||||
--dma stuff
|
||||
--as can only be done if we know the uds/lds!
|
||||
if( BGACK_030_INT='0'
|
||||
--and AS_000='0'
|
||||
and DS_DMA ='0'
|
||||
--and (UDS_000='0' or LDS_000='0')
|
||||
and (
|
||||
|
||||
--CYCLE_DMA ="00" or
|
||||
--CYCLE_DMA ="01" or
|
||||
CYCLE_DMA ="10" or
|
||||
CYCLE_DMA ="11"
|
||||
)
|
||||
)then
|
||||
|
||||
|
||||
--set AS_000
|
||||
if( CLK_030='0' and CLK_030_D0='1') then
|
||||
AS_000_DMA <= '0'; --sampled on rising edges!
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <='0';
|
||||
else
|
||||
DS_000_DMA <= AS_000_DMA;
|
||||
end if;
|
||||
end if;
|
||||
|
||||
else
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
|
||||
--RESET <= 'Z' when RESET_OUT ='1' else '0';
|
||||
RESET <= RESET_OUT;
|
||||
|
||||
-- bus drivers
|
||||
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE
|
||||
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
||||
'1';
|
||||
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
|
||||
'1';
|
||||
|
||||
|
||||
AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
|
||||
'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
|
||||
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
|
||||
'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
|
||||
'0'; --Point towarts TK
|
||||
|
||||
|
||||
--dma stuff
|
||||
DTACK <= 'Z';
|
||||
--DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
-- '0' when DSACK1 ='0' else
|
||||
-- '1';
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
'0' when AS_000_DMA ='0' and AS_000 ='0' else
|
||||
'1';
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
'0' when DS_000_DMA ='0' and AS_000 ='0' else
|
||||
'1';
|
||||
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
'0' when A0_DMA ='0' else
|
||||
'1';
|
||||
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
"10" when SIZE_DMA ="10" else
|
||||
"01" when SIZE_DMA ="01" else
|
||||
"00";
|
||||
--rw
|
||||
RW <= 'Z' when BGACK_030_INT ='1' else
|
||||
'0' when RW_000_DMA ='0' else
|
||||
'1';
|
||||
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
|
||||
--fpu
|
||||
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
|
||||
else '1';
|
||||
|
||||
--if no copro is installed:
|
||||
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
|
||||
else 'Z';
|
||||
--BERR <= 'Z';
|
||||
|
||||
|
||||
|
||||
--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
|
||||
'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
|
||||
'0'; --off for the Amiga
|
||||
|
||||
|
||||
--e and VMA
|
||||
E <= cpu_est(3);
|
||||
VMA <= VMA_INT;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
'0' when AS_000_INT ='0' and AS_030 ='0' else
|
||||
'1';
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
'0' when RW_000_INT ='0' else
|
||||
'1';
|
||||
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
'0' when UDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
|
||||
'1';
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
'0' when LDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
|
||||
'1';
|
||||
|
||||
--dsack
|
||||
DSACK1 <= 'Z' when nEXP_SPACE_D0 = '0' else -- output on amiga cycle
|
||||
'0' when DSACK1_INT ='0' else
|
||||
'1';
|
||||
|
||||
end Behavioral;
|
||||
|
|
@ -1,582 +0,0 @@
|
|||
-- Copyright: Matthias Heinrichs 2014
|
||||
-- Free for non-comercial use
|
||||
-- No warranty just for fun
|
||||
-- If you want to earn money with this code, ask me first!
|
||||
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
|
||||
entity BUS68030 is
|
||||
|
||||
port(
|
||||
AS_030: inout std_logic ;
|
||||
AS_000: inout std_logic ;
|
||||
RW_000: inout std_logic ;
|
||||
DS_030: inout std_logic ;
|
||||
UDS_000: inout std_logic;
|
||||
LDS_000: inout std_logic;
|
||||
SIZE: inout std_logic_vector ( 1 downto 0 );
|
||||
A: in std_logic_vector ( 31 downto 16 );
|
||||
A0: inout std_logic;
|
||||
A1: in std_logic;
|
||||
nEXP_SPACE: in std_logic ;
|
||||
BERR: inout std_logic ;
|
||||
BG_030: in std_logic ;
|
||||
BG_000: out std_logic ;
|
||||
BGACK_030: out std_logic ;
|
||||
BGACK_000: in std_logic ;
|
||||
CLK_030: in std_logic ;
|
||||
CLK_000: in std_logic ;
|
||||
CLK_OSZI: in std_logic ;
|
||||
CLK_DIV_OUT: out std_logic ;
|
||||
CLK_EXP: out std_logic ;
|
||||
FPU_CS: out std_logic ;
|
||||
FPU_SENSE: in std_logic ;
|
||||
IPL_030: out std_logic_vector ( 2 downto 0 );
|
||||
IPL: in std_logic_vector ( 2 downto 0 );
|
||||
DSACK1: inout std_logic;
|
||||
DTACK: inout std_logic ;
|
||||
AVEC: out std_logic ;
|
||||
E: out std_logic ;
|
||||
VPA: in std_logic ;
|
||||
VMA: out std_logic ;
|
||||
RST: in std_logic ;
|
||||
RESET: out std_logic ;
|
||||
RW: inout std_logic ;
|
||||
-- D: inout std_logic_vector ( 31 downto 28 );
|
||||
FC: in std_logic_vector ( 1 downto 0 );
|
||||
AMIGA_ADDR_ENABLE: out std_logic ;
|
||||
AMIGA_BUS_DATA_DIR: out std_logic ;
|
||||
AMIGA_BUS_ENABLE_LOW: out std_logic;
|
||||
AMIGA_BUS_ENABLE_HIGH: out std_logic;
|
||||
CIIN: out std_logic
|
||||
);
|
||||
end BUS68030;
|
||||
|
||||
architecture Behavioral of BUS68030 is
|
||||
|
||||
|
||||
subtype ESTATE is std_logic_vector(3 downto 0);
|
||||
|
||||
constant E1 : ESTATE := "0110";
|
||||
constant E2 : ESTATE := "0111";
|
||||
constant E3 : ESTATE := "0100";
|
||||
constant E4 : ESTATE := "0101";
|
||||
constant E5 : ESTATE := "0010";
|
||||
constant E6 : ESTATE := "0011";
|
||||
constant E7 : ESTATE := "1010";
|
||||
constant E8 : ESTATE := "1011";
|
||||
constant E9 : ESTATE := "1100";
|
||||
constant E10 : ESTATE := "1111";
|
||||
-- Illegal states
|
||||
constant E20 : ESTATE := "0000";
|
||||
constant E4a : ESTATE := "0001";
|
||||
constant E21 : ESTATE := "1000";
|
||||
constant E22 : ESTATE := "1001";
|
||||
constant E23 : ESTATE := "1101";
|
||||
constant E24 : ESTATE := "1110";
|
||||
|
||||
signal cpu_est : ESTATE;
|
||||
|
||||
subtype AMIGA_STATE is std_logic_vector(2 downto 0);
|
||||
|
||||
constant IDLE_P : AMIGA_STATE := "000";
|
||||
constant IDLE_N : AMIGA_STATE := "001";
|
||||
constant AS_SET_P : AMIGA_STATE := "010";
|
||||
constant AS_SET_N : AMIGA_STATE := "011";
|
||||
constant SAMPLE_DTACK_P: AMIGA_STATE := "100";
|
||||
constant DATA_FETCH_N: AMIGA_STATE := "101";
|
||||
constant DATA_FETCH_P : AMIGA_STATE := "110";
|
||||
constant END_CYCLE_N : AMIGA_STATE := "111";
|
||||
|
||||
signal SM_AMIGA : AMIGA_STATE;
|
||||
|
||||
--signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
|
||||
signal AS_000_INT:STD_LOGIC := '1';
|
||||
signal RW_000_INT:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1';
|
||||
signal AS_030_D0:STD_LOGIC := '1';
|
||||
signal nEXP_SPACE_D0:STD_LOGIC := '1';
|
||||
signal DS_030_D0:STD_LOGIC := '1';
|
||||
signal AS_030_000_SYNC:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT_D:STD_LOGIC := '1';
|
||||
signal AS_000_DMA:STD_LOGIC := '1';
|
||||
signal DS_000_DMA:STD_LOGIC := '1';
|
||||
signal RW_000_DMA:STD_LOGIC := '1';
|
||||
signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
|
||||
signal A0_DMA: STD_LOGIC := '1';
|
||||
signal VMA_INT: STD_LOGIC := '1';
|
||||
signal VPA_D: STD_LOGIC := '1';
|
||||
signal UDS_000_INT: STD_LOGIC := '1';
|
||||
signal LDS_000_INT: STD_LOGIC := '1';
|
||||
signal DS_000_ENABLE: STD_LOGIC := '0';
|
||||
signal DSACK1_INT: STD_LOGIC := '1';
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE_50: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_50_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_25: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33_D: STD_LOGIC := '1';
|
||||
signal CLK_PRE_66:STD_LOGIC := '0';
|
||||
signal CLK_OUT_PRE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_NE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_INT: STD_LOGIC := '1';
|
||||
signal CLK_030_H: STD_LOGIC := '1';
|
||||
signal CLK_000_D0: STD_LOGIC := '1';
|
||||
signal CLK_000_D1: STD_LOGIC := '1';
|
||||
signal CLK_000_D2: STD_LOGIC := '1';
|
||||
signal CLK_000_D3: STD_LOGIC := '1';
|
||||
signal CLK_000_D4: STD_LOGIC := '1';
|
||||
signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000";
|
||||
signal CLK_000_PE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE_D0: STD_LOGIC := '0';
|
||||
signal DTACK_D0: STD_LOGIC := '1';
|
||||
signal RESET_DLY: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000";
|
||||
|
||||
begin
|
||||
|
||||
--pos edge clock
|
||||
pos_clk: process(CLK_OSZI)
|
||||
begin
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
--clk generation :
|
||||
|
||||
CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_50_D<= CLK_OUT_PRE_50;
|
||||
|
||||
if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
|
||||
CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25;
|
||||
end if;
|
||||
|
||||
--here the clock is selected
|
||||
CLK_OUT_PRE <= CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_D <= CLK_OUT_PRE;
|
||||
|
||||
--a negative edge is comming next cycle
|
||||
if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then
|
||||
CLK_OUT_NE <= '1';
|
||||
else
|
||||
CLK_OUT_NE <= '0';
|
||||
end if;
|
||||
-- the external clock to the processor is generated here
|
||||
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
--delayed Clocks and signals for edge detection
|
||||
CLK_000_D0 <= CLK_000;
|
||||
CLK_000_D1 <= CLK_000_D0;
|
||||
CLK_000_D2 <= CLK_000_D1;
|
||||
CLK_000_D3 <= CLK_000_D2;
|
||||
CLK_000_D4 <= CLK_000_D3;
|
||||
|
||||
--shift registers for edge detection
|
||||
CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 );
|
||||
CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1;
|
||||
CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 );
|
||||
CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1;
|
||||
|
||||
-- values are determined empiracally for 7.09 MHz Clock
|
||||
-- since the clock is not symmetrically these values differ!
|
||||
CLK_000_PE <= CLK_000_P_SYNC(9);
|
||||
CLK_000_NE <= CLK_000_N_SYNC(11);
|
||||
CLK_000_NE_D0 <= CLK_000_NE;
|
||||
|
||||
-- e-clock is changed on the FALLING edge!
|
||||
|
||||
if(CLK_000_NE_D0 = '1' ) then
|
||||
--if(CLK_000_D0='0' AND CLK_000_D1='1') then
|
||||
case (cpu_est) is
|
||||
when E1 => cpu_est <= E2 ;
|
||||
when E2 => cpu_est <= E3 ;
|
||||
when E3 => cpu_est <= E4;
|
||||
when E4 => cpu_est <= E5 ;
|
||||
when E5 => cpu_est <= E6 ;
|
||||
when E6 => cpu_est <= E7 ;
|
||||
when E7 => cpu_est <= E8 ;
|
||||
when E8 => cpu_est <= E9 ;
|
||||
when E9 => cpu_est <= E10;
|
||||
when E10 => cpu_est <= E1 ;
|
||||
-- Illegal states
|
||||
when E4a => cpu_est <= E5 ;
|
||||
when E20 => cpu_est <= E10;
|
||||
when E21 => cpu_est <= E10;
|
||||
when E22 => cpu_est <= E9 ;
|
||||
when E23 => cpu_est <= E9 ;
|
||||
when E24 => cpu_est <= E10;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process pos_clk;
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_PRE_D;
|
||||
CLK_EXP <= CLK_OUT_PRE_D;
|
||||
|
||||
-- i need to delay the board reset by some eclocks, so everything is synced fine afeter a soft reset!
|
||||
reset_delay_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
RESET_DLY <= "00000000";
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset delay: wait 128 E-Clocks!
|
||||
if(CLK_000_NE_D0 = '1' and cpu_est = E1) then
|
||||
RESET_DLY <= RESET_DLY +1;
|
||||
end if;
|
||||
end if;
|
||||
end process reset_delay_machine;
|
||||
|
||||
--the state machine
|
||||
state_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
RESET <= '0';
|
||||
VPA_D <= '1';
|
||||
DTACK_D0 <= '1';
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
RW_000_DMA <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
CLK_REF <= "00";
|
||||
VMA_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
BGACK_030_INT_D <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
IPL_030 <= "111";
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
AS_030_D0 <= '1';
|
||||
nEXP_SPACE_D0 <= '1';
|
||||
DS_030_D0 <= '1';
|
||||
CLK_030_H <= '0';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset buffer
|
||||
if(RESET_DLY="01111111")then
|
||||
RESET <= '1';
|
||||
end if;
|
||||
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
--buffering signals
|
||||
AS_030_D0 <= AS_030;
|
||||
nEXP_SPACE_D0 <= nEXP_SPACE;
|
||||
DS_030_D0 <= DS_030;
|
||||
DTACK_D0 <= DTACK;
|
||||
VPA_D <= VPA;
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif ( BGACK_000='1'
|
||||
AND CLK_000_PE='1'
|
||||
--AND CLK_000_D0='1' and CLK_000_D1='0'
|
||||
) then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
BGACK_030_INT_D <= BGACK_030_INT;
|
||||
|
||||
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
|
||||
and CLK_000_D0='1'
|
||||
--and CLK_000_D0='1' AND CLK_000_D1='0'
|
||||
) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
if(CLK_000_NE='1')then
|
||||
--if(CLK_000_D0='0' and CLK_000_D1='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
|
||||
if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
AS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
RW_000_INT <= '1';
|
||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030_D0 = '0' AND --as set
|
||||
BGACK_000='1' AND --no dma -cycle
|
||||
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
||||
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
|
||||
SM_AMIGA = IDLE_P --last amiga cycle terminated
|
||||
) then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
-- VMA generation
|
||||
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
--if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
--uds/lds precalculation
|
||||
if (DS_030_D0 = '0' AND SM_AMIGA = IDLE_N) then --DS: set udl/lds
|
||||
if(A0='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
--Amiga statemachine
|
||||
|
||||
if(BERR='0')then --"async" reset on errors
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
RW_000_INT <= '1';
|
||||
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||
SM_AMIGA<=IDLE_N; --go to s1
|
||||
else
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
if(CLK_000_PE='1')then --go to s2
|
||||
--if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
RW_000_INT <= RW;
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
if(CLK_000_NE='1')then --go to s3
|
||||
--if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||
|
||||
if(CLK_000_PE='1')then --go to s4
|
||||
--if(CLK_000_D0='1')then --go to s4
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
if( CLK_000_NE='1' and --falling edge
|
||||
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
|
||||
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
|
||||
(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
|
||||
)then --go to s5
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000_PE = '1')then --go to s6
|
||||
--if(CLK_000_D0='1')then --go to s6
|
||||
SM_AMIGA<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( (CLK_000_N_SYNC( 8)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
|
||||
(CLK_000_N_SYNC( 9)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
|
||||
DSACK1_INT <='0';
|
||||
end if;
|
||||
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
-- DSACK1_INT <='0';
|
||||
--end if;
|
||||
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--DSACK1_INT <='0';
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
|
||||
if(CLK_000_PE='1')then --go to s0
|
||||
--if(CLK_000_D0='1')then --go to s0
|
||||
SM_AMIGA<=IDLE_P;
|
||||
RW_000_INT <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
if(BGACK_030_INT='0')then
|
||||
--switch amiga bus on for DMA-Cycles
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;
|
||||
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
AMIGA_BUS_ENABLE_INT <= '1' ;
|
||||
end if;
|
||||
|
||||
--dma stuff
|
||||
--as can only be done if we know the uds/lds!
|
||||
if(BGACK_030_INT='0' and AS_000='0' and (UDS_000='0' or LDS_000='0'))then
|
||||
RW_000_DMA <= RW_000;
|
||||
--set AS_000
|
||||
if( CLK_030='1') then
|
||||
AS_000_DMA <= '0'; --sampled on rising edges!
|
||||
end if;
|
||||
|
||||
--delayed clock for write cycle
|
||||
if(AS_000_DMA = '0' and CLK_030='0')then
|
||||
CLK_030_H <= '1';
|
||||
end if;
|
||||
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <='0';
|
||||
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
|
||||
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
|
||||
end if;
|
||||
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
|
||||
if(UDS_000='0' and LDS_000='0') then
|
||||
SIZE_DMA <= "10"; --16bit
|
||||
else
|
||||
SIZE_DMA <= "01"; --8 bit
|
||||
end if;
|
||||
|
||||
--now calculate the offset:
|
||||
--if uds is set low, a0 is so too.
|
||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
||||
|
||||
--A1 is set by the amiga side
|
||||
--here we determine the upper or lower half of the databus
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= A1;
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= not A1;
|
||||
else
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "00";
|
||||
A0_DMA <= '0';
|
||||
RW_000_DMA <= '1';
|
||||
CLK_030_H <= '0';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- bus drivers
|
||||
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
|
||||
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE
|
||||
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
|
||||
'1';
|
||||
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
|
||||
'1';
|
||||
|
||||
|
||||
AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
|
||||
'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
|
||||
'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
|
||||
'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
|
||||
'0'; --Point towarts TK
|
||||
|
||||
|
||||
--dma stuff
|
||||
DTACK <= 'Z';
|
||||
--DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
-- '0' when DSACK1 ='0' else
|
||||
-- '1';
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
'0' when AS_000_DMA ='0' else
|
||||
'1';
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
'0' when DS_000_DMA ='0' else
|
||||
'1';
|
||||
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
'0' when A0_DMA ='0' else
|
||||
'1';
|
||||
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
"10" when SIZE_DMA ="10" else
|
||||
"01" when SIZE_DMA ="01" else
|
||||
"00";
|
||||
|
||||
--fpu
|
||||
FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
|
||||
else '1';
|
||||
|
||||
--if no copro is installed:
|
||||
BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
|
||||
else 'Z';
|
||||
--BERR <= 'Z';
|
||||
|
||||
|
||||
|
||||
--cache inhibit: Tristate for expansion (it decides) and off for the Amiga
|
||||
CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
|
||||
'Z' WHEN (not(A(31 downto 24) = x"00") and AS_030 ='0') OR nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
|
||||
'0'; --off for the Amiga
|
||||
|
||||
|
||||
--e and VMA
|
||||
E <= cpu_est(3);
|
||||
VMA <= VMA_INT;
|
||||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
'0' when AS_000_INT ='0' and AS_030 ='0' else
|
||||
'1';
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
'0' when RW_000_INT ='0' else
|
||||
'1';
|
||||
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
'0' when UDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
|
||||
'1';
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
'0' when LDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
|
||||
'1';
|
||||
|
||||
--dsack
|
||||
DSACK1 <= 'Z' when nEXP_SPACE_D0 = '0' else -- output on amiga cycle
|
||||
'0' when DSACK1_INT ='0' else
|
||||
'1';
|
||||
|
||||
--rw
|
||||
RW <= 'Z' when BGACK_030_INT ='1' else
|
||||
'0' when RW_000_DMA ='0' else
|
||||
'1';
|
||||
|
||||
BGACK_030 <= BGACK_030_INT;
|
||||
end Behavioral;
|
||||
|
|
@ -102,7 +102,7 @@ signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1';
|
|||
signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1';
|
||||
signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1';
|
||||
signal AS_030_D0:STD_LOGIC := '1';
|
||||
signal nEXP_SPACE_D0:STD_LOGIC := '1';
|
||||
signal nEXP_SPACE_D0:STD_LOGIC := '0';
|
||||
signal DS_030_D0:STD_LOGIC := '1';
|
||||
signal AS_030_000_SYNC:STD_LOGIC := '1';
|
||||
signal BGACK_030_INT:STD_LOGIC := '1';
|
||||
|
|
@ -119,16 +119,10 @@ signal UDS_000_INT: STD_LOGIC := '1';
|
|||
signal LDS_000_INT: STD_LOGIC := '1';
|
||||
signal DS_000_ENABLE: STD_LOGIC := '0';
|
||||
signal DSACK1_INT: STD_LOGIC := '1';
|
||||
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
|
||||
signal CLK_OUT_PRE_50: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_50_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_25: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_33_D: STD_LOGIC := '1';
|
||||
signal CLK_PRE_66:STD_LOGIC := '0';
|
||||
signal CLK_OUT_PRE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_PRE_D: STD_LOGIC := '1';
|
||||
signal CLK_OUT_NE: STD_LOGIC := '1';
|
||||
signal CLK_OUT_INT: STD_LOGIC := '1';
|
||||
signal CLK_030_H: STD_LOGIC := '1';
|
||||
signal CLK_000_D0: STD_LOGIC := '1';
|
||||
|
|
@ -142,56 +136,31 @@ signal CLK_000_PE: STD_LOGIC := '0';
|
|||
signal CLK_000_NE: STD_LOGIC := '0';
|
||||
signal CLK_000_NE_D0: STD_LOGIC := '0';
|
||||
signal DTACK_D0: STD_LOGIC := '1';
|
||||
signal RESET_DLY: STD_LOGIC_VECTOR ( 5 downto 0 ) := "000000";
|
||||
signal RESET_OUT: STD_LOGIC := '0';
|
||||
signal CLK_030_D0: STD_LOGIC := '0';
|
||||
--signal NO_RESET: STD_LOGIC := '0';
|
||||
|
||||
begin
|
||||
|
||||
--pos edge clock
|
||||
--pos edge clock process
|
||||
--no ansynchronious reset! the reset is sampled synchroniously
|
||||
--this mut be because of the e-clock: The E-Clock has to run CONSTANTLY
|
||||
--or the Amiga will fail to boot from a reset.
|
||||
--However a compilation with no resets on thEe-Clock and resets on other signals does not work, either!
|
||||
pos_clk: process(CLK_OSZI)
|
||||
begin
|
||||
if(false ) then
|
||||
CLK_OUT_PRE_50 <= '0';
|
||||
CLK_OUT_PRE_50_D<= '0';
|
||||
--CLK_OUT_PRE_25 <= '0';
|
||||
--CLK_OUT_PRE <= '0';
|
||||
CLK_OUT_PRE_D <= '0';
|
||||
--CLK_OUT_NE <= '0';
|
||||
--CLK_OUT_INT <= '0';
|
||||
CLK_000_D0 <= '0';
|
||||
CLK_000_D1 <= '0';
|
||||
CLK_000_D2 <= '0';
|
||||
CLK_000_D3 <= '0';
|
||||
CLK_000_D4 <= '0';
|
||||
CLK_000_P_SYNC <= "0000000000000";
|
||||
CLK_000_N_SYNC <= "0000000000000";
|
||||
CLK_000_NE_D0 <= '0';
|
||||
cpu_est <= E20;
|
||||
CLK_030_D0 <='0';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
if(rising_edge(CLK_OSZI)) then
|
||||
--clk generation :
|
||||
CLK_030_D0 <=CLK_030;
|
||||
CLK_OUT_PRE_50 <= not CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_50_D<= CLK_OUT_PRE_50;
|
||||
|
||||
--if(CLK_OUT_PRE_50='1' and CLK_OUT_PRE_50_D='0')then
|
||||
-- CLK_OUT_PRE_25 <= not CLK_OUT_PRE_25;
|
||||
--end if;
|
||||
|
||||
--here the clock is selected
|
||||
--CLK_OUT_PRE <= CLK_OUT_PRE_50;
|
||||
CLK_OUT_PRE_D <= CLK_OUT_PRE_50;
|
||||
|
||||
--a negative edge is comming next cycle
|
||||
--if(CLK_OUT_PRE_D='1' and CLK_OUT_PRE='0' )then
|
||||
-- CLK_OUT_NE <= '1';
|
||||
--else
|
||||
-- CLK_OUT_NE <= '0';
|
||||
--end if;
|
||||
-- the external clock to the processor is generated here
|
||||
--CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
|
||||
--delayed Clocks and signals for edge detection
|
||||
CLK_000_D0 <= CLK_000;
|
||||
CLK_000_D1 <= CLK_000_D0;
|
||||
|
|
@ -237,300 +206,279 @@ begin
|
|||
null;
|
||||
end case;
|
||||
end if;
|
||||
|
||||
--the statemachine
|
||||
if(RST = '0' ) then
|
||||
VPA_D <= '1';
|
||||
DTACK_D0 <= '1';
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
RW_000_DMA <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
VMA_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
BGACK_030_INT_D <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
IPL_030 <= "111";
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
AS_030_D0 <= '1';
|
||||
nEXP_SPACE_D0 <= '1';
|
||||
DS_030_D0 <= '1';
|
||||
CLK_030_H <= '0';
|
||||
CYCLE_DMA <= "00";
|
||||
RESET_OUT <= '0';
|
||||
else
|
||||
|
||||
RESET_OUT <= '1';
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
--buffering signals
|
||||
AS_030_D0 <= AS_030;
|
||||
nEXP_SPACE_D0 <= nEXP_SPACE;
|
||||
DS_030_D0 <= DS_030;
|
||||
DTACK_D0 <= DTACK;
|
||||
VPA_D <= VPA;
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif ( BGACK_000='1'
|
||||
AND CLK_000_PE='1'
|
||||
--AND CLK_000_D0='1' and CLK_000_D1='0'
|
||||
) then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
BGACK_030_INT_D <= BGACK_030_INT;
|
||||
|
||||
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
|
||||
and CLK_000_D0='1'
|
||||
--and CLK_000_D0='1' AND CLK_000_D1='0'
|
||||
) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
if(CLK_000_NE='1')then
|
||||
--if(CLK_000_D0='0' and CLK_000_D1='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
|
||||
if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
AS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
--RW_000_INT <= '1';
|
||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030_D0 = '0' AND --as set
|
||||
BGACK_030_INT='1' AND
|
||||
BGACK_030_INT_D='1' AND --no dma -cycle
|
||||
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
||||
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
|
||||
SM_AMIGA = IDLE_P --last amiga cycle terminated
|
||||
) then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
-- VMA generation
|
||||
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
--if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
--uds/lds precalculation
|
||||
if (DS_030_D0 = '0' AND SM_AMIGA = IDLE_N) then --DS: set udl/lds
|
||||
if(A0='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
--Amiga statemachine
|
||||
|
||||
if(BERR='0')then --"async" reset on errors
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
RW_000_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= CLK_000_D1;
|
||||
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
||||
SM_AMIGA<=IDLE_N; --go to s1
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||
if(CLK_000_PE='1')then --go to s2
|
||||
--if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
RW_000_INT <= RW;
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
if(CLK_000_NE='1')then --go to s3
|
||||
--if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||
|
||||
if(CLK_000_PE='1')then --go to s4
|
||||
--if(CLK_000_D0='1')then --go to s4
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
if( CLK_000_NE='1' and --falling edge
|
||||
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
|
||||
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
|
||||
(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
|
||||
)then --go to s5
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000_PE = '1')then --go to s6
|
||||
--if(CLK_000_D0='1')then --go to s6
|
||||
SM_AMIGA<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( (CLK_000_N_SYNC( 9)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
|
||||
(CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
|
||||
DSACK1_INT <='0';
|
||||
end if;
|
||||
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
-- DSACK1_INT <='0';
|
||||
--end if;
|
||||
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--DSACK1_INT <='0';
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
|
||||
if(CLK_000_PE='1')then --go to s0
|
||||
--if(CLK_000_D0='1')then --go to s0
|
||||
SM_AMIGA<=IDLE_P;
|
||||
RW_000_INT <= '1';
|
||||
--AMIGA_BUS_ENABLE_INT <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
--dma stuff
|
||||
if(BGACK_030_INT='0')then
|
||||
--switch amiga bus on for DMA-Cycles
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;
|
||||
--set some signals NOT linked to AS_000='0'
|
||||
RW_000_DMA <= RW_000;
|
||||
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
|
||||
if(UDS_000='0' and LDS_000='0') then
|
||||
SIZE_DMA <= "10"; --16bit
|
||||
else
|
||||
SIZE_DMA <= "01"; --8 bit
|
||||
end if;
|
||||
--now calculate the offset:
|
||||
--if uds is set low, a0 is so too.
|
||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
||||
--A1 is set by the amiga side
|
||||
--here we determine the upper or lower half of the databus
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= A1;
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= not A1;
|
||||
|
||||
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
AMIGA_BUS_ENABLE_INT <= '1' ;
|
||||
RW_000_DMA <= '1';
|
||||
SIZE_DMA <= "00";
|
||||
A0_DMA <= '0';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
end if;
|
||||
|
||||
if(BGACK_030_INT='0' and AS_000='0')then
|
||||
-- an 68000-memory cycle is three positive edges long!
|
||||
if(CLK_000_P_SYNC(10)='1')then
|
||||
CYCLE_DMA <= CYCLE_DMA+1;
|
||||
end if;
|
||||
else
|
||||
CYCLE_DMA <= "00";
|
||||
end if;
|
||||
|
||||
--as can only be done if we know the uds/lds!
|
||||
if( BGACK_030_INT='0'
|
||||
and AS_000='0'
|
||||
and(UDS_000='0' or LDS_000='0')
|
||||
and (
|
||||
--CYCLE_DMA ="00" or
|
||||
CYCLE_DMA ="01"
|
||||
or CYCLE_DMA ="10"
|
||||
--or CYCLE_DMA ="11"
|
||||
)
|
||||
)then
|
||||
--set AS_000
|
||||
if( CLK_030='1') then
|
||||
AS_000_DMA <= '0'; --sampled on rising edges!
|
||||
end if;
|
||||
|
||||
--delayed clock for write cycle
|
||||
if(AS_000_DMA = '0' and CLK_030='0')then
|
||||
CLK_030_H <= '1';
|
||||
end if;
|
||||
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <='0';
|
||||
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
|
||||
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
|
||||
end if;
|
||||
else
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
CLK_030_H <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process pos_clk;
|
||||
|
||||
--output clock assignment
|
||||
CLK_DIV_OUT <= CLK_OUT_PRE_D;
|
||||
CLK_EXP <= CLK_OUT_PRE_D;
|
||||
--NO_RESET <= '1';
|
||||
|
||||
-- i need to delay the board reset by some eclocks, so everything is synced fine afeter a soft reset!
|
||||
reset_delay_machine: process(RST, CLK_OSZI)
|
||||
begin
|
||||
if(RST = '0' ) then
|
||||
RESET_DLY <= "000000";
|
||||
RESET_OUT <= '0';
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
--reset delay: wait 128 E-Clocks!
|
||||
if(CLK_000_NE = '1' and cpu_est = E1) then
|
||||
RESET_DLY <= RESET_DLY +1;
|
||||
end if;
|
||||
end if;
|
||||
--reset buffer
|
||||
if(RESET_DLY="111111")then
|
||||
RESET_OUT <= '1';
|
||||
end if;
|
||||
end process reset_delay_machine;
|
||||
|
||||
--the state machine
|
||||
state_machine: process(RESET_OUT, CLK_OSZI)
|
||||
begin
|
||||
if(RESET_OUT = '0' ) then
|
||||
VPA_D <= '1';
|
||||
DTACK_D0 <= '1';
|
||||
SM_AMIGA <= IDLE_P;
|
||||
AS_000_INT <= '1';
|
||||
RW_000_INT <= '1';
|
||||
RW_000_DMA <= '1';
|
||||
AS_030_000_SYNC <= '1';
|
||||
UDS_000_INT <= '1';
|
||||
LDS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
CLK_REF <= "00";
|
||||
VMA_INT <= '1';
|
||||
BG_000 <= '1';
|
||||
BGACK_030_INT <= '1';
|
||||
BGACK_030_INT_D <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
IPL_030 <= "111";
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
SIZE_DMA <= "11";
|
||||
A0_DMA <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
AS_030_D0 <= '1';
|
||||
nEXP_SPACE_D0 <= '1';
|
||||
DS_030_D0 <= '1';
|
||||
CLK_030_H <= '0';
|
||||
CYCLE_DMA <= "00";
|
||||
elsif(rising_edge(CLK_OSZI)) then
|
||||
|
||||
|
||||
--now: 68000 state machine and signals
|
||||
|
||||
--buffering signals
|
||||
AS_030_D0 <= AS_030;
|
||||
nEXP_SPACE_D0 <= nEXP_SPACE;
|
||||
DS_030_D0 <= DS_030;
|
||||
DTACK_D0 <= DTACK;
|
||||
VPA_D <= VPA;
|
||||
|
||||
|
||||
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
|
||||
if(BGACK_000='0') then
|
||||
BGACK_030_INT <= '0';
|
||||
elsif ( BGACK_000='1'
|
||||
AND CLK_000_PE='1'
|
||||
--AND CLK_000_D0='1' and CLK_000_D1='0'
|
||||
) then -- BGACK_000 is high here!
|
||||
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
|
||||
end if;
|
||||
BGACK_030_INT_D <= BGACK_030_INT;
|
||||
|
||||
|
||||
|
||||
--bus grant only in idle state
|
||||
if(BG_030= '1')then
|
||||
BG_000 <= '1';
|
||||
elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P)
|
||||
and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
|
||||
and CLK_000_D0='1'
|
||||
--and CLK_000_D0='1' AND CLK_000_D1='0'
|
||||
) then --bus granted no local access and no AS_030 running!
|
||||
BG_000 <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
--interrupt buffering to avoid ghost interrupts
|
||||
if(CLK_000_NE='1')then
|
||||
--if(CLK_000_D0='0' and CLK_000_D1='1')then
|
||||
IPL_030<=IPL;
|
||||
end if;
|
||||
|
||||
-- as030-sampling and FPU-Select
|
||||
|
||||
|
||||
if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
|
||||
AS_030_000_SYNC <= '1';
|
||||
DSACK1_INT <= '1';
|
||||
AS_000_INT <= '1';
|
||||
DS_000_ENABLE <= '0';
|
||||
RW_000_INT <= '1';
|
||||
elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks
|
||||
AS_030_D0 = '0' AND --as set
|
||||
BGACK_030_INT='1' AND
|
||||
BGACK_030_INT_D='1' AND --no dma -cycle
|
||||
NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
|
||||
nEXP_SPACE_D0 ='1' and --not an expansion space cycle
|
||||
SM_AMIGA = IDLE_P --last amiga cycle terminated
|
||||
) then
|
||||
AS_030_000_SYNC <= '0';
|
||||
end if;
|
||||
|
||||
|
||||
-- VMA generation
|
||||
if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
--if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert
|
||||
VMA_INT <= '0';
|
||||
elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
|
||||
VMA_INT <= '1';
|
||||
end if;
|
||||
|
||||
--uds/lds precalculation
|
||||
if (DS_030_D0 = '0' AND SM_AMIGA = IDLE_N) then --DS: set udl/lds
|
||||
if(A0='0') then
|
||||
UDS_000_INT <= '0';
|
||||
else
|
||||
UDS_000_INT <= '1';
|
||||
end if;
|
||||
if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
|
||||
LDS_000_INT <= '0';
|
||||
else
|
||||
LDS_000_INT <= '1';
|
||||
end if;
|
||||
end if;
|
||||
|
||||
|
||||
--Amiga statemachine
|
||||
|
||||
if(BERR='0')then --"async" reset on errors
|
||||
SM_AMIGA<=IDLE_P;
|
||||
end if;
|
||||
|
||||
case (SM_AMIGA) is
|
||||
when IDLE_P => --68000:S0 wait for a falling edge
|
||||
RW_000_INT <= '1';
|
||||
AMIGA_BUS_ENABLE_INT <= CLK_000_D1;
|
||||
if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
|
||||
SM_AMIGA<=IDLE_N; --go to s1
|
||||
end if;
|
||||
when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
|
||||
if(CLK_000_PE='1')then --go to s2
|
||||
--if(CLK_000_D0='1')then --go to s2
|
||||
SM_AMIGA <= AS_SET_P; --as for amiga set!
|
||||
end if;
|
||||
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
|
||||
RW_000_INT <= RW;
|
||||
AS_000_INT <= '0';
|
||||
if (RW='1' ) then --read: set udl/lds
|
||||
DS_000_ENABLE <= '1';
|
||||
end if;
|
||||
if(CLK_000_NE='1')then --go to s3
|
||||
--if(CLK_000_D0='0')then --go to s3
|
||||
SM_AMIGA<=AS_SET_N;
|
||||
end if;
|
||||
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
|
||||
|
||||
if(CLK_000_PE='1')then --go to s4
|
||||
--if(CLK_000_D0='1')then --go to s4
|
||||
-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
|
||||
SM_AMIGA <= SAMPLE_DTACK_P;
|
||||
end if;
|
||||
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
|
||||
DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late
|
||||
if( CLK_000_NE='1' and --falling edge
|
||||
--if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
|
||||
((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
|
||||
(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
|
||||
)then --go to s5
|
||||
SM_AMIGA<=DATA_FETCH_N;
|
||||
end if;
|
||||
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
|
||||
if(CLK_000_PE = '1')then --go to s6
|
||||
--if(CLK_000_D0='1')then --go to s6
|
||||
SM_AMIGA<=DATA_FETCH_P;
|
||||
end if;
|
||||
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
|
||||
if( (CLK_000_N_SYNC( 9)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
|
||||
(CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
|
||||
DSACK1_INT <='0';
|
||||
end if;
|
||||
--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
-- DSACK1_INT <='0';
|
||||
--end if;
|
||||
if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
|
||||
--DSACK1_INT <='0';
|
||||
SM_AMIGA<=END_CYCLE_N;
|
||||
end if;
|
||||
when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
|
||||
if(CLK_000_PE='1')then --go to s0
|
||||
--if(CLK_000_D0='1')then --go to s0
|
||||
SM_AMIGA<=IDLE_P;
|
||||
RW_000_INT <= '1';
|
||||
--AMIGA_BUS_ENABLE_INT <= '1';
|
||||
end if;
|
||||
end case;
|
||||
|
||||
--dma stuff
|
||||
if(BGACK_030_INT='0')then
|
||||
--switch amiga bus on for DMA-Cycles
|
||||
AMIGA_BUS_ENABLE_INT <= '0' ;
|
||||
--set some signals NOT linked to AS_000='0'
|
||||
RW_000_DMA <= RW_000;
|
||||
-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
|
||||
if(UDS_000='0' and LDS_000='0') then
|
||||
SIZE_DMA <= "10"; --16bit
|
||||
else
|
||||
SIZE_DMA <= "01"; --8 bit
|
||||
end if;
|
||||
--now calculate the offset:
|
||||
--if uds is set low, a0 is so too.
|
||||
--if only lds is set a1 is high
|
||||
--therefore a1 = uds
|
||||
--great! life is simple here!
|
||||
A0_DMA <= UDS_000;
|
||||
--A1 is set by the amiga side
|
||||
--here we determine the upper or lower half of the databus
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= A1;
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= not A1;
|
||||
|
||||
elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then
|
||||
AMIGA_BUS_ENABLE_INT <= '1' ;
|
||||
RW_000_DMA <= '1';
|
||||
SIZE_DMA <= "00";
|
||||
A0_DMA <= '0';
|
||||
AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
|
||||
AMIGA_BUS_ENABLE_DMA_LOW <= '1';
|
||||
end if;
|
||||
|
||||
if(BGACK_030_INT='0' and AS_000='0')then
|
||||
-- an 68000-memory cycle is three positive edges long!
|
||||
if(CLK_000_P_SYNC(10)='1')then
|
||||
CYCLE_DMA <= CYCLE_DMA+1;
|
||||
end if;
|
||||
else
|
||||
CYCLE_DMA <= "00";
|
||||
end if;
|
||||
|
||||
--as can only be done if we know the uds/lds!
|
||||
if( BGACK_030_INT='0'
|
||||
and AS_000='0'
|
||||
and(UDS_000='0' or LDS_000='0')
|
||||
and (
|
||||
--CYCLE_DMA ="00" or
|
||||
CYCLE_DMA ="01"
|
||||
or CYCLE_DMA ="10"
|
||||
--or CYCLE_DMA ="11"
|
||||
)
|
||||
)then
|
||||
--set AS_000
|
||||
if( CLK_030='1') then
|
||||
AS_000_DMA <= '0'; --sampled on rising edges!
|
||||
end if;
|
||||
|
||||
--delayed clock for write cycle
|
||||
if(AS_000_DMA = '0' and CLK_030='0')then
|
||||
CLK_030_H <= '1';
|
||||
end if;
|
||||
|
||||
if(RW_000='1') then
|
||||
DS_000_DMA <='0';
|
||||
elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
|
||||
DS_000_DMA <=AS_000_DMA; -- write: one clock delayed!
|
||||
end if;
|
||||
else
|
||||
AS_000_DMA <= '1';
|
||||
DS_000_DMA <= '1';
|
||||
CLK_030_H <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process state_machine;
|
||||
|
||||
CLK_DIV_OUT <= CLK_OUT_INT;
|
||||
CLK_EXP <= CLK_OUT_INT;
|
||||
--CLK_DIV_OUT <= 'Z';
|
||||
--CLK_EXP <= CLK_030;
|
||||
|
||||
|
||||
|
||||
|
|
@ -559,13 +507,13 @@ begin
|
|||
--DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
-- '0' when DSACK1 ='0' else
|
||||
-- '1';
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
|
||||
'0' when AS_000_DMA ='0' and AS_000 ='0' else
|
||||
'1';
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
|
||||
'0' when DS_000_DMA ='0' and AS_000 ='0' else
|
||||
'1';
|
||||
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
|
||||
'0' when A0_DMA ='0' else
|
||||
'1';
|
||||
SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
|
||||
|
|
@ -573,7 +521,7 @@ begin
|
|||
"01" when SIZE_DMA ="01" else
|
||||
"00";
|
||||
--rw
|
||||
RW <= 'Z' when BGACK_030_INT ='1' else
|
||||
RW <= 'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' else
|
||||
'0' when RW_000_DMA ='0' else
|
||||
'1';
|
||||
|
||||
|
|
@ -602,21 +550,21 @@ begin
|
|||
|
||||
|
||||
--AVEC
|
||||
AVEC <= '1';
|
||||
AVEC <= '1';
|
||||
|
||||
--as and uds/lds
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
AS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else
|
||||
'0' when AS_000_INT ='0' and AS_030 ='0' else
|
||||
'1';
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' else
|
||||
RW_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else
|
||||
'0' when RW_000_INT ='0' else
|
||||
'1';
|
||||
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
UDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
'0' when UDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
|
||||
'1';
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle
|
||||
LDS_000 <= 'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
|
||||
--'1' when DS_000_ENABLE ='0' else
|
||||
'0' when LDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
|
||||
'1';
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
[synthesis-type]
|
||||
tool=Synplify
|
||||
[STRATEGY-LIST]
|
||||
Normal=True, 1412327082
|
||||
[TOUCHED-REPORT]
|
||||
Design.impFile=1422960966
|
||||
[synthesis-type]
|
||||
tool=Synplify
|
||||
Design.impFile=1426423374
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ Remember_Setting=1
|
|||
Open_PV_Opt=2
|
||||
Open_PV=0
|
||||
PV_IS_ACTIVE=0
|
||||
ACTIVE_SHEET=Global Constraints
|
||||
ACTIVE_SHEET=Pin Attributes
|
||||
Show_Def_Opt=2
|
||||
Show_Def_Val=1
|
||||
Expand_All_Column=0
|
||||
|
|
@ -40,9 +40,9 @@ State=43,no
|
|||
Constraint Name=162,no
|
||||
Constraint Value=115,no
|
||||
[OPT WINDOWS]
|
||||
MAIN_WINDOW_POSITION=0,0,1928,1168
|
||||
MAIN_WINDOW_POSITION=0,0,1920,1200
|
||||
CHILD_FRAME_STATE=Maximal
|
||||
CHILD_WINDOW_SIZE=1928,942
|
||||
CHILD_WINDOW_SIZE=1920,974
|
||||
CHILD_WINDOW_POS=-8,-30
|
||||
[OPT GUI SETTING]
|
||||
Remember_Setting=1
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
|
|||
|
||||
[Revision]
|
||||
Parent = m4a5.lci;
|
||||
DATE = 02/03/2015;
|
||||
TIME = 11:56:06;
|
||||
DATE = 03/15/2015;
|
||||
TIME = 13:42:54;
|
||||
Source_Format = Pure_VHDL;
|
||||
Synthesis = Synplify;
|
||||
|
||||
|
|
@ -28,9 +28,9 @@ Spread_placement = Yes;
|
|||
Zero_hold_time = Yes;
|
||||
Max_pterm_split = 16;
|
||||
Max_pterm_collapse = 16;
|
||||
Nodes_collapsing_mode = Area;
|
||||
Nodes_collapsing_mode = Speed;
|
||||
Max_fanin = 32;
|
||||
Set_reset_dont_care = Yes;
|
||||
Set_reset_dont_care = No;
|
||||
Balanced_partitioning = Yes;
|
||||
Max_macrocell_percent = 100;
|
||||
Dt_synthesis = Yes;
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ EN_PinMacrocell = Yes;
|
|||
|
||||
[Revision]
|
||||
Parent = m4a5.lci;
|
||||
DATE = 02/03/2015;
|
||||
TIME = 11:56:06;
|
||||
DATE = 03/15/2015;
|
||||
TIME = 13:42:54;
|
||||
Source_Format = Pure_VHDL;
|
||||
Synthesis = Synplify;
|
||||
|
||||
|
|
@ -28,9 +28,9 @@ Spread_placement = Yes;
|
|||
Zero_hold_time = Yes;
|
||||
Max_pterm_split = 16;
|
||||
Max_pterm_collapse = 16;
|
||||
Nodes_collapsing_mode = Area;
|
||||
Nodes_collapsing_mode = Speed;
|
||||
Max_fanin = 32;
|
||||
Set_reset_dont_care = Yes;
|
||||
Set_reset_dont_care = No;
|
||||
Balanced_partitioning = Yes;
|
||||
Max_macrocell_percent = 100;
|
||||
Dt_synthesis = Yes;
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
JDF B
|
||||
// Created by Version 1.7
|
||||
// Created by Version 1.8
|
||||
PROJECT 68030_TK
|
||||
DESIGN 68030_tk Normal
|
||||
DEVKIT M4A5-128/64-10VC
|
||||
|
|
|
|||
3495
Logic/68030_TK.tcl
3495
Logic/68030_TK.tcl
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
// Signal Name Cross Reference File
|
||||
// ispLEVER Classic 1.7.00.05.28.13
|
||||
// ispLEVER Classic 1.8.00.04.29.14
|
||||
|
||||
// Design '68030_tk' created Thu Feb 19 14:38:45 2015
|
||||
// Design '68030_tk' created Sun Mar 15 13:42:37 2015
|
||||
|
||||
|
||||
// LEGEND: '>' Functional Block Port Separator
|
||||
|
|
@ -10,4 +10,5 @@
|
|||
|
||||
|
||||
// Hierarchical Name Short Name
|
||||
state_machine_un22_bgack_030_int_i_0_i_n U0_achine_un22_bgack_030_int_i_0
|
||||
|
||||
// *** Shortened names not required for this design. ***
|
||||
|
|
|
|||
|
|
@ -1,2 +1 @@
|
|||
<LATTICE_ENCRYPTED_BLIF>6330162ñ
|
||||
a*hO:!
|
||||
<LATTICE_ENCRYPTED_BLIF>7410610toyi|\
|
||||
|
|
@ -1,20 +1,20 @@
|
|||
|
||||
fsm_encoding {7144321441} onehot
|
||||
fsm_encoding {7137371371} onehot
|
||||
|
||||
fsm_state_encoding {7144321441} idle_p {00000001}
|
||||
fsm_state_encoding {7137371371} idle_p {00000000}
|
||||
|
||||
fsm_state_encoding {7144321441} idle_n {00000010}
|
||||
fsm_state_encoding {7137371371} idle_n {00000011}
|
||||
|
||||
fsm_state_encoding {7144321441} as_set_p {00000100}
|
||||
fsm_state_encoding {7137371371} as_set_p {00000101}
|
||||
|
||||
fsm_state_encoding {7144321441} as_set_n {00001000}
|
||||
fsm_state_encoding {7137371371} as_set_n {00001001}
|
||||
|
||||
fsm_state_encoding {7144321441} sample_dtack_p {00010000}
|
||||
fsm_state_encoding {7137371371} sample_dtack_p {00010001}
|
||||
|
||||
fsm_state_encoding {7144321441} data_fetch_n {00100000}
|
||||
fsm_state_encoding {7137371371} data_fetch_n {00100001}
|
||||
|
||||
fsm_state_encoding {7144321441} data_fetch_p {01000000}
|
||||
fsm_state_encoding {7137371371} data_fetch_p {01000001}
|
||||
|
||||
fsm_state_encoding {7144321441} end_cycle_n {10000000}
|
||||
fsm_state_encoding {7137371371} end_cycle_n {10000001}
|
||||
|
||||
fsm_registers {7144321441} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]}
|
||||
fsm_registers {7137371371} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
<html>
|
||||
<head>
|
||||
<title>syntmp/BUS68030_srr.htm log file</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="syntmp/BUS68030_toc.htm" name="tocFrame" />
|
||||
<frame src="syntmp/BUS68030_srr.htm" name="srrFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
#-- Lattice Semiconductor Corporation Ltd.
|
||||
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
|
||||
#-- Written on Thu Feb 19 14:38:38 2015
|
||||
#-- Written on Sun Mar 15 13:42:23 2015
|
||||
|
||||
|
||||
#device options
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@
|
|||
<BScanVal>0</BScanVal>
|
||||
</Bypass>
|
||||
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
|
||||
<FileTime>02/01/15 21:36:01</FileTime>
|
||||
<JedecChecksum>0x7298</JedecChecksum>
|
||||
<FileTime>03/15/15 13:43:06</FileTime>
|
||||
<JedecChecksum>0x2570</JedecChecksum>
|
||||
<Operation>Erase,Program,Verify</Operation>
|
||||
<Option>
|
||||
<SVFVendor>JTAG STANDARD</SVFVendor>
|
||||
|
|
|
|||
|
|
@ -1,43 +1,32 @@
|
|||
#Build: Synplify Pro G-2012.09LC-SP1 , Build 035R, Mar 19 2013
|
||||
#install: C:\Program Files (x86)\ispLever\synpbase
|
||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: C:\ispLever\synpbase
|
||||
#OS: Windows 7 6.1
|
||||
#Hostname: DEEPTHOUGHT
|
||||
|
||||
#Implementation: logic
|
||||
|
||||
$ Start of Compile
|
||||
#Thu Feb 19 14:38:39 2015
|
||||
#Sun Mar 15 13:42:30 2015
|
||||
|
||||
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
VHDL syntax check successful!
|
||||
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_25 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:20|Signal clk_out_pre_33 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:22|Signal clk_out_pre_33_d is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:8:128:17|Signal clk_pre_66 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":261:2:261:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
|
|
@ -48,55 +37,21 @@ State machine has 8 reachable states with original encodings of:
|
|||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
||||
@END
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Feb 19 14:38:39 2015
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
|
||||
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||
Product Version G-2012.09LC-SP1
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000001
|
||||
001 -> 00000010
|
||||
010 -> 00000100
|
||||
011 -> 00001000
|
||||
100 -> 00010000
|
||||
101 -> 00100000
|
||||
110 -> 01000000
|
||||
111 -> 10000000
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":218:4:218:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFFSH 27 uses
|
||||
DFFRH 17 uses
|
||||
DFF 33 uses
|
||||
BI_DIR 11 uses
|
||||
IBUF 32 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 2 uses
|
||||
AND2 237 uses
|
||||
INV 187 uses
|
||||
DLATRH 1 use
|
||||
XOR2 10 uses
|
||||
OR2 28 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
G-2012.09LC-SP1
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Feb 19 14:38:41 2015
|
||||
# Sun Mar 15 13:42:30 2015
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Mar 15 13:42:32 2015
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
%%% protect protected_file
|
||||
@EG<?lPDRCHs#F"M=4"3jROCMFM8Hok="0UV-"
|
||||
?>
|
||||
-<!-7R]pHR]CssNORE$7HCVMHH0FwMRHRDCwlFsN-0R-<>
|
||||
]17p0Osk0CksRsPC#MHF=3"4j
|
||||
">
|
||||
!S<-1-RFOksCHRVDRC#O0FMskHL0oHMRR0F0REC8HC#o-MR-S>
|
||||
<k1Fs#OC>S
|
||||
S<k1FsROCbB=":#\HbPpCC#s\$LMbN\#CD\HLP\E8#308P"E8R"N=jD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8M\#bE#_N_b#b3 oP"E8R"N=4D"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P80\#8n44cE3P8N"R="".R"D=PDE8"DROH=#0""-4RHbD#"0=-/4">S
|
||||
S<k1FsROCbB=":#\HbPpCC#s\$LMbN\#CD\HLP\E8MCkls3HOP"E8R"N=dD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8l\ksN_Ob3HlP"E8R"N=cD"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8s\NH30EP"E8R"N=6D"R=E"P8RD"O#DH0-="4b"RD0H#=4"-"
|
||||
/>S1S<FOksC=Rb"\B:Hp#bCsPC\M#$b#LNCH\DLE\P8M\k#MHoCP83ER8"Nn=""=RD"8PEDO"RD0H#=4"-"DRbH=#0""-4/S>
|
||||
SF<1kCsOR"b=Bk:\##Cs\0lNx8C\FlOkC#M0\0oHE\kLndUjj\0 DHFoOU\nj-djnjUjjk-L#E3P8N"R=""(R"D=PDE8"DROH=#0""-4RHbD#"0=-/4"><
|
||||
S/k1Fs#OC>S
|
||||
|
||||
<-!-R8vFkRDCs0FFR>--
|
||||
)S<FRF0MI="F3s Anz1Ujjd3ELCNFPHs"ND/
|
||||
>
|
||||
|
||||
<
|
||||
S!R--vkF8D7CRCMVHHF0HM-R-><
|
||||
S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
|
||||
SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
|
||||
/>SqS<R"M=3ONsEDVHCP"R=""(/S>
|
||||
SR<qM3="lkF8DHCVDRC"P(=""
|
||||
/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.j"
|
||||
/>SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
|
||||
/>SqS<R"M=3l#00#DH0l0HCP"R=3"jjn46j/j">S
|
||||
S<MqR=s"FHHo_M_#0FRV"P&="J0kF;1AzndUjjk&JF"0;/S>
|
||||
SR<qM3="FosHhCNl"=RP"k&JFA0;zU1nj&djJ0kF;>"/
|
||||
/S<7>CV
|
||||
]</70p1s0kOk>sC
|
||||
|
||||
@
|
||||
|
|
@ -1,13 +1,14 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version G-2012.09LC-SP1
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
|
||||
#-- Written on Thu Feb 19 14:38:39 2015
|
||||
#-- Written on Sun Mar 15 13:42:30 2015
|
||||
|
||||
|
||||
#project files
|
||||
add_file -vhdl -lib work "./68030-68000-bus.vhd"
|
||||
|
||||
|
||||
|
||||
#implementation: "logic"
|
||||
impl -add logic -type fpga
|
||||
|
||||
|
|
@ -41,6 +42,9 @@ set_option -symbolic_fsm_compiler 1
|
|||
set_option -compiler_compatible 0
|
||||
set_option -resource_sharing 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -auto_infer_blackbox 0
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
|
|
|
|||
|
|
@ -1,11 +1,12 @@
|
|||
#-- Synopsys, Inc.
|
||||
#-- Version G-2012.09LC-SP1
|
||||
#-- Version I-2014.03LC
|
||||
#-- Project file C:\users\matze\documents\github\68030tk\logic\scratchproject.prs
|
||||
|
||||
#project files
|
||||
add_file -vhdl -lib work "C:/users/matze/documents/github/68030tk/logic/68030-68000-bus.vhd"
|
||||
|
||||
|
||||
|
||||
#implementation: "logic"
|
||||
impl -add C:\users\matze\documents\github\68030tk\logic -type fpga
|
||||
|
||||
|
|
@ -39,6 +40,9 @@ set_option -symbolic_fsm_compiler 1
|
|||
set_option -compiler_compatible 0
|
||||
set_option -resource_sharing 1
|
||||
|
||||
# Compiler Options
|
||||
set_option -auto_infer_blackbox 0
|
||||
|
||||
#automatic place and route (vendor) options
|
||||
set_option -write_apr_constraint 1
|
||||
|
||||
|
|
|
|||
|
|
@ -1,2 +1 @@
|
|||
source "C:/Users/Matze/AppData/Local/Synplicity/scm_perforce.tcl"
|
||||
history clear
|
||||
project -load c:/users/matze/documents/github/68030tk/logic/BUS68030.prj
|
||||
|
|
|
|||
|
|
@ -0,0 +1,9 @@
|
|||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N|Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Mar 15 13:42:32 2015
|
||||
|
||||
###########################################################]
|
||||
|
|
@ -1,45 +1,41 @@
|
|||
Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
|
||||
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
|
||||
Product Version G-2012.09LC-SP1
|
||||
Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N: MF248 |Running in 64-bit mode.
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000001
|
||||
001 -> 00000010
|
||||
010 -> 00000100
|
||||
011 -> 00001000
|
||||
100 -> 00010000
|
||||
101 -> 00100000
|
||||
110 -> 01000000
|
||||
111 -> 10000000
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":218:4:218:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
|
||||
000 -> 00000000
|
||||
001 -> 00000011
|
||||
010 -> 00000101
|
||||
011 -> 00001001
|
||||
100 -> 00010001
|
||||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:4:183:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
---------------------------------------
|
||||
Resource Usage Report
|
||||
|
||||
Simple gate primitives:
|
||||
DFFSH 27 uses
|
||||
DFFRH 17 uses
|
||||
DFF 33 uses
|
||||
DFF 73 uses
|
||||
BI_DIR 11 uses
|
||||
IBUF 32 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 2 uses
|
||||
AND2 237 uses
|
||||
INV 187 uses
|
||||
DLATRH 1 use
|
||||
XOR2 10 uses
|
||||
AND2 269 uses
|
||||
INV 240 uses
|
||||
OR2 28 uses
|
||||
XOR2 5 uses
|
||||
|
||||
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
G-2012.09LC-SP1
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Thu Feb 19 14:38:41 2015
|
||||
# Sun Mar 15 13:42:32 2015
|
||||
|
||||
###########################################################]
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
@N|Running in 64-bit mode
|
||||
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
||||
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
|
||||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
||||
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<job_run_status name="compiler">
|
||||
<report_link name="Detailed report">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\BUS68030.srr</data>
|
||||
<title>$ Start of Compile</title>
|
||||
<title>Start of Compile</title>
|
||||
</report_link>
|
||||
<job_status>
|
||||
<data>Completed </data>
|
||||
|
|
@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>17</data>
|
||||
<data>9</data>
|
||||
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
|
||||
</info>
|
||||
<info name="Errors">
|
||||
|
|
@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
|
|||
<data>-</data>
|
||||
</info>
|
||||
<info name="Real Time">
|
||||
<data>0h:00m:00s</data>
|
||||
<data>0h:00m:01s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>-</data>
|
||||
</info>
|
||||
<info name="Date &Time">
|
||||
<data type="timestamp">1424353119</data>
|
||||
<data type="timestamp">1426423350</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
@ -1,18 +1,10 @@
|
|||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_25 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:20|Signal clk_out_pre_33 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:7:127:22|Signal clk_out_pre_33_d is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":128:8:128:17|Signal clk_pre_66 is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:7:131:16|Signal clk_out_ne is undriven
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:7:132:17|Signal clk_out_int is undriven
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:36:109:38|Pruning register AMIGA_BUS_ENABLE_INT
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Pruning register CLK_REF(1 downto 0)
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:34:137:36|Pruning register CLK_000_D4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:34:136:36|Pruning register CLK_000_D3
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:34:135:36|Pruning register CLK_000_D2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":123:36:123:38|Pruning register CLK_OUT_PRE_50_D
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":261:2:261:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,3 @@
|
|||
@N: MF248 |Running in 64-bit mode.
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":218:4:218:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:4:183:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<job_run_status name="Mapper">
|
||||
<report_link name="Detailed report">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\BUS68030_fpga_mapper.srr</data>
|
||||
<title>Synopsys CPLD Technology Mapper</title>
|
||||
</report_link>
|
||||
<job_status>
|
||||
<data>Completed</data>
|
||||
|
|
@ -18,7 +19,7 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
</report_link>
|
||||
</info>
|
||||
<info name="Warnings">
|
||||
<data>2</data>
|
||||
<data>1</data>
|
||||
<report_link name="more">
|
||||
<data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
|
||||
</report_link>
|
||||
|
|
@ -36,10 +37,10 @@ The file contains the job information from mapper to be displayed as part of the
|
|||
<data>0h:00m:00s</data>
|
||||
</info>
|
||||
<info name="Peak Memory">
|
||||
<data>96MB</data>
|
||||
<data>105MB</data>
|
||||
</info>
|
||||
<info name="Date & Time">
|
||||
<data type="timestamp">1424353121</data>
|
||||
<data type="timestamp">1426423352</data>
|
||||
</info>
|
||||
</job_info>
|
||||
</job_run_status>
|
||||
|
|
|
|||
|
|
@ -1,2 +1 @@
|
|||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
@W: MT462 :|Net RST_c appears to be an unidentified clock source. Assuming default frequency.
|
||||
@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE
|
||||
|
|
|
|||
|
|
@ -0,0 +1,104 @@
|
|||
<html><body><samp><pre>
|
||||
<!@TC:1426423350>
|
||||
#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
|
||||
#install: C:\ispLever\synpbase
|
||||
#OS: Windows 7 6.1
|
||||
#Hostname: DEEPTHOUGHT
|
||||
|
||||
#Implementation: logic
|
||||
|
||||
<a name=compilerReport1>$ Start of Compile</a>
|
||||
#Sun Mar 15 13:42:30 2015
|
||||
|
||||
Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1426423350> | Running in 64-bit mode
|
||||
Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited.
|
||||
|
||||
@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1426423350> | Setting time resolution to ns
|
||||
@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1426423350> | Top entity is set to BUS68030.
|
||||
VHDL syntax check successful!
|
||||
@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1426423350> | Synthesizing work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1426423350> | Signal clk_out_pre is undriven </font>
|
||||
Post processing for work.bus68030.behavioral
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1426423350> | Pruning register AMIGA_BUS_ENABLE_INT_4 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1426423350> | Pruning register CLK_000_D4_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1426423350> | Pruning register CLK_000_D3_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:129:34:129:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(129)</a><!@TM:1426423350> | Pruning register CLK_000_D2_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:122:36:122:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(122)</a><!@TM:1426423350> | Pruning register CLK_OUT_PRE_50_D_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:148:2:148:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(148)</a><!@TM:1426423350> | Pruning register CLK_030_D0_2 </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:61:133:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1426423350> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1426423350> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1426423350> | Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
001
|
||||
010
|
||||
011
|
||||
100
|
||||
101
|
||||
110
|
||||
111
|
||||
@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:137:37:137:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(137)</a><!@TM:1426423350> | Trying to extract state machine for register cpu_est
|
||||
@END
|
||||
|
||||
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Mar 15 13:42:30 2015
|
||||
|
||||
###########################################################]
|
||||
Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
|
||||
@N: : <!@TM:1426423352> | Running in 64-bit mode
|
||||
|
||||
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Mar 15 13:42:32 2015
|
||||
|
||||
###########################################################]
|
||||
Map & Optimize Report
|
||||
|
||||
<a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014</a>
|
||||
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
||||
Product Version I-2014.03LC
|
||||
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1426423352> | Running in 64-bit mode.
|
||||
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
|
||||
original code -> new code
|
||||
000 -> 00000000
|
||||
001 -> 00000011
|
||||
010 -> 00000101
|
||||
011 -> 00001001
|
||||
100 -> 00010001
|
||||
101 -> 00100001
|
||||
110 -> 01000001
|
||||
111 -> 10000001
|
||||
@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:183:4:183:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(183)</a><!@TM:1426423352> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits
|
||||
<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1426423352> | Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE</font>
|
||||
---------------------------------------
|
||||
<a name=resourceUsage3>Resource Usage Report</a>
|
||||
|
||||
Simple gate primitives:
|
||||
DFF 73 uses
|
||||
BI_DIR 11 uses
|
||||
IBUF 32 uses
|
||||
OBUF 16 uses
|
||||
BUFTH 2 uses
|
||||
AND2 269 uses
|
||||
INV 240 uses
|
||||
OR2 28 uses
|
||||
XOR2 5 uses
|
||||
|
||||
|
||||
@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1426423352> | Timing Report not generated for this device, please use place and route tools for timing analysis.
|
||||
I-2014.03LC
|
||||
Mapper successful!
|
||||
|
||||
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
|
||||
|
||||
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
||||
# Sun Mar 15 13:42:32 2015
|
||||
|
||||
###########################################################]
|
||||
|
||||
</pre></samp></body></html>
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
<html>
|
||||
<head>
|
||||
<script type="text/javascript" src="file:///C:\ispLever\synpbase\lib\report\reportlog_tree.js"></script>
|
||||
<link rel="stylesheet" type="text/css" href="file:///C:\ispLever\synpbase\lib\report\reportlog_tree.css" />
|
||||
</head>
|
||||
|
||||
<body style="background-color:#e0e0ff;">
|
||||
<script type="text/javascript"> reportLogObj.loadImage("closed.png", "open.png")</script>
|
||||
<ul id="logic-menu" class="treeview" style="padding-left:12;">
|
||||
<li style="font-size:12; font-style:normal"> <b style="background-color:#a2bff0; font-weight:bold">BUS68030 (logic)</b>
|
||||
<ul rel="open" style="font-size:small;">
|
||||
|
||||
<li style="font-size:12; font-style:normal"><b style="background-color:#a2bff0; font-weight:bold">Synthesis - </b>
|
||||
<ul rel="open">
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#compilerReport1" target="srrFrame" title="">Compiler Report</a> </li>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>
|
||||
<ul rel="open" >
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a> </li></ul></li></ul></li>
|
||||
<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (13:42 15-Mar)</a>
|
||||
<ul ></ul></li> </ul>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
<script type="text/javascript"> reportLogObj.generateLog("logic-menu")</script>
|
||||
|
||||
</body>
|
||||
</html>
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 3.6 KiB |
Binary file not shown.
|
After Width: | Height: | Size: 452 B |
|
|
@ -1,9 +1,9 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!--
|
||||
Synopsys, Inc.
|
||||
Version G-2012.09LC-SP1
|
||||
Version I-2014.03LC
|
||||
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
|
||||
Written on Thu Feb 19 14:38:39 2015
|
||||
Written on Sun Mar 15 13:42:30 2015
|
||||
|
||||
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -0,0 +1,60 @@
|
|||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html xmlns="http://www.w3.org/1999/xhtml">
|
||||
<head> <meta http-equiv="Content-Type" content="text/html; charset=iso-8859-1" />
|
||||
<title>Project Status Summary Page</title>
|
||||
<script type="text/javascript" src="projectstatuspage.js"></script>
|
||||
<link rel="stylesheet" type="text/css" href="projectstatuspage.css" />
|
||||
</head>
|
||||
|
||||
<body style="background-color:#f0f0ff;">
|
||||
|
||||
<table style="border:none;" width="100%" ><tr> <td class="outline">
|
||||
<table width="100%" border="0" cellspacing="0" cellpadding="0"> <thead><tr><th colspan="4">Project Settings</th><tr>
|
||||
<tr> <td class="optionTitle" align="left"> Project Name</td> <td> BUS68030</td> <td class="optionTitle" align="left"> Implementation Name</td> <td> logic</td> </tr>
|
||||
</thead>
|
||||
<tbody> <tr> <td class="optionTitle" align="left"> Top Module</td> <td> BUS68030</td> <td class="optionTitle" align="left"> Resource Sharing</td> <td> 1</td> </tr>
|
||||
<tr> <td class="optionTitle" align="left"> Disable I/O Insertion</td> <td> 0</td> <td class="optionTitle" align="left"> FSM Compiler</td> <td> 1</td> </tr>
|
||||
|
||||
</tbody>
|
||||
</table><br> <table width="100%" border="0" cellspacing= "0" cellpadding= "0">
|
||||
<thead><tr><th colspan="9">Run Status</th></tr></thead>
|
||||
<tbody>
|
||||
<tr>
|
||||
<th align="left" width="17%">Job Name</th>
|
||||
<th align="left">Status</th>
|
||||
<td class="lnote" align="center" title="Notes"></td>
|
||||
<td class="lwarn" align="center" title="Warnings"></td>
|
||||
<td class="lerror" align="center" title="Errors"></td>
|
||||
<th align="left">CPU Time</th>
|
||||
<th align="left">Real Time</th>
|
||||
<th align="left">Memory</th>
|
||||
<th align="left">Date/Time</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="optionTitle">Compile Input</td><td>Complete</td>
|
||||
<td>6</td>
|
||||
<td>9</td>
|
||||
<td>0</td>
|
||||
<td>-</td>
|
||||
<td>0m:01s</td>
|
||||
<td>-</td>
|
||||
<td><font size="-1">15.03.2015</font><br/><font size="-2">13:42:30</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Map & Optimize</td><td>Complete</td>
|
||||
<td>3</td>
|
||||
<td>1</td>
|
||||
<td>0</td>
|
||||
<td>0m:00s</td>
|
||||
<td>0m:00s</td>
|
||||
<td>105MB</td>
|
||||
<td><font size="-1">15.03.2015</font><br/><font size="-2">13:42:32</font></td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td class="optionTitle">Multi-srs Generator</td>
|
||||
<td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">15.03.2015</font><br/><font size="-2">13:42:32</font></td> </tbody>
|
||||
</table>
|
||||
</td></tr></table></body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
#defaultlanguage:vhdl
|
||||
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
|
||||
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1426423340
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
0 -1
|
||||
|
||||
# Dependency Lists (Users Of)
|
||||
0 -1
|
||||
|
||||
# Design Unit to File Association
|
||||
arch work bus68030 behavioral 0
|
||||
module work bus68030 0
|
||||
|
||||
|
||||
# Configuration files used
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#defaultlanguage:vhdl
|
||||
#OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
|
||||
#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
|
||||
#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1426423340
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
0 -1
|
||||
|
||||
# Dependency Lists (Users Of)
|
||||
0 -1
|
||||
|
||||
# Design Unit to File Association
|
||||
arch work bus68030 behavioral 0
|
||||
module work bus68030 0
|
||||
Binary file not shown.
|
|
@ -0,0 +1,23 @@
|
|||
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
|
||||
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven
|
||||
Post processing for work.bus68030.behavioral
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Pruning register AMIGA_BUS_ENABLE_INT_4
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D4_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D3_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:34:129:36|Pruning register CLK_000_D2_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_50_D_2
|
||||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":148:2:148:3|Pruning register CLK_030_D0_2
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:61:133:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ...
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
State machine has 8 reachable states with original encodings of:
|
||||
000
|
||||
001
|
||||
010
|
||||
011
|
||||
100
|
||||
101
|
||||
110
|
||||
111
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:37:137:39|Trying to extract state machine for register cpu_est
|
||||
|
|
@ -10,7 +10,7 @@
|
|||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1424353112
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1425240376
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@
|
|||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363690728
|
||||
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363690728
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1424353112
|
||||
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1425240376
|
||||
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
|
||||
|
||||
# Dependency Lists (Uses list)
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -16,7 +16,7 @@ Post processing for work.bus68030.behavioral
|
|||
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0
|
||||
@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:61:139:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:34:138:36|Pruning bits 12 to 11 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
|
||||
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":261:2:261:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
|
||||
@W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":263:2:263:3|Latch generated from process for signal RESET_OUT; possible missing assignment in an if or case statement.
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":143:37:143:39|Trying to extract state machine for register cpu_est
|
||||
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":144:32:144:34|Trying to extract state machine for register SM_AMIGA
|
||||
Extracted state machine for register SM_AMIGA
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Loading…
Reference in New Issue