mirror of https://github.com/kr239/68030tk.git
25 lines
1.2 KiB
Plaintext
25 lines
1.2 KiB
Plaintext
ispLEVER Classic 2.0.00.17.20.15 SDFGEN
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Copyright(C),1992-2015, Lattice Semiconductor Corporation. All Rights Reserved.
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Output Files:
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Netlist File: 68030_tk.vho
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Delay File: 68030_tk.sdf
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Parsing E:/ispLEVER_Classic2_0/ispcpld/dat/sdf.mdl
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Input file: c:/users/matze/documents/github/68030tk/logic\68030_tk.tte
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Reading library information ...
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Mapping to combinational gates
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Mapping to netlist view.
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Note 18862: NODE name cpu_est_2_bus.D.X1 being renamed to GATE_cpu_est_2_bus_D_X1.
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Note 18862: NODE name RST_DLY_1_bus.D.X1 being renamed to GATE_RST_DLY_1_bus_D_X1.
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Note 18862: NODE name RST_DLY_1_bus.D.X2 being renamed to GATE_RST_DLY_1_bus_D_X2.
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Note 18862: NODE name SM_AMIGA_3_bus.D.X1 being renamed to GATE_SM_AMIGA_3_bus_D_X1.
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Note 18862: NODE name SM_AMIGA_3_bus.D.X2 being renamed to GATE_SM_AMIGA_3_bus_D_X2.
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Note 18862: NODE name SM_AMIGA_i_7_bus.D.X1 being renamed to GATE_SM_AMIGA_i_7_bus_D_X1.
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Note 18862: NODE name SM_AMIGA_i_7_bus.D.X2 being renamed to GATE_SM_AMIGA_i_7_bus_D_X2.
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Note 18862: NODE name CIIN_0 being renamed to GATE_CIIN_OE.
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Utilization Estimate
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Combinational Macros: 524
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Flip-Flop and Latch Macros: 61
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I/O Pads: 61
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Elapsed time: 1 seconds
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