mirror of https://github.com/kr239/68030tk.git
583 lines
21 KiB
Plaintext
583 lines
21 KiB
Plaintext
ispLEVER Classic 2.0.00.17.20.15 Linked Equations File
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Copyright(C), 1992-2015, Lattice Semiconductor Corp.
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All Rights Reserved.
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Design bus68030 created Sat Dec 30 00:43:37 2017
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P-Terms Fan-in Fan-out Type Name (attributes)
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--------- ------ ------- ---- -----------------
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0 0 1 Pin AHIGH_27_
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1 1 1 Pin AHIGH_27_.OE
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0 0 1 Pin AHIGH_26_
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1 1 1 Pin AHIGH_26_.OE
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0 0 1 Pin AHIGH_25_
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1 1 1 Pin AHIGH_25_.OE
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0 0 1 Pin AHIGH_24_
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1 1 1 Pin AHIGH_24_.OE
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0 0 1 Pin AHIGH_31_
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1 1 1 Pin AHIGH_31_.OE
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1 2 1 Pin AS_030-
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1 1 1 Pin AS_030.OE
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1 2 1 Pin AS_000-
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1 2 1 Pin AS_000.OE
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1 2 1 Pin DS_030-
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1 1 1 Pin DS_030.OE
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1 2 1 Pin UDS_000-
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1 2 1 Pin UDS_000.OE
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1 2 1 Pin LDS_000-
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1 2 1 Pin LDS_000.OE
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0 0 1 Pin BERR
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1 9 1 Pin BERR.OE
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1 1 1 Pin CLK_DIV_OUT
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1 1 1 Pin CLK_EXP
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1 9 1 Pin FPU_CS-
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1 2 1 Pin DSACK1-
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1 2 1 Pin DSACK1.OE
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1 0 1 Pin AVEC
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2 3 1 Pin E
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0 0 1 Pin AMIGA_ADDR_ENABLE
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2 4 1 Pin AMIGA_BUS_DATA_DIR
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1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
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2 4 1 Pin AMIGA_BUS_ENABLE_HIGH-
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1 13 1 Pin CIIN
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1 1 1 Pin CIIN.OE
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0 0 1 Pin AHIGH_30_
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1 1 1 Pin AHIGH_30_.OE
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0 0 1 Pin AHIGH_29_
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1 1 1 Pin AHIGH_29_.OE
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0 0 1 Pin AHIGH_28_
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1 1 1 Pin AHIGH_28_.OE
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1 1 1 Pin SIZE_1_.OE
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2 4 1 Pin SIZE_1_.D
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1 1 1 Pin SIZE_1_.C
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10 8 1 Pin IPL_030_2_.D-
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1 1 1 Pin IPL_030_2_.C
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1 2 1 Pin RW_000.OE
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4 8 1 Pin RW_000.D-
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1 1 1 Pin RW_000.C
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2 6 1 Pin BG_000.D-
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1 1 1 Pin BG_000.C
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3 6 1 Pin BGACK_030.D
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1 1 1 Pin BGACK_030.C
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1 1 1 Pin A_0_.OE
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2 3 1 Pin A_0_.D
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1 1 1 Pin A_0_.C
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10 8 1 Pin IPL_030_1_.D-
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1 1 1 Pin IPL_030_1_.C
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10 8 1 Pin IPL_030_0_.D-
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1 1 1 Pin IPL_030_0_.C
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1 1 1 Pin VMA.OE
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3 9 1 Pin VMA.T
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1 1 1 Pin VMA.C
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1 1 1 Pin RW.OE
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1 3 1 Pin RW.D-
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1 1 1 Pin RW.C
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1 1 1 Pin SIZE_0_.OE
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2 4 1 Pin SIZE_0_.D-
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1 1 1 Pin SIZE_0_.C
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3 3 1 Node cpu_est_0_.D
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1 1 1 Node cpu_est_0_.C
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4 5 1 Node cpu_est_1_.D
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1 1 1 Node cpu_est_1_.C
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1 4 1 NodeX1 cpu_est_2_.D.X1
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1 1 1 NodeX2 cpu_est_2_.D.X2
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1 1 1 Node cpu_est_2_.C
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4 6 1 Node cpu_est_3_.D
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1 1 1 Node cpu_est_3_.C
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1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
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1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
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1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
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1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
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1 2 1 Node inst_AS_030_D0.D-
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1 1 1 Node inst_AS_030_D0.C
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2 3 1 Node inst_AS_030_D1.D
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1 1 1 Node inst_AS_030_D1.C
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7 14 1 Node inst_AS_030_000_SYNC.D-
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1 1 1 Node inst_AS_030_000_SYNC.C
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6 9 1 Node inst_AS_000_DMA.D
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1 1 1 Node inst_AS_000_DMA.C
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6 9 1 Node inst_DS_000_DMA.D
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1 1 1 Node inst_DS_000_DMA.C
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1 2 1 Node inst_VPA_D.D-
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1 1 1 Node inst_VPA_D.C
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1 1 1 Node CLK_000_D_3_.D
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1 1 1 Node CLK_000_D_3_.C
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1 2 1 Node inst_DTACK_D0.D-
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1 1 1 Node inst_DTACK_D0.C
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2 3 1 Node inst_AMIGA_DS.D
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1 1 1 Node inst_AMIGA_DS.C
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1 1 1 Node CLK_000_D_1_.D
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1 1 1 Node CLK_000_D_1_.C
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1 1 1 Node CLK_000_D_0_.D
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1 1 1 Node CLK_000_D_0_.C
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1 1 1 Node inst_CLK_OUT_PRE_50.D
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1 1 1 Node inst_CLK_OUT_PRE_50.C
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1 1 1 Node inst_CLK_OUT_PRE_D.D
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1 1 1 Node inst_CLK_OUT_PRE_D.C
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1 2 1 Node IPL_D0_0_.D-
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1 1 1 Node IPL_D0_0_.C
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1 2 1 Node IPL_D0_1_.D-
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1 1 1 Node IPL_D0_1_.C
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1 2 1 Node IPL_D0_2_.D-
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1 1 1 Node IPL_D0_2_.C
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1 1 1 Node CLK_000_D_2_.D
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1 1 1 Node CLK_000_D_2_.C
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1 1 1 Node CLK_000_D_4_.D
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1 1 1 Node CLK_000_D_4_.C
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2 4 1 Node inst_UDS_000_INT.D-
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1 1 1 Node inst_UDS_000_INT.C
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3 8 1 Node inst_DS_000_ENABLE.D
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1 1 1 Node inst_DS_000_ENABLE.C
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3 6 1 Node inst_LDS_000_INT.D
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1 1 1 Node inst_LDS_000_INT.C
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1 2 1 Node inst_BGACK_030_INT_D.D-
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1 1 1 Node inst_BGACK_030_INT_D.C
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3 9 1 Node SM_AMIGA_6_.D
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1 1 1 Node SM_AMIGA_6_.C
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3 5 1 Node SM_AMIGA_4_.D
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1 1 1 Node SM_AMIGA_4_.C
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3 5 1 Node SM_AMIGA_1_.D
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1 1 1 Node SM_AMIGA_1_.C
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3 5 1 Node SM_AMIGA_0_.D
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1 1 1 Node SM_AMIGA_0_.C
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4 7 1 Node CYCLE_DMA_0_.D
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1 1 1 Node CYCLE_DMA_0_.C
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2 7 1 Node CYCLE_DMA_1_.D
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1 1 1 Node CYCLE_DMA_1_.C
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2 6 1 Node inst_DSACK1_INT.D-
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1 1 1 Node inst_DSACK1_INT.C
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2 6 1 Node inst_AS_000_INT.D-
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1 1 1 Node inst_AS_000_INT.C
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3 5 1 Node SM_AMIGA_5_.D
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1 1 1 Node SM_AMIGA_5_.C
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5 13 1 Node SM_AMIGA_3_.T
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1 1 1 Node SM_AMIGA_3_.C
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5 13 1 Node SM_AMIGA_2_.D
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1 1 1 Node SM_AMIGA_2_.C
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1 1 1 Node CLK_OUT_INTreg.D
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1 1 1 Node CLK_OUT_INTreg.C
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3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1
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1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2
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1 1 1 Node SM_AMIGA_i_7_.C
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2 14 1 Node N_60
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=========
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243 P-Term Total: 243
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Total Pins: 59
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Total Nodes: 42
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Average P-Term/Output: 2
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Equations:
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AHIGH_27_ = (0);
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AHIGH_27_.OE = (!BGACK_030.Q);
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AHIGH_26_ = (0);
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AHIGH_26_.OE = (!BGACK_030.Q);
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AHIGH_25_ = (0);
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AHIGH_25_.OE = (!BGACK_030.Q);
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AHIGH_24_ = (0);
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AHIGH_24_.OE = (!BGACK_030.Q);
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AHIGH_31_ = (0);
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AHIGH_31_.OE = (!BGACK_030.Q);
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!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
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AS_030.OE = (!BGACK_030.Q);
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!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
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AS_000.OE = (RST & BGACK_030.Q);
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!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
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DS_030.OE = (!BGACK_030.Q);
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!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
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UDS_000.OE = (RST & BGACK_030.Q);
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!LDS_000 = (inst_DS_000_ENABLE.Q & !inst_LDS_000_INT.Q);
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LDS_000.OE = (RST & BGACK_030.Q);
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BERR = (0);
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BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
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CLK_DIV_OUT = (CLK_OUT_INTreg.Q);
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CLK_EXP = (CLK_OUT_INTreg.Q);
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!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN);
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!DSACK1 = (!inst_DSACK1_INT.Q & !AS_030.PIN);
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DSACK1.OE = (nEXP_SPACE & BGACK_030.Q);
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AVEC = (1);
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E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q
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# cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q);
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AMIGA_ADDR_ENABLE = (0);
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AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
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# !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN);
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!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
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!AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
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# BGACK_030.Q & !inst_AS_030_000_SYNC.Q & !AS_030.PIN);
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CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
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CIIN.OE = (N_60);
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AHIGH_30_ = (0);
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AHIGH_30_.OE = (!BGACK_030.Q);
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AHIGH_29_ = (0);
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AHIGH_29_.OE = (!BGACK_030.Q);
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AHIGH_28_ = (0);
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AHIGH_28_.OE = (!BGACK_030.Q);
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SIZE_1_.OE = (!BGACK_030.Q);
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SIZE_1_.D = (!RST
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# !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
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SIZE_1_.C = (CLK_OSZI);
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!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
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# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
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# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
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# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
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# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
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# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
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# !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
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IPL_030_2_.C = (CLK_OSZI);
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RW_000.OE = (RST & BGACK_030.Q);
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!RW_000.D = (RST & CLK_000_D_1_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
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# RST & !CLK_000_D_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
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# RST & !SM_AMIGA_6_.Q & !RW_000.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q
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# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q & !RW.PIN);
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RW_000.C = (CLK_OSZI);
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!BG_000.D = (!BG_030 & RST & !BG_000.Q
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# nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q);
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BG_000.C = (CLK_OSZI);
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BGACK_030.D = (!RST
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# BGACK_000 & BGACK_030.Q
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# BGACK_000 & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & AS_000.PIN);
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BGACK_030.C = (CLK_OSZI);
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A_0_.OE = (!BGACK_030.Q);
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A_0_.D = (!RST
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# !BGACK_030.Q & UDS_000.PIN);
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A_0_.C = (CLK_OSZI);
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!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
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# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
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# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
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# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
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# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
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# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
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# IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
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# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
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IPL_030_1_.C = (CLK_OSZI);
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!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
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# RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
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# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
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# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
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# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
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# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
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# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
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# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
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# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
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IPL_030_0_.C = (CLK_OSZI);
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VMA.OE = (BGACK_030.Q);
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VMA.T = (!RST & !VMA.Q
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# !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !VMA.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q
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# RST & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
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VMA.C = (CLK_OSZI);
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RW.OE = (!BGACK_030.Q);
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!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN);
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RW.C = (CLK_OSZI);
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SIZE_0_.OE = (!BGACK_030.Q);
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!SIZE_0_.D = (RST & BGACK_030.Q
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# RST & !UDS_000.PIN & !LDS_000.PIN);
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SIZE_0_.C = (CLK_OSZI);
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cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q
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# cpu_est_0_.Q & CLK_000_D_0_.Q
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# !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
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cpu_est_0_.C = (CLK_OSZI);
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cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
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# cpu_est_1_.Q & !CLK_000_D_1_.Q
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# cpu_est_1_.Q & CLK_000_D_0_.Q
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# cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
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cpu_est_1_.C = (CLK_OSZI);
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cpu_est_2_.D.X1 = (cpu_est_0_.Q & cpu_est_1_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
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cpu_est_2_.D.X2 = (cpu_est_2_.Q);
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cpu_est_2_.C = (CLK_OSZI);
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cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q
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# cpu_est_3_.Q & !CLK_000_D_1_.Q
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# cpu_est_3_.Q & CLK_000_D_0_.Q
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# cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q);
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cpu_est_3_.C = (CLK_OSZI);
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!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q);
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inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
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!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q);
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inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
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!inst_AS_030_D0.D = (RST & !AS_030.PIN);
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inst_AS_030_D0.C = (CLK_OSZI);
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inst_AS_030_D1.D = (RST & inst_AS_030_D0.Q
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# !RST & inst_AS_030_D1.Q);
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inst_AS_030_D1.C = (CLK_OSZI);
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!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_000_SYNC.Q & !AS_030.PIN
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# !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN
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# nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN
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# nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN
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# nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN
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# nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN
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# nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D1.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & !AS_030.PIN);
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inst_AS_030_000_SYNC.C = (CLK_OSZI);
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inst_AS_000_DMA.D = (!RST
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# inst_AMIGA_DS.Q
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# AS_000.PIN
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# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
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# inst_AS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q
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# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN);
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inst_AS_000_DMA.C = (CLK_OSZI);
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inst_DS_000_DMA.D = (!RST
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# inst_AMIGA_DS.Q
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# AS_000.PIN
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# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
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# inst_DS_000_DMA.Q & inst_CLK_OUT_PRE_D.Q & !CLK_OUT_INTreg.Q
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# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !RW_000.PIN);
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inst_DS_000_DMA.C = (CLK_OSZI);
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!inst_VPA_D.D = (!VPA & RST);
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inst_VPA_D.C = (CLK_OSZI);
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CLK_000_D_3_.D = (CLK_000_D_2_.Q);
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CLK_000_D_3_.C = (CLK_OSZI);
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!inst_DTACK_D0.D = (!DTACK & RST);
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inst_DTACK_D0.C = (CLK_OSZI);
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inst_AMIGA_DS.D = (!RST
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# UDS_000.PIN & LDS_000.PIN);
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inst_AMIGA_DS.C = (CLK_OSZI);
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CLK_000_D_1_.D = (CLK_000_D_0_.Q);
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CLK_000_D_1_.C = (CLK_OSZI);
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CLK_000_D_0_.D = (CLK_000);
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CLK_000_D_0_.C = (CLK_OSZI);
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inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
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inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
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inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
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inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
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!IPL_D0_0_.D = (RST & !IPL_0_);
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IPL_D0_0_.C = (CLK_OSZI);
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!IPL_D0_1_.D = (RST & !IPL_1_);
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IPL_D0_1_.C = (CLK_OSZI);
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!IPL_D0_2_.D = (!IPL_2_ & RST);
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IPL_D0_2_.C = (CLK_OSZI);
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CLK_000_D_2_.D = (CLK_000_D_1_.Q);
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CLK_000_D_2_.C = (CLK_OSZI);
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CLK_000_D_4_.D = (CLK_000_D_3_.Q);
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CLK_000_D_4_.C = (CLK_OSZI);
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!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
|
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# RST & SM_AMIGA_6_.Q & !A_0_.PIN);
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inst_UDS_000_INT.C = (CLK_OSZI);
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inst_DS_000_ENABLE.D = (RST & inst_DS_000_ENABLE.Q & !AS_030.PIN
|
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# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q
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# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q & RW.PIN);
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inst_DS_000_ENABLE.C = (CLK_OSZI);
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inst_LDS_000_INT.D = (!RST
|
|
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
|
|
# SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN);
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inst_LDS_000_INT.C = (CLK_OSZI);
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!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
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inst_BGACK_030_INT_D.C = (CLK_OSZI);
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SM_AMIGA_6_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_6_.Q
|
|
# RST & !CLK_000_D_0_.Q & SM_AMIGA_6_.Q
|
|
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q);
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SM_AMIGA_6_.C = (CLK_OSZI);
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SM_AMIGA_4_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_4_.Q
|
|
# RST & !CLK_000_D_0_.Q & SM_AMIGA_4_.Q
|
|
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_5_.Q);
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SM_AMIGA_4_.C = (CLK_OSZI);
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|
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SM_AMIGA_1_.D = (RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_2_.Q
|
|
# RST & !CLK_000_D_1_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
|
|
# RST & CLK_000_D_0_.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
|
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SM_AMIGA_1_.C = (CLK_OSZI);
|
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|
|
SM_AMIGA_0_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_0_.Q
|
|
# RST & !CLK_000_D_0_.Q & SM_AMIGA_0_.Q
|
|
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q);
|
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|
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SM_AMIGA_0_.C = (CLK_OSZI);
|
|
|
|
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CLK_000_D_1_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN
|
|
# RST & !BGACK_030.Q & CLK_000_D_0_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN
|
|
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
|
|
# RST & !BGACK_030.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !CYCLE_DMA_0_.Q & !AS_000.PIN);
|
|
|
|
CYCLE_DMA_0_.C = (CLK_OSZI);
|
|
|
|
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
|
|
# RST & !BGACK_030.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & CYCLE_DMA_0_.Q & !AS_000.PIN);
|
|
|
|
CYCLE_DMA_1_.C = (CLK_OSZI);
|
|
|
|
!inst_DSACK1_INT.D = (RST & !inst_DSACK1_INT.Q & !AS_030.PIN
|
|
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_1_.Q);
|
|
|
|
inst_DSACK1_INT.C = (CLK_OSZI);
|
|
|
|
!inst_AS_000_INT.D = (RST & !inst_AS_000_INT.Q & !AS_030.PIN
|
|
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q);
|
|
|
|
inst_AS_000_INT.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_5_.D = (RST & !CLK_000_D_1_.Q & SM_AMIGA_5_.Q
|
|
# RST & CLK_000_D_0_.Q & SM_AMIGA_5_.Q
|
|
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_6_.Q);
|
|
|
|
SM_AMIGA_5_.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
|
|
# CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
|
# inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
|
|
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
|
|
# !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
|
|
|
|
SM_AMIGA_3_.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_2_.D = (RST & CLK_000_D_1_.Q & SM_AMIGA_2_.Q
|
|
# RST & !CLK_000_D_0_.Q & SM_AMIGA_2_.Q
|
|
# RST & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q & !BERR.PIN
|
|
# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q
|
|
# RST & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !VMA.Q & !inst_VPA_D.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & SM_AMIGA_3_.Q);
|
|
|
|
SM_AMIGA_2_.C = (CLK_OSZI);
|
|
|
|
CLK_OUT_INTreg.D = (inst_CLK_OUT_PRE_D.Q);
|
|
|
|
CLK_OUT_INTreg.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_i_7_.T.X1 = (!RST & SM_AMIGA_i_7_.Q
|
|
# RST & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & SM_AMIGA_0_.Q & SM_AMIGA_i_7_.Q
|
|
# nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & CLK_000_D_4_.Q & !SM_AMIGA_i_7_.Q);
|
|
|
|
SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_.Q & !CLK_000_D_1_.Q & CLK_000_D_0_.Q & CLK_000_D_4_.Q & SM_AMIGA_0_.Q & !SM_AMIGA_i_7_.Q);
|
|
|
|
SM_AMIGA_i_7_.C = (CLK_OSZI);
|
|
|
|
N_60 = (nEXP_SPACE
|
|
# A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN);
|
|
|
|
|
|
Reverse-Polarity Equations:
|
|
|