mirror of https://github.com/kr239/68030tk.git
774 lines
31 KiB
Plaintext
774 lines
31 KiB
Plaintext
ispLEVER Classic 1.8.00.04.29.14 Linked Equations File
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Copyright(C), 1992-2014, Lattice Semiconductor Corp.
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All Rights Reserved.
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Design bus68030 created Wed May 13 22:59:21 2015
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P-Terms Fan-in Fan-out Type Name (attributes)
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--------- ------ ------- ---- -----------------
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1 2 1 Pin SIZE_1_
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1 2 1 Pin SIZE_1_.OE
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1 2 1 Pin AS_030-
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1 3 1 Pin AS_030.OE
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1 2 1 Pin AS_000-
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1 2 1 Pin AS_000.OE
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1 2 1 Pin DS_030-
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1 3 1 Pin DS_030.OE
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1 3 1 Pin UDS_000-
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1 2 1 Pin UDS_000.OE
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1 3 1 Pin LDS_000-
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1 2 1 Pin LDS_000.OE
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0 0 1 Pin BERR
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1 9 1 Pin BERR.OE
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0 0 1 Pin CLK_DIV_OUT
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0 0 1 Pin CLK_DIV_OUT.OE
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1 1 1 Pin CLK_EXP
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1 9 1 Pin FPU_CS-
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1 0 1 Pin AVEC
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0 0 1 Pin AMIGA_ADDR_ENABLE
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2 4 1 Pin AMIGA_BUS_DATA_DIR
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1 2 1 Pin AMIGA_BUS_ENABLE_LOW-
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2 3 1 Pin AMIGA_BUS_ENABLE_HIGH
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1 13 1 Pin CIIN
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1 1 1 Pin CIIN.OE
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1 2 1 Pin SIZE_0_
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1 2 1 Pin SIZE_0_.OE
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10 8 1 Pin IPL_030_2_.D-
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1 1 1 Pin IPL_030_2_.C
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1 2 1 Pin RW_000.OE
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3 7 1 Pin RW_000.D-
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1 1 1 Pin RW_000.C
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1 3 1 Pin A0.OE
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3 5 1 Pin A0.D
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1 1 1 Pin A0.C
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2 6 1 Pin BG_000.D-
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1 1 1 Pin BG_000.C
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2 4 1 Pin BGACK_030.D-
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1 1 1 Pin BGACK_030.C
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10 8 1 Pin IPL_030_1_.D-
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1 1 1 Pin IPL_030_1_.C
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10 8 1 Pin IPL_030_0_.D-
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1 1 1 Pin IPL_030_0_.C
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1 1 1 Pin DSACK1.OE
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4 9 1 Pin DSACK1.D-
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1 1 1 Pin DSACK1.C
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5 5 1 Pin E.D
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1 1 1 Pin E.C
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3 9 1 Pin VMA.T
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1 1 1 Pin VMA.C
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2 11 1 Pin RESET.D
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1 1 1 Pin RESET.C
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1 2 1 Pin RW.OE
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2 5 1 Pin RW.D-
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1 1 1 Pin RW.C
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2 2 1 Node cpu_est_0_.D
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1 1 1 Node cpu_est_0_.C
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5 5 1 Node cpu_est_1_.D-
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1 1 1 Node cpu_est_1_.C
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2 5 1 Node inst_AS_000_INT.D-
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1 1 1 Node inst_AS_000_INT.C
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3 6 1 Node SM_AMIGA_5_.D
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1 1 1 Node SM_AMIGA_5_.C
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2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
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1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C
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1 2 1 Node inst_AS_030_D0.D-
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1 1 1 Node inst_AS_030_D0.C
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1 2 1 Node inst_nEXP_SPACE_D0reg.D-
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1 1 1 Node inst_nEXP_SPACE_D0reg.C
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1 2 1 Node inst_DS_030_D0.D-
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1 1 1 Node inst_DS_030_D0.C
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7 14 1 Node inst_AS_030_000_SYNC.D-
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1 1 1 Node inst_AS_030_000_SYNC.C
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1 2 1 Node inst_BGACK_030_INT_D.D-
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1 1 1 Node inst_BGACK_030_INT_D.C
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7 9 1 Node inst_AS_000_DMA.D
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1 1 1 Node inst_AS_000_DMA.C
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9 12 1 Node inst_DS_000_DMA.D
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1 1 1 Node inst_DS_000_DMA.C
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2 5 1 Node CYCLE_DMA_0_.D
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1 1 1 Node CYCLE_DMA_0_.C
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3 6 1 Node CYCLE_DMA_1_.D
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1 1 1 Node CYCLE_DMA_1_.C
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3 6 1 Node SIZE_DMA_0_.D-
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1 1 1 Node SIZE_DMA_0_.C
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3 6 1 Node SIZE_DMA_1_.D
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1 1 1 Node SIZE_DMA_1_.C
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1 2 1 Node inst_VPA_D.D-
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1 1 1 Node inst_VPA_D.C
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3 5 1 Node inst_UDS_000_INT.D-
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1 1 1 Node inst_UDS_000_INT.C
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4 7 1 Node inst_LDS_000_INT.D
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1 1 1 Node inst_LDS_000_INT.C
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1 1 1 Node inst_CLK_OUT_PRE_D.D
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1 1 1 Node inst_CLK_OUT_PRE_D.C
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1 2 1 Node inst_DTACK_D0.D-
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1 1 1 Node inst_DTACK_D0.C
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1 1 1 Node inst_CLK_OUT_PRE_50.D
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1 1 1 Node inst_CLK_OUT_PRE_50.C
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1 1 1 Node inst_CLK_000_D1.D
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1 1 1 Node inst_CLK_000_D1.C
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1 1 1 Node inst_CLK_000_D0.D
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1 1 1 Node inst_CLK_000_D0.C
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1 1 1 Node inst_CLK_000_PE.D
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1 1 1 Node inst_CLK_000_PE.C
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1 1 1 Node CLK_000_P_SYNC_9_.D
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1 1 1 Node CLK_000_P_SYNC_9_.C
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1 1 1 Node inst_CLK_000_NE.D
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1 1 1 Node inst_CLK_000_NE.C
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4 11 1 Node N_96_i-
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1 1 1 Node CLK_000_N_SYNC_11_.D
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1 1 1 Node CLK_000_N_SYNC_11_.C
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4 5 1 Node cpu_est_2_.D
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1 1 1 Node cpu_est_2_.C
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1 2 1 Node IPL_D0_0_.D-
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1 1 1 Node IPL_D0_0_.C
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1 2 1 Node IPL_D0_1_.D-
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1 1 1 Node IPL_D0_1_.C
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1 2 1 Node IPL_D0_2_.D-
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1 1 1 Node IPL_D0_2_.C
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5 13 1 Node SM_AMIGA_3_.T
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1 1 1 Node SM_AMIGA_3_.C
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1 1 1 Node inst_CLK_000_NE_D0.D
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1 1 1 Node inst_CLK_000_NE_D0.C
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2 6 1 Node SM_AMIGA_0_.D
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1 1 1 Node SM_AMIGA_0_.C
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2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
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1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
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3 9 1 Node SM_AMIGA_6_.D
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1 1 1 Node SM_AMIGA_6_.C
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3 10 1 Node RST_DLY_0_.D
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1 1 1 Node RST_DLY_0_.C
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4 10 1 Node RST_DLY_1_.D
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1 1 1 Node RST_DLY_1_.C
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5 10 1 Node RST_DLY_2_.D
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1 1 1 Node RST_DLY_2_.C
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6 10 1 Node RST_DLY_3_.D
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1 1 1 Node RST_DLY_3_.C
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2 7 1 NodeX1 RST_DLY_4_.T.X1
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1 10 1 NodeX2 RST_DLY_4_.T.X2
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1 1 1 Node RST_DLY_4_.C
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4 10 1 Node RST_DLY_5_.T
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1 1 1 Node RST_DLY_5_.C
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3 10 1 Node RST_DLY_6_.T
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1 1 1 Node RST_DLY_6_.C
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2 10 1 Node RST_DLY_7_.D
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1 1 1 Node RST_DLY_7_.C
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1 2 1 Node CLK_000_P_SYNC_0_.D
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1 1 1 Node CLK_000_P_SYNC_0_.C
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1 1 1 Node CLK_000_P_SYNC_1_.D
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1 1 1 Node CLK_000_P_SYNC_1_.C
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1 1 1 Node CLK_000_P_SYNC_2_.D
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1 1 1 Node CLK_000_P_SYNC_2_.C
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1 1 1 Node CLK_000_P_SYNC_3_.D
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1 1 1 Node CLK_000_P_SYNC_3_.C
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1 1 1 Node CLK_000_P_SYNC_4_.D
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1 1 1 Node CLK_000_P_SYNC_4_.C
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1 1 1 Node CLK_000_P_SYNC_5_.D
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1 1 1 Node CLK_000_P_SYNC_5_.C
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1 1 1 Node CLK_000_P_SYNC_6_.D
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1 1 1 Node CLK_000_P_SYNC_6_.C
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1 1 1 Node CLK_000_P_SYNC_7_.D
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1 1 1 Node CLK_000_P_SYNC_7_.C
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1 1 1 Node CLK_000_P_SYNC_8_.D
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1 1 1 Node CLK_000_P_SYNC_8_.C
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1 2 1 Node CLK_000_N_SYNC_0_.D
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1 1 1 Node CLK_000_N_SYNC_0_.C
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1 1 1 Node CLK_000_N_SYNC_1_.D
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1 1 1 Node CLK_000_N_SYNC_1_.C
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1 1 1 Node CLK_000_N_SYNC_2_.D
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1 1 1 Node CLK_000_N_SYNC_2_.C
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1 1 1 Node CLK_000_N_SYNC_3_.D
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1 1 1 Node CLK_000_N_SYNC_3_.C
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1 1 1 Node CLK_000_N_SYNC_4_.D
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1 1 1 Node CLK_000_N_SYNC_4_.C
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1 1 1 Node CLK_000_N_SYNC_5_.D
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1 1 1 Node CLK_000_N_SYNC_5_.C
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1 1 1 Node CLK_000_N_SYNC_6_.D
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1 1 1 Node CLK_000_N_SYNC_6_.C
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1 1 1 Node CLK_000_N_SYNC_7_.D
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1 1 1 Node CLK_000_N_SYNC_7_.C
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1 1 1 Node CLK_000_N_SYNC_8_.D
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1 1 1 Node CLK_000_N_SYNC_8_.C
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1 1 1 Node CLK_000_N_SYNC_9_.D
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1 1 1 Node CLK_000_N_SYNC_9_.C
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1 1 1 Node CLK_000_N_SYNC_10_.D
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1 1 1 Node CLK_000_N_SYNC_10_.C
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8 10 1 Node inst_CLK_030_H.D
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1 1 1 Node inst_CLK_030_H.C
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3 6 1 Node SM_AMIGA_1_.D
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1 1 1 Node SM_AMIGA_1_.C
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3 6 1 Node SM_AMIGA_4_.D
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1 1 1 Node SM_AMIGA_4_.C
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4 13 1 Node SM_AMIGA_2_.D
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1 1 1 Node SM_AMIGA_2_.C
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3 7 1 Node inst_DS_000_ENABLE.D
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1 1 1 Node inst_DS_000_ENABLE.C
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14 20 1 Node SM_AMIGA_i_7_.D
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1 1 1 Node SM_AMIGA_i_7_.C
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2 14 1 Node CIIN_0
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=========
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348 P-Term Total: 348
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Total Pins: 61
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Total Nodes: 73
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Average P-Term/Output: 2
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Equations:
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SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
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SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
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!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
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AS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);
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!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
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AS_000.OE = (BGACK_030.Q & RESET.Q);
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!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
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DS_030.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);
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!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);
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UDS_000.OE = (BGACK_030.Q & RESET.Q);
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!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN);
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LDS_000.OE = (BGACK_030.Q & RESET.Q);
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BERR = (0);
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BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
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CLK_DIV_OUT = (0);
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CLK_DIV_OUT.OE = (0);
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CLK_EXP = (CLK_030);
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!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
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AVEC = (1);
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AMIGA_ADDR_ENABLE = (0);
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AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
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# !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
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!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
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AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
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# BGACK_030.Q & !SM_AMIGA_i_7_.Q);
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CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
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CIIN.OE = (CIIN_0);
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SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
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SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
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!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
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# RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
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# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
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# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
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# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
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# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
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# !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
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IPL_030_2_.C = (CLK_OSZI);
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RW_000.OE = (BGACK_030.Q & RESET.Q);
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!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
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# RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
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# RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);
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RW_000.C = (CLK_OSZI);
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A0.OE = (!BGACK_030.Q & RESET.Q & !inst_nEXP_SPACE_D0reg.Q);
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A0.D = (!RST
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# !BGACK_030.Q & UDS_000.PIN
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# BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q);
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A0.C = (CLK_OSZI);
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!BG_000.D = (!BG_030 & RST & !BG_000.Q
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# !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);
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BG_000.C = (CLK_OSZI);
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!BGACK_030.D = (!BGACK_000 & RST
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# RST & !BGACK_030.Q & !inst_CLK_000_PE.Q);
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BGACK_030.C = (CLK_OSZI);
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!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
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# RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
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# RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
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# RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
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# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
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# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
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# IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
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# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
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IPL_030_1_.C = (CLK_OSZI);
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!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
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# RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
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# RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
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# RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
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# !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
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# IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
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# IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
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# IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
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# !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
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# !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
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IPL_030_0_.C = (CLK_OSZI);
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DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
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!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
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# !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
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# RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
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# RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
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DSACK1.C = (CLK_OSZI);
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E.D = (E.Q & !cpu_est_0_.Q
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# E.Q & !cpu_est_1_.Q
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# E.Q & !inst_CLK_000_NE_D0.Q
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# cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
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# !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
|
|
|
|
E.C = (CLK_OSZI);
|
|
|
|
VMA.T = (!RST & !VMA.Q
|
|
# !E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q
|
|
# RST & !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q);
|
|
|
|
VMA.C = (CLK_OSZI);
|
|
|
|
RESET.D = (RST & RESET.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
|
|
|
RESET.C = (CLK_OSZI);
|
|
|
|
RW.OE = (!BGACK_030.Q & RESET.Q);
|
|
|
|
!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
|
|
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
|
|
|
|
RW.C = (CLK_OSZI);
|
|
|
|
cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
|
|
# cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
|
|
|
|
cpu_est_0_.C = (CLK_OSZI);
|
|
|
|
!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
|
|
# E.Q & cpu_est_0_.Q & !cpu_est_1_.Q
|
|
# !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q
|
|
# E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q
|
|
# !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
|
|
|
|
cpu_est_1_.C = (CLK_OSZI);
|
|
|
|
!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q
|
|
# RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
|
|
|
|
inst_AS_000_INT.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
|
|
# RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN
|
|
# RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);
|
|
|
|
SM_AMIGA_5_.C = (CLK_OSZI);
|
|
|
|
!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q
|
|
# RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
|
|
|
|
inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
|
|
|
|
!inst_AS_030_D0.D = (RST & !AS_030.PIN);
|
|
|
|
inst_AS_030_D0.C = (CLK_OSZI);
|
|
|
|
!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST);
|
|
|
|
inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);
|
|
|
|
!inst_DS_030_D0.D = (RST & !DS_030.PIN);
|
|
|
|
inst_DS_030_D0.C = (CLK_OSZI);
|
|
|
|
!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
|
|
# !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
# RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
# RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
# RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
# RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
|
|
# RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
|
|
|
|
inst_AS_030_000_SYNC.C = (CLK_OSZI);
|
|
|
|
!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
|
|
|
|
inst_BGACK_030_INT_D.C = (CLK_OSZI);
|
|
|
|
inst_AS_000_DMA.D = (!RST
|
|
# BGACK_030.Q
|
|
# AS_000.PIN
|
|
# !CLK_030 & inst_AS_000_DMA.Q
|
|
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
|
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
|
# UDS_000.PIN & LDS_000.PIN);
|
|
|
|
inst_AS_000_DMA.C = (CLK_OSZI);
|
|
|
|
inst_DS_000_DMA.D = (!RST
|
|
# BGACK_030.Q
|
|
# AS_000.PIN
|
|
# CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
|
|
# !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
|
|
# UDS_000.PIN & LDS_000.PIN
|
|
# !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
|
|
# inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
|
|
# CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
|
|
|
|
inst_DS_000_DMA.C = (CLK_OSZI);
|
|
|
|
CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN
|
|
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN);
|
|
|
|
CYCLE_DMA_0_.C = (CLK_OSZI);
|
|
|
|
CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
|
|
# RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN
|
|
# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN);
|
|
|
|
CYCLE_DMA_1_.C = (CLK_OSZI);
|
|
|
|
!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
|
|
# RST & BGACK_030.Q & !SIZE_DMA_0_.Q
|
|
# RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
|
|
|
SIZE_DMA_0_.C = (CLK_OSZI);
|
|
|
|
SIZE_DMA_1_.D = (!RST
|
|
# BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
|
|
# !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
|
|
|
|
SIZE_DMA_1_.C = (CLK_OSZI);
|
|
|
|
!inst_VPA_D.D = (!VPA & RST);
|
|
|
|
inst_VPA_D.C = (CLK_OSZI);
|
|
|
|
!inst_UDS_000_INT.D = (RST & inst_DS_030_D0.Q & !inst_UDS_000_INT.Q
|
|
# RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
|
|
# RST & !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & !A0.PIN);
|
|
|
|
inst_UDS_000_INT.C = (CLK_OSZI);
|
|
|
|
inst_LDS_000_INT.D = (!RST
|
|
# inst_DS_030_D0.Q & inst_LDS_000_INT.Q
|
|
# inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
|
|
# !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
|
|
|
|
inst_LDS_000_INT.C = (CLK_OSZI);
|
|
|
|
inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q);
|
|
|
|
inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
|
|
|
|
!inst_DTACK_D0.D = (!DTACK & RST);
|
|
|
|
inst_DTACK_D0.C = (CLK_OSZI);
|
|
|
|
inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
|
|
|
|
inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
|
|
|
|
inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
|
|
|
|
inst_CLK_000_D1.C = (CLK_OSZI);
|
|
|
|
inst_CLK_000_D0.D = (CLK_000);
|
|
|
|
inst_CLK_000_D0.C = (CLK_OSZI);
|
|
|
|
inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
|
|
|
|
inst_CLK_000_PE.C = (CLK_OSZI);
|
|
|
|
CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
|
|
|
|
CLK_000_P_SYNC_9_.C = (CLK_OSZI);
|
|
|
|
inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
|
|
|
|
inst_CLK_000_NE.C = (CLK_OSZI);
|
|
|
|
!N_96_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
|
# !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
|
# !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
|
|
# !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);
|
|
|
|
CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
|
|
|
|
CLK_000_N_SYNC_11_.C = (CLK_OSZI);
|
|
|
|
cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q
|
|
# cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
|
|
# E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
|
|
# !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q);
|
|
|
|
cpu_est_2_.C = (CLK_OSZI);
|
|
|
|
!IPL_D0_0_.D = (RST & !IPL_0_);
|
|
|
|
IPL_D0_0_.C = (CLK_OSZI);
|
|
|
|
!IPL_D0_1_.D = (RST & !IPL_1_);
|
|
|
|
IPL_D0_1_.C = (CLK_OSZI);
|
|
|
|
!IPL_D0_2_.D = (!IPL_2_ & RST);
|
|
|
|
IPL_D0_2_.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
|
|
# SM_AMIGA_3_.Q & !BERR.PIN
|
|
# RST & inst_CLK_000_PE.Q & !SM_AMIGA_3_.Q & SM_AMIGA_4_.Q
|
|
# inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q
|
|
# E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q);
|
|
|
|
SM_AMIGA_3_.C = (CLK_OSZI);
|
|
|
|
inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);
|
|
|
|
inst_CLK_000_NE_D0.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
|
|
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);
|
|
|
|
SM_AMIGA_0_.C = (CLK_OSZI);
|
|
|
|
!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q
|
|
# RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
|
|
|
|
inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
|
|
|
|
SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
|
|
# RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
|
|
# RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);
|
|
|
|
SM_AMIGA_6_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q
|
|
# RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q
|
|
# RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
|
|
|
RST_DLY_0_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q
|
|
# RST & !RST_DLY_0_.Q & RST_DLY_1_.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q
|
|
# RST & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
|
|
|
RST_DLY_1_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_2_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_2_.Q
|
|
# RST & !RST_DLY_0_.Q & RST_DLY_2_.Q
|
|
# RST & !RST_DLY_1_.Q & RST_DLY_2_.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & !RST_DLY_2_.Q
|
|
# RST & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
|
|
|
RST_DLY_2_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_3_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_3_.Q
|
|
# RST & !RST_DLY_0_.Q & RST_DLY_3_.Q
|
|
# RST & !RST_DLY_1_.Q & RST_DLY_3_.Q
|
|
# RST & !RST_DLY_2_.Q & RST_DLY_3_.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & !RST_DLY_3_.Q
|
|
# RST & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
|
|
|
RST_DLY_3_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_4_.T.X1 = (!RST & RST_DLY_4_.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q);
|
|
|
|
RST_DLY_4_.T.X2 = (RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & RST_DLY_7_.Q);
|
|
|
|
RST_DLY_4_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_5_.T = (!RST & RST_DLY_5_.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & !RST_DLY_5_.Q
|
|
# inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q
|
|
# inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_7_.Q);
|
|
|
|
RST_DLY_5_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_6_.T = (!RST & RST_DLY_6_.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & !RST_DLY_6_.Q
|
|
# inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q & !RST_DLY_7_.Q);
|
|
|
|
RST_DLY_6_.C = (CLK_OSZI);
|
|
|
|
RST_DLY_7_.D = (RST & RST_DLY_7_.Q
|
|
# RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q & RST_DLY_3_.Q & RST_DLY_4_.Q & RST_DLY_5_.Q & RST_DLY_6_.Q);
|
|
|
|
RST_DLY_7_.C = (CLK_OSZI);
|
|
|
|
CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
|
|
|
|
CLK_000_P_SYNC_0_.C = (CLK_OSZI);
|
|
|
|
CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
|
|
|
|
CLK_000_P_SYNC_1_.C = (CLK_OSZI);
|
|
|
|
CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
|
|
|
|
CLK_000_P_SYNC_2_.C = (CLK_OSZI);
|
|
|
|
CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
|
|
|
|
CLK_000_P_SYNC_3_.C = (CLK_OSZI);
|
|
|
|
CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
|
|
|
|
CLK_000_P_SYNC_4_.C = (CLK_OSZI);
|
|
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CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
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CLK_000_P_SYNC_5_.C = (CLK_OSZI);
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CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
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CLK_000_P_SYNC_6_.C = (CLK_OSZI);
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CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
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CLK_000_P_SYNC_7_.C = (CLK_OSZI);
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CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
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CLK_000_P_SYNC_8_.C = (CLK_OSZI);
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CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
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CLK_000_N_SYNC_0_.C = (CLK_OSZI);
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CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
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CLK_000_N_SYNC_1_.C = (CLK_OSZI);
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CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
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CLK_000_N_SYNC_2_.C = (CLK_OSZI);
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CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
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CLK_000_N_SYNC_3_.C = (CLK_OSZI);
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CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
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CLK_000_N_SYNC_4_.C = (CLK_OSZI);
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CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
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CLK_000_N_SYNC_5_.C = (CLK_OSZI);
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CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
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CLK_000_N_SYNC_6_.C = (CLK_OSZI);
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CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
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CLK_000_N_SYNC_7_.C = (CLK_OSZI);
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CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
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CLK_000_N_SYNC_8_.C = (CLK_OSZI);
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CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
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CLK_000_N_SYNC_9_.C = (CLK_OSZI);
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CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
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CLK_000_N_SYNC_10_.C = (CLK_OSZI);
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inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
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# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
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# RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
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# RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
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# !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
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inst_CLK_030_H.C = (CLK_OSZI);
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SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
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# RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN
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# RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN);
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SM_AMIGA_1_.C = (CLK_OSZI);
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SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
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# RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
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# RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);
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SM_AMIGA_4_.C = (CLK_OSZI);
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SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
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# RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
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# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q
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# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & inst_CLK_000_NE_D0.Q);
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SM_AMIGA_2_.C = (CLK_OSZI);
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inst_DS_000_ENABLE.D = (RST & !SM_AMIGA_5_.Q & SM_AMIGA_3_.Q
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# RST & SM_AMIGA_5_.Q & RW.PIN
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# RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN);
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inst_DS_000_ENABLE.C = (CLK_OSZI);
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SM_AMIGA_i_7_.D = (RST & !inst_CLK_000_PE.Q & N_96_i & BERR.PIN
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# RST & N_96_i & !SM_AMIGA_0_.Q & BERR.PIN
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# RST & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q
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# RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
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# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
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# RST & inst_CLK_000_NE.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
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# RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
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# RST & !SM_AMIGA_5_.Q & N_96_i & !SM_AMIGA_3_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
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# RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
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# RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_96_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
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# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
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# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
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# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q
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# RST & E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_96_i & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_2_.Q);
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SM_AMIGA_i_7_.C = (CLK_OSZI);
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CIIN_0 = (inst_nEXP_SPACE_D0reg.Q
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# !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
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Reverse-Polarity Equations:
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