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https://github.com/erichelgeson/BlueSCSI.git
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commit
437b2531ca
@ -920,9 +920,6 @@ void writeDataLoop(uint32_t blocksize, const byte* srcptr)
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// Start the first bus cycle.
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FETCH_BSRR_DB();
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REQ_OFF_DB_SET(bsrr_val);
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#ifdef XCVR
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TRANSCEIVER_IO_SET(vTR_DBP,TR_OUTPUT)
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#endif
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REQ_ON();
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FETCH_BSRR_DB();
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WAIT_ACK_ACTIVE();
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@ -959,9 +956,11 @@ void writeDataPhase(int len, const byte* p)
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LOGN("DATAIN PHASE");
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SCSI_PHASE_CHANGE(SCSI_PHASE_DATAIN);
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// Bus settle delay 400ns. Following code was measured at 800ns before REQ asserted. STM32F103.
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#ifdef XCVR
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TRANSCEIVER_IO_SET(vTR_DBP,TR_OUTPUT)
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#endif
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SCSI_DB_OUTPUT()
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writeDataLoop(len, p);
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SCSI_DB_INPUT()
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}
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/*
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@ -977,6 +976,9 @@ void writeDataPhaseSD(uint32_t adds, uint32_t len)
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uint64_t pos = (uint64_t)adds * m_img->m_blocksize;
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m_img->m_file.seekSet(pos);
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#ifdef XCVR
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TRANSCEIVER_IO_SET(vTR_DBP,TR_OUTPUT)
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#endif
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SCSI_DB_OUTPUT()
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for(uint32_t i = 0; i < len; i++) {
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// Asynchronous reads will make it faster ...
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@ -986,10 +988,6 @@ void writeDataPhaseSD(uint32_t adds, uint32_t len)
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writeDataLoop(m_img->m_blocksize, m_buf);
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}
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SCSI_DB_INPUT()
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#ifdef XCVR
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TRANSCEIVER_IO_SET(vTR_DBP,TR_INPUT)
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#endif
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}
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#pragma GCC push_options
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@ -1770,5 +1768,11 @@ BusFree:
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SCSI_TARGET_INACTIVE() // Turn off BSY, REQ, MSG, CD, IO output
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#ifdef XCVR
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TRANSCEIVER_IO_SET(vTR_TARGET,TR_INPUT);
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// Something in code linked after this function is performing better with a +4 alignment.
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// Adding this nop is causing the next function (_GLOBAL__sub_I_SD) to have an address with a last digit of 0x4.
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// Last digit of 0xc also works.
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// This affects both with and without XCVR, currently without XCVR doesn't need any padding.
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// Until the culprit can be tracked down and fixed, it may be necessary to do manual adjustment.
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asm("nop.w");
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#endif
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}
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