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GW28R8128
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19a6bfed01 ... 5579696769

Author SHA1 Message Date
Zane Kaminski 5579696769 Documentation update 2023-01-02 08:27:34 -05:00
Zane Kaminski 150e9b951e Switch to KiCAD 6 3d models 2022-02-05 21:05:09 -05:00
Zane Kaminski 0a7d9b86e5 Migrate to KiCAD 6 2022-02-05 19:08:54 -05:00
Zane Kaminski 86e295eb2e Documentation update 2021-09-04 23:57:26 -04:00
Zane Kaminski 4771972a69 Documentation update 2021-08-06 02:43:51 -04:00
Zane Kaminski c4297fe2d4 Create LICENSE 2021-06-21 12:05:28 -04:00
Zane Kaminski 88347f9627 Delete Description 2021-04-13 03:34:11 -04:00
Zane Kaminski 238c556c60 Update manual 2021-04-03 05:04:19 -04:00
Zane Kaminski 2ed97eb0a2 Create ROM01Manual.pdf 2021-04-03 04:49:52 -04:00
Zane Kaminski df2ae013c5 Documentation update 2021-04-03 04:49:04 -04:00
Zane Kaminski a8c0a311d5 Remove fiducials to look better 2021-04-02 23:54:35 -04:00
Zane Kaminski 16a2c124c9 Enlarged mask bridges 2021-04-02 23:51:40 -04:00
Zane Kaminski 7d311bd45e Remove "J1" text on back of board 2021-04-02 23:39:04 -04:00
Zane Kaminski bc1aca1cf3 Small update 2021-03-12 10:36:39 -05:00
Zane Kaminski fe02aaba93 Fabbed 2020-12-14 09:25:31 -05:00
Zane Kaminski d62c38fcd0 Create Description 2020-07-05 17:18:21 -04:00
34 changed files with 40124 additions and 1977 deletions
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2
.gitignore vendored
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@ -14,6 +14,7 @@ _autosave-*
*-save.pro
*-save.kicad_pcb
fp-info-cache
GW28R8128-backups/*
# Netlist files (exported from Eeschema)
*.net
@ -23,3 +24,4 @@ fp-info-cache
*.ses
*.DS_Store
Documentation/~$M01Manual.docx

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GW28R8128-rescue.dcm
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@ -1,3 +0,0 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

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{
"board": {
"active_layer": 0,
"active_layer_preset": "All Layers",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
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{
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"different_unit_footprint": "error",
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"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
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"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
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"meta": {
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"net_settings": {
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"net_colors": null
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"netlist": "GW28R8128.net",
"specctra_dsn": "",
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1367
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258
GW28R8128.pro
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@ -1,258 +0,0 @@
update=Wednesday, May 20, 2020 at 04:28:46 PM
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=GW28R8128.net
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.1524
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.1524
TrackWidth2=0.2
TrackWidth3=0.254
TrackWidth4=0.508
TrackWidth5=0.762
TrackWidth6=1.27
TrackWidth7=1.524
ViaDiameter1=0.6
ViaDrill1=0.3
ViaDiameter2=0.8
ViaDrill2=0.4
ViaDiameter3=1.524
ViaDrill3=0.762
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.15
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.1524
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.15
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.07619999999999999
SolderMaskMinWidth=0.127
SolderPasteClearance=-0.03809999999999999
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.1524
TrackWidth=0.1524
ViaDiameter=0.6
ViaDrill=0.3
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=Pcbnew
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

353
GW28R8128.sch
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@ -1,353 +0,0 @@
EESchema Schematic File Version 4
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Sheet 1 1
Title "GW28R8128"
Date "2019-07-23"
Rev "1.0"
Comp "Garrett's Workshop"
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
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20
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Copyright (c) Garrett's Workshop
Rationale
----------------------------------------
We at Garrett's Workshop create our products and release their source in
hopes of encouraging others to contribute and build their own "clones,"
even selling them and competing with us. One day, GW will be defunct,
and it would be a shame if our hardware and software die along with GW.
At the same time, however, we seek to protect our trademark and ensure
that clones and derivative products do not masquerade as genuine
Garrett's Workshop products.
License Terms
----------------------------------------
This project may be licensed under one of two licenses:
1. You may elect to license this project under CC BY-NC-SA 4.0.
2. You may elect to license this project under CC BY-SA 4.0 ONLY IF
you remove all "Garrett's Workshop" trademarks from the project.

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G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,(5.1.5-0-10_14)*
G04 #@! TF.CreationDate,2021-04-02T23:53:53-04:00*
G04 #@! TF.ProjectId,GW28R8128,47573238-5238-4313-9238-2e6b69636164,rev?*
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G04 #@! TF.FileFunction,Profile,NP*
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Ref,Val,Package,PosX,PosY,Rot,Side
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### Module positions - created on Friday, April 02, 2021 at 11:54:06 PM ###
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Ref,Val,Package,PosX,PosY,Rot,Side
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5 TP1 ~OE~ Tyco_RCU_0603_Paste 49.784000 -51.943000 0.000000 top
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7 U1 39SF010 PLCC-32 48.260000 -36.830000 0.000000 top

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### Module positions - created on Friday, April 02, 2021 at 11:54:06 PM ###
### Printed by Pcbnew version kicad (5.1.5-0-10_14)
## Unit = mm, Angle = deg.
## Side : top
# Ref Val Package PosX PosY Rot Side
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