Moved 2MB simm to its own folder

2020-05-16 14:21:02 -04:00 · 2020-05-16 14:21:02 -04:00 · 63f7f121f5
parent 8c8b9a2a72
commit 63f7f121f5
11 changed files with 284 additions and 76727 deletions
--- a/ROMSIMM-cache.lib
+++ b/ROMSIMM-cache.lib
@ -1,237 +0,0 @@
-EESchema-LIBRARY Version 2.4
-#encoding utf-8
-#
-# Connector_Generic_Conn_02x32_Counter_Clockwise
-#
-DEF Connector_Generic_Conn_02x32_Counter_Clockwise J 0 40 Y N 1 F N
-F0 "J" 50 1600 50 H V C CNN
-F1 "Connector_Generic_Conn_02x32_Counter_Clockwise" 50 -1700 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- Connector*:*_2x??_*
-$ENDFPLIST
-DRAW
-S -50 -1595 0 -1605 1 1 6 N
-S -50 -1495 0 -1505 1 1 6 N
-S -50 -1395 0 -1405 1 1 6 N
-S -50 -1295 0 -1305 1 1 6 N
-S -50 -1195 0 -1205 1 1 6 N
-S -50 -1095 0 -1105 1 1 6 N
-S -50 -995 0 -1005 1 1 6 N
-S -50 -895 0 -905 1 1 6 N
-S -50 -795 0 -805 1 1 6 N
-S -50 -695 0 -705 1 1 6 N
-S -50 -595 0 -605 1 1 6 N
-S -50 -495 0 -505 1 1 6 N
-S -50 -395 0 -405 1 1 6 N
-S -50 -295 0 -305 1 1 6 N
-S -50 -195 0 -205 1 1 6 N
-S -50 -95 0 -105 1 1 6 N
-S -50 5 0 -5 1 1 6 N
-S -50 105 0 95 1 1 6 N
-S -50 205 0 195 1 1 6 N
-S -50 305 0 295 1 1 6 N
-S -50 405 0 395 1 1 6 N
-S -50 505 0 495 1 1 6 N
-S -50 605 0 595 1 1 6 N
-S -50 705 0 695 1 1 6 N
-S -50 805 0 795 1 1 6 N
-S -50 905 0 895 1 1 6 N
-S -50 1005 0 995 1 1 6 N
-S -50 1105 0 1095 1 1 6 N
-S -50 1205 0 1195 1 1 6 N
-S -50 1305 0 1295 1 1 6 N
-S -50 1405 0 1395 1 1 6 N
-S -50 1505 0 1495 1 1 6 N
-S -50 1550 150 -1650 1 1 10 f
-S 150 -1595 100 -1605 1 1 6 N
-S 150 -1495 100 -1505 1 1 6 N
-S 150 -1395 100 -1405 1 1 6 N
-S 150 -1295 100 -1305 1 1 6 N
-S 150 -1195 100 -1205 1 1 6 N
-S 150 -1095 100 -1105 1 1 6 N
-S 150 -995 100 -1005 1 1 6 N
-S 150 -895 100 -905 1 1 6 N
-S 150 -795 100 -805 1 1 6 N
-S 150 -695 100 -705 1 1 6 N
-S 150 -595 100 -605 1 1 6 N
-S 150 -495 100 -505 1 1 6 N
-S 150 -395 100 -405 1 1 6 N
-S 150 -295 100 -305 1 1 6 N
-S 150 -195 100 -205 1 1 6 N
-S 150 -95 100 -105 1 1 6 N
-S 150 5 100 -5 1 1 6 N
-S 150 105 100 95 1 1 6 N
-S 150 205 100 195 1 1 6 N
-S 150 305 100 295 1 1 6 N
-S 150 405 100 395 1 1 6 N
-S 150 505 100 495 1 1 6 N
-S 150 605 100 595 1 1 6 N
-S 150 705 100 695 1 1 6 N
-S 150 805 100 795 1 1 6 N
-S 150 905 100 895 1 1 6 N
-S 150 1005 100 995 1 1 6 N
-S 150 1105 100 1095 1 1 6 N
-S 150 1205 100 1195 1 1 6 N
-S 150 1305 100 1295 1 1 6 N
-S 150 1405 100 1395 1 1 6 N
-S 150 1505 100 1495 1 1 6 N
-X Pin_1 1 -200 1500 150 R 50 50 1 1 P
-X Pin_10 10 -200 600 150 R 50 50 1 1 P
-X Pin_11 11 -200 500 150 R 50 50 1 1 P
-X Pin_12 12 -200 400 150 R 50 50 1 1 P
-X Pin_13 13 -200 300 150 R 50 50 1 1 P
-X Pin_14 14 -200 200 150 R 50 50 1 1 P
-X Pin_15 15 -200 100 150 R 50 50 1 1 P
-X Pin_16 16 -200 0 150 R 50 50 1 1 P
-X Pin_17 17 -200 -100 150 R 50 50 1 1 P
-X Pin_18 18 -200 -200 150 R 50 50 1 1 P
-X Pin_19 19 -200 -300 150 R 50 50 1 1 P
-X Pin_2 2 -200 1400 150 R 50 50 1 1 P
-X Pin_20 20 -200 -400 150 R 50 50 1 1 P
-X Pin_21 21 -200 -500 150 R 50 50 1 1 P
-X Pin_22 22 -200 -600 150 R 50 50 1 1 P
-X Pin_23 23 -200 -700 150 R 50 50 1 1 P
-X Pin_24 24 -200 -800 150 R 50 50 1 1 P
-X Pin_25 25 -200 -900 150 R 50 50 1 1 P
-X Pin_26 26 -200 -1000 150 R 50 50 1 1 P
-X Pin_27 27 -200 -1100 150 R 50 50 1 1 P
-X Pin_28 28 -200 -1200 150 R 50 50 1 1 P
-X Pin_29 29 -200 -1300 150 R 50 50 1 1 P
-X Pin_3 3 -200 1300 150 R 50 50 1 1 P
-X Pin_30 30 -200 -1400 150 R 50 50 1 1 P
-X Pin_31 31 -200 -1500 150 R 50 50 1 1 P
-X Pin_32 32 -200 -1600 150 R 50 50 1 1 P
-X Pin_33 33 300 -1600 150 L 50 50 1 1 P
-X Pin_34 34 300 -1500 150 L 50 50 1 1 P
-X Pin_35 35 300 -1400 150 L 50 50 1 1 P
-X Pin_36 36 300 -1300 150 L 50 50 1 1 P
-X Pin_37 37 300 -1200 150 L 50 50 1 1 P
-X Pin_38 38 300 -1100 150 L 50 50 1 1 P
-X Pin_39 39 300 -1000 150 L 50 50 1 1 P
-X Pin_4 4 -200 1200 150 R 50 50 1 1 P
-X Pin_40 40 300 -900 150 L 50 50 1 1 P
-X Pin_41 41 300 -800 150 L 50 50 1 1 P
-X Pin_42 42 300 -700 150 L 50 50 1 1 P
-X Pin_43 43 300 -600 150 L 50 50 1 1 P
-X Pin_44 44 300 -500 150 L 50 50 1 1 P
-X Pin_45 45 300 -400 150 L 50 50 1 1 P
-X Pin_46 46 300 -300 150 L 50 50 1 1 P
-X Pin_47 47 300 -200 150 L 50 50 1 1 P
-X Pin_48 48 300 -100 150 L 50 50 1 1 P
-X Pin_49 49 300 0 150 L 50 50 1 1 P
-X Pin_5 5 -200 1100 150 R 50 50 1 1 P
-X Pin_50 50 300 100 150 L 50 50 1 1 P
-X Pin_51 51 300 200 150 L 50 50 1 1 P
-X Pin_52 52 300 300 150 L 50 50 1 1 P
-X Pin_53 53 300 400 150 L 50 50 1 1 P
-X Pin_54 54 300 500 150 L 50 50 1 1 P
-X Pin_55 55 300 600 150 L 50 50 1 1 P
-X Pin_56 56 300 700 150 L 50 50 1 1 P
-X Pin_57 57 300 800 150 L 50 50 1 1 P
-X Pin_58 58 300 900 150 L 50 50 1 1 P
-X Pin_59 59 300 1000 150 L 50 50 1 1 P
-X Pin_6 6 -200 1000 150 R 50 50 1 1 P
-X Pin_60 60 300 1100 150 L 50 50 1 1 P
-X Pin_61 61 300 1200 150 L 50 50 1 1 P
-X Pin_62 62 300 1300 150 L 50 50 1 1 P
-X Pin_63 63 300 1400 150 L 50 50 1 1 P
-X Pin_64 64 300 1500 150 L 50 50 1 1 P
-X Pin_7 7 -200 900 150 R 50 50 1 1 P
-X Pin_8 8 -200 800 150 R 50 50 1 1 P
-X Pin_9 9 -200 700 150 R 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# Device_C_Small
-#
-DEF Device_C_Small C 0 10 N N 1 F N
-F0 "C" 10 70 50 H V L CNN
-F1 "Device_C_Small" 10 -80 50 H V L CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-$FPLIST
- C_*
-$ENDFPLIST
-DRAW
-P 2 0 1 13 -60 -20 60 -20 N
-P 2 0 1 12 -60 20 60 20 N
-X ~ 1 0 100 80 D 50 50 1 1 P
-X ~ 2 0 -100 80 U 50 50 1 1 P
-ENDDRAW
-ENDDEF
-#
-# GW_RAM_Flash-512Kx8-PLCC-32
-#
-DEF GW_RAM_Flash-512Kx8-PLCC-32 U 0 20 Y Y 1 F N
-F0 "U" 0 1050 50 H V C CNN
-F1 "GW_RAM_Flash-512Kx8-PLCC-32" 0 0 50 V V C CNN
-F2 "stdpads:PLCC-32_SMDSocket" 0 -1050 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-S -300 1000 300 -1000 0 1 10 f
-X GND 16 400 -900 100 L 50 50 0 0 W
-X VCC 32 400 900 100 L 50 50 0 0 W
-X A18 1 -400 -900 100 R 50 50 1 1 I
-X A2 10 -400 700 100 R 50 50 1 1 I
-X A1 11 -400 800 100 R 50 50 1 1 I
-X A0 12 -400 900 100 R 50 50 1 1 I
-X D0 13 400 700 100 L 50 50 1 1 B
-X D1 14 400 600 100 L 50 50 1 1 B
-X D2 15 400 500 100 L 50 50 1 1 B
-X D3 17 400 400 100 L 50 50 1 1 B
-X D4 18 400 300 100 L 50 50 1 1 B
-X D5 19 400 200 100 L 50 50 1 1 B
-X A16 2 -400 -700 100 R 50 50 1 1 I
-X D6 20 400 100 100 L 50 50 1 1 B
-X D7 21 400 0 100 L 50 50 1 1 B
-X ~CS~ 22 400 -400 100 L 50 50 1 1 I
-X A10 23 -400 -100 100 R 50 50 1 1 I
-X ~OE~ 24 400 -600 100 L 50 50 1 1 I
-X A11 25 -400 -200 100 R 50 50 1 1 I
-X A9 26 -400 0 100 R 50 50 1 1 I
-X A8 27 -400 100 100 R 50 50 1 1 I
-X A13 28 -400 -400 100 R 50 50 1 1 I
-X A14 29 -400 -500 100 R 50 50 1 1 I
-X A15 3 -400 -600 100 R 50 50 1 1 I
-X A17 30 -400 -800 100 R 50 50 1 1 I
-X ~WE~ 31 400 -500 100 L 50 50 1 1 I
-X A12 4 -400 -300 100 R 50 50 1 1 I
-X A7 5 -400 200 100 R 50 50 1 1 I
-X A6 6 -400 300 100 R 50 50 1 1 I
-X A5 7 -400 400 100 R 50 50 1 1 I
-X A4 8 -400 500 100 R 50 50 1 1 I
-X A3 9 -400 600 100 R 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
-# power_+5V
-#
-DEF power_+5V #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -150 50 H I C CNN
-F1 "power_+5V" 0 140 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 2 0 1 0 -30 50 0 100 N
-P 2 0 1 0 0 0 0 100 N
-P 2 0 1 0 0 100 30 50 N
-X +5V 1 0 0 0 U 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-# power_GND
-#
-DEF power_GND #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "power_GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
-#End Library
--- a/ROMSIMM.4401A-gerber.zip
+++ b/ROMSIMM.4401A-gerber.zip
--- a/ROMSIMM.pro
+++ b/ROMSIMM.pro
@ -1,10 +1,29 @@
-update=Thursday, May 14, 2020 at 06:45:41 PM
+update=22/05/2015 07:44:53
 version=1
 last_client=kicad
 [general]
 version=1
 RootSch=
 BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
 [cvpcb]
 version=1
 NetIExt=net
@ -12,246 +31,3 @@ NetIExt=net
 version=1
 LibDir=
 [eeschema/libraries]
-[schematic_editor]
-version=1
-PageLayoutDescrFile=
-PlotDirectoryName=
-SubpartIdSeparator=0
-SubpartFirstId=65
-NetFmtName=Pcbnew
-SpiceAjustPassiveValues=0
-LabSize=50
-ERC_TestSimilarLabels=1
-[pcbnew]
-version=1
-PageLayoutDescrFile=
-LastNetListRead=ROMSIMM.net
-CopperLayerCount=4
-BoardThickness=1.6
-AllowMicroVias=0
-AllowBlindVias=0
-RequireCourtyardDefinitions=0
-ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.127
-MinViaDiameter=0.508
-MinViaDrill=0.2
-MinMicroViaDiameter=0.2
-MinMicroViaDrill=0.09999999999999999
-MinHoleToHole=0.25
-TrackWidth1=0.1524
-TrackWidth2=0.1524
-TrackWidth3=0.254
-TrackWidth4=0.508
-TrackWidth5=0.762
-TrackWidth6=0.8
-TrackWidth7=1.27
-TrackWidth8=1.524
-ViaDiameter1=0.508
-ViaDrill1=0.2
-ViaDiameter2=0.8
-ViaDrill2=0.4
-dPairWidth1=0.2
-dPairGap1=0.25
-dPairViaGap1=0.25
-SilkLineWidth=0.15
-SilkTextSizeV=1
-SilkTextSizeH=1
-SilkTextSizeThickness=0.15
-SilkTextItalic=0
-SilkTextUpright=1
-CopperLineWidth=0.2
-CopperTextSizeV=1.5
-CopperTextSizeH=1.5
-CopperTextThickness=0.3
-CopperTextItalic=0
-CopperTextUpright=1
-EdgeCutLineWidth=0.15
-CourtyardLineWidth=0.05
-OthersLineWidth=0.15
-OthersTextSizeV=1
-OthersTextSizeH=1
-OthersTextSizeThickness=0.15
-OthersTextItalic=0
-OthersTextUpright=1
-SolderMaskClearance=0.07619999999999999
-SolderMaskMinWidth=0.1524
-SolderPasteClearance=-0.03809999999999999
-SolderPasteRatio=0
-[pcbnew/Layer.F.Cu]
-Name=F.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.In1.Cu]
-Name=In1.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.In2.Cu]
-Name=In2.Cu
-Type=0
-Enabled=1
-[pcbnew/Layer.In3.Cu]
-Name=In3.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In4.Cu]
-Name=In4.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In5.Cu]
-Name=In5.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In6.Cu]
-Name=In6.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In7.Cu]
-Name=In7.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In8.Cu]
-Name=In8.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In9.Cu]
-Name=In9.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In10.Cu]
-Name=In10.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In11.Cu]
-Name=In11.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In12.Cu]
-Name=In12.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In13.Cu]
-Name=In13.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In14.Cu]
-Name=In14.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In15.Cu]
-Name=In15.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In16.Cu]
-Name=In16.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In17.Cu]
-Name=In17.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In18.Cu]
-Name=In18.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In19.Cu]
-Name=In19.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In20.Cu]
-Name=In20.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In21.Cu]
-Name=In21.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In22.Cu]
-Name=In22.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In23.Cu]
-Name=In23.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In24.Cu]
-Name=In24.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In25.Cu]
-Name=In25.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In26.Cu]
-Name=In26.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In27.Cu]
-Name=In27.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In28.Cu]
-Name=In28.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In29.Cu]
-Name=In29.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.In30.Cu]
-Name=In30.Cu
-Type=0
-Enabled=0
-[pcbnew/Layer.B.Cu]
-Name=B.Cu
-Type=1
-Enabled=1
-[pcbnew/Layer.B.Adhes]
-Enabled=1
-[pcbnew/Layer.F.Adhes]
-Enabled=1
-[pcbnew/Layer.B.Paste]
-Enabled=1
-[pcbnew/Layer.F.Paste]
-Enabled=1
-[pcbnew/Layer.B.SilkS]
-Enabled=1
-[pcbnew/Layer.F.SilkS]
-Enabled=1
-[pcbnew/Layer.B.Mask]
-Enabled=1
-[pcbnew/Layer.F.Mask]
-Enabled=1
-[pcbnew/Layer.Dwgs.User]
-Enabled=1
-[pcbnew/Layer.Cmts.User]
-Enabled=1
-[pcbnew/Layer.Eco1.User]
-Enabled=1
-[pcbnew/Layer.Eco2.User]
-Enabled=1
-[pcbnew/Layer.Edge.Cuts]
-Enabled=1
-[pcbnew/Layer.Margin]
-Enabled=1
-[pcbnew/Layer.B.CrtYd]
-Enabled=1
-[pcbnew/Layer.F.CrtYd]
-Enabled=1
-[pcbnew/Layer.B.Fab]
-Enabled=1
-[pcbnew/Layer.F.Fab]
-Enabled=1
-[pcbnew/Layer.Rescue]
-Enabled=0
-[pcbnew/Netclasses]
-[pcbnew/Netclasses/Default]
-Name=Default
-Clearance=0.1524
-TrackWidth=0.1524
-ViaDiameter=0.508
-ViaDrill=0.2
-uViaDiameter=0.3
-uViaDrill=0.1
-dPairWidth=0.2
-dPairGap=0.25
-dPairViaGap=0.25
--- a/SIMM2MB.4401A/ROMSIMM.kicad_pcb
+++ b/SIMM2MB.4401A/ROMSIMM.kicad_pcb
@ -915,7 +915,7 @@
      (net 4 /~WE~))
    (pad 32 smd roundrect (at 1.27 -6.8375) (size 0.6 1.475) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
      (net 1 +5V))
-    (model ${KIPRJMOD}/../stdpads.3dshapes/PLCC-32_PTHSocket.wrl
+    (model ${KIPRJMOD}/../../stdpads.3dshapes/PLCC-32_PTHSocket.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 0.5))
      (rotate (xyz 0 0 180))
--- a/SIMM2MB.4401A/ROMSIMM.pro
+++ b/SIMM2MB.4401A/ROMSIMM.pro
@ -0,0 +1,257 @@
+update=Thursday, May 14, 2020 at 06:45:41 PM
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=Pcbnew
+SpiceAjustPassiveValues=0
+LabSize=50
+ERC_TestSimilarLabels=1
+[pcbnew]
+version=1
+PageLayoutDescrFile=
+LastNetListRead=ROMSIMM.net
+CopperLayerCount=4
+BoardThickness=1.6
+AllowMicroVias=0
+AllowBlindVias=0
+RequireCourtyardDefinitions=0
+ProhibitOverlappingCourtyards=1
+MinTrackWidth=0.127
+MinViaDiameter=0.508
+MinViaDrill=0.2
+MinMicroViaDiameter=0.2
+MinMicroViaDrill=0.09999999999999999
+MinHoleToHole=0.25
+TrackWidth1=0.1524
+TrackWidth2=0.1524
+TrackWidth3=0.254
+TrackWidth4=0.508
+TrackWidth5=0.762
+TrackWidth6=0.8
+TrackWidth7=1.27
+TrackWidth8=1.524
+ViaDiameter1=0.508
+ViaDrill1=0.2
+ViaDiameter2=0.8
+ViaDrill2=0.4
+dPairWidth1=0.2
+dPairGap1=0.25
+dPairViaGap1=0.25
+SilkLineWidth=0.15
+SilkTextSizeV=1
+SilkTextSizeH=1
+SilkTextSizeThickness=0.15
+SilkTextItalic=0
+SilkTextUpright=1
+CopperLineWidth=0.2
+CopperTextSizeV=1.5
+CopperTextSizeH=1.5
+CopperTextThickness=0.3
+CopperTextItalic=0
+CopperTextUpright=1
+EdgeCutLineWidth=0.15
+CourtyardLineWidth=0.05
+OthersLineWidth=0.15
+OthersTextSizeV=1
+OthersTextSizeH=1
+OthersTextSizeThickness=0.15
+OthersTextItalic=0
+OthersTextUpright=1
+SolderMaskClearance=0.07619999999999999
+SolderMaskMinWidth=0.1524
+SolderPasteClearance=-0.03809999999999999
+SolderPasteRatio=0
+[pcbnew/Layer.F.Cu]
+Name=F.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In1.Cu]
+Name=In1.Cu
+Type=1
+Enabled=1
+[pcbnew/Layer.In2.Cu]
+Name=In2.Cu
+Type=0
+Enabled=1
+[pcbnew/Layer.In3.Cu]
+Name=In3.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In4.Cu]
+Name=In4.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In5.Cu]
+Name=In5.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In6.Cu]
+Name=In6.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In7.Cu]
+Name=In7.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In8.Cu]
+Name=In8.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In9.Cu]
+Name=In9.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In10.Cu]
+Name=In10.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In11.Cu]
+Name=In11.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In12.Cu]
+Name=In12.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In13.Cu]
+Name=In13.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In14.Cu]
+Name=In14.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In15.Cu]
+Name=In15.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In16.Cu]
+Name=In16.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In17.Cu]
+Name=In17.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In18.Cu]
+Name=In18.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In19.Cu]
+Name=In19.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In20.Cu]
+Name=In20.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In21.Cu]
+Name=In21.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In22.Cu]
+Name=In22.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In23.Cu]
+Name=In23.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In24.Cu]
+Name=In24.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In25.Cu]
+Name=In25.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In26.Cu]
+Name=In26.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In27.Cu]
+Name=In27.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In28.Cu]
+Name=In28.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In29.Cu]
+Name=In29.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.In30.Cu]
+Name=In30.Cu
+Type=0
+Enabled=0
+[pcbnew/Layer.B.Cu]
+Name=B.Cu
+Type=1
+Enabled=1
+[pcbnew/Layer.B.Adhes]
+Enabled=1
+[pcbnew/Layer.F.Adhes]
+Enabled=1
+[pcbnew/Layer.B.Paste]
+Enabled=1
+[pcbnew/Layer.F.Paste]
+Enabled=1
+[pcbnew/Layer.B.SilkS]
+Enabled=1
+[pcbnew/Layer.F.SilkS]
+Enabled=1
+[pcbnew/Layer.B.Mask]
+Enabled=1
+[pcbnew/Layer.F.Mask]
+Enabled=1
+[pcbnew/Layer.Dwgs.User]
+Enabled=1
+[pcbnew/Layer.Cmts.User]
+Enabled=1
+[pcbnew/Layer.Eco1.User]
+Enabled=1
+[pcbnew/Layer.Eco2.User]
+Enabled=1
+[pcbnew/Layer.Edge.Cuts]
+Enabled=1
+[pcbnew/Layer.Margin]
+Enabled=1
+[pcbnew/Layer.B.CrtYd]
+Enabled=1
+[pcbnew/Layer.F.CrtYd]
+Enabled=1
+[pcbnew/Layer.B.Fab]
+Enabled=1
+[pcbnew/Layer.F.Fab]
+Enabled=1
+[pcbnew/Layer.Rescue]
+Enabled=0
+[pcbnew/Netclasses]
+[pcbnew/Netclasses/Default]
+Name=Default
+Clearance=0.1524
+TrackWidth=0.1524
+ViaDiameter=0.508
+ViaDrill=0.2
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25
--- a/SIMM2MB.4401A/ROMSIMM.sch
+++ b/SIMM2MB.4401A/ROMSIMM.sch
--- a/SIMM2MB.4401A/fp-lib-table
+++ b/SIMM2MB.4401A/fp-lib-table
@ -0,0 +1,3 @@
+(fp_lib_table
+  (lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../../stdpads.pretty")(options "")(descr ""))
+)
--- a/SIMM2MB.4401A/sym-lib-table
+++ b/SIMM2MB.4401A/sym-lib-table
@ -0,0 +1,3 @@
+(sym_lib_table
+  (lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../../GW_Parts/GW_RAM.lib")(options "")(descr ""))
+)
--- a/76238
+++ b/76238
--- a/3
+++ b/3
@ -1,3 +0,0 @@
-(fp_lib_table
-  (lib (name stdpads)(type KiCad)(uri "$(KIPRJMOD)/../stdpads.pretty")(options "")(descr ""))
-)
--- a/4
+++ b/4
@ -1,4 +0,0 @@
-(sym_lib_table
-  (lib (name GW_RAM)(type Legacy)(uri "$(KIPRJMOD)/../GW_Parts/GW_RAM.lib")(options "")(descr ""))
-  (lib (name ROMSIMM-rescue)(type Legacy)(uri ${KIPRJMOD}/ROMSIMM-rescue.lib)(options "")(descr ""))
-)