Correct aspect ratio, update sys, update readme (#10)
* Correct aspect ratio Early compact Macintoshes (including the Plus) use 512 by 342 resolution monochrome monitors with 1:1 PAR and 256:171 DAR. * Update readme.md Bring readme up-to-date with latest core * Update sys Update sys to latest version * Update sys & readme
This commit is contained in:
meauxdal
GitHub
parent
708e2e510f
commit
32e223ac31
23
MacPlus.qsf
23
MacPlus.qsf
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@ -50,6 +50,29 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
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set_global_assignment -name SEED 1
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
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#enable it only if 8bit indexed mode is used in core
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#set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
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#do not enable DEBUG_NOHDMI in release!
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#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
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# disable bilinear filtering when downscaling
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#set_global_assignment -name VERILOG_MACRO "MISTER_DOWNSCALE_NN=1"
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# disable adaptive scanline filtering
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#set_global_assignment -name VERILOG_MACRO "MISTER_DISABLE_ADAPTIVE=1"
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#use only 1MB per frame for scaler to free ~21MB DDR3 RAM
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#set_global_assignment -name VERILOG_MACRO "MISTER_SMALL_VBUF=1"
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# Disable YC / Composite output to save some resources
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#set_global_assignment -name VERILOG_MACRO "MISTER_DISABLE_YC=1"
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# Disable ALSA audio output to save some resources
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#set_global_assignment -name VERILOG_MACRO "MISTER_DISABLE_ALSA=1"
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source sys/sys.tcl
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source sys/sys_analog.tcl
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source files.qip
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@ -195,8 +195,8 @@ video_freak video_freak
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.VGA_DE_IN(VGA_DE),
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.VGA_DE(),
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.ARX((!ar) ? 12'd4 : (ar - 1'd1)),
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.ARY((!ar) ? 12'd3 : 12'd0),
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.ARX((!ar) ? 12'd256 : (ar - 1'd1)),
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.ARY((!ar) ? 12'd171 : 12'd0),
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.CROP_SIZE(0),
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.CROP_OFF(0),
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.SCALE(status[12:11])
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@ -223,6 +223,9 @@ localparam CONF_STR = {
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//"OA,Serial,Off,On;",
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//"-;",
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"R0,Reset & Apply CPU+Memory;",
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"v,0;", // [optional] config version 0-99.
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// If CONF_STR options are changed in incompatible way, then change version number too,
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// so all options will get default values on first start.
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"V,v",`BUILD_DATE
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};
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42
readme.md
42
readme.md
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@ -2,50 +2,52 @@
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This is a port of the [Plus Too core](https://github.com/mist-devel/mist-binaries/tree/master/cores/plus_too) from MiST which is the port of the [Plus Too project](http://www.bigmessowires.com/plus-too/).
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I've tried to optimize the code with converting to synchronous style and fixing some glitches and instabilities.
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I've tried to optimize the code by converting to synchronous style and fixing some glitches and instabilities.
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## Usage
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* Copy the [*.rbf](https://github.com/MiSTer-devel/MacPlus_MiSTer/tree/master/releases) onto the root of SD card
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* Copy the [boot.rom](https://github.com/MiSTer-devel/MacPlus_MiSTer/tree/master/releases) to MacPlus folder
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* Copy [boot0.rom & boot1.rom](https://github.com/MiSTer-devel/MacPlus_MiSTer/tree/master/releases) (Plus and SE ROM files) to MacPlus folder
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* Copy disk images in dsk format (e.g. Disk605.dsk) to MacPlus folder
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After a few seconds the floppy disk icon should
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appear. Open the on screen display using the F12 key and select the
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a disk image. The upload of the disk image will take a few seconds. MacPlus will then boot into the MacOS desktop.
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After a few seconds, the floppy disk icon should appear. Open the on-screen display using the F12 key and select the a disk image. The upload of the disk image will take a few seconds. If a bootable system is found on disk, a smiling Mac icon will appear. MacPlus will then begin booting into the desktop.
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## Floppy disk image format
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## Floppy disk support
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Floppy disk images need to be in raw disk format. Double sided 800k disk images have to be exactly 819200 bytes in size. Single sided 400k disk images have to be exactly 409600 bytes in size.
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Internal and external floppy disk drives are both supported. The first and second entries in the OSD correspond to the internal and external floppy disk drives, respectively.
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Both the internal as well as the external floppy disk are supported. The first entry in the OSD refers to the internal floppy disk, the second one to the external floppy disk.
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Floppy disk images need to be in raw disk format (a.k.a. DiskDup format) with a .dsk extension. Single-sided 400k disk images must be exactly 409,600 bytes in size. Double-sided 800k disk images must be exactly 819,200 bytes in size. Disk Copy 4.2 files are not currently supported. They are largely the same as raw disk format, but include an additional 84-byte header. A tool to convert DC42 format to dsk is available [here](https://www.bigmessowires.com/2013/12/16/macintosh-diskcopy-4-2-floppy-image-converter/).
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Currently floppy disk images cannot be loaded while the Mac accesses a floppy disk. Thus it's recommended to wait for the desktop to appear until a second floppy can be inserted.
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Currently, floppy disk images are not writable within the core.
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Before loading a different disk image it's recommended to eject the previously inserted disk image from within MacOS.
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Floppy disk images cannot be loaded while the Mac accesses a floppy disk. Thus, it's recommended to wait for the desktop to appear until a second floppy can be inserted. Before loading a different disk image, it's recommended to eject the previously inserted disk image from within the OS.
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Official system disk images are available from apple at [here](https://web.archive.org/web/20141025043714/http://www.info.apple.com/support/oldersoftwarelist.html). Under Linux these can be converted into the desired dsk format using [Linux stuffit](http://web.archive.org/web/20060205025441/http://www.stuffit.com/downloads/files/stuffit520.611linux-i386.tar.gz), unar and [dc2dsk](http://www.bigmessowires.com/dc2dsk.c) in that order. A shell script has been provided for convenience at [releases/bin2dsk.sh](releases/bin2dsk.sh).
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Note that the floppy disk drive will not be read when the CPU speed is set to 16 MHz.
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Official system disk images are available from an archived Apple support page [here](https://web.archive.org/web/20141025043714/http://www.info.apple.com/support/oldersoftwarelist.html). Under Linux these can be converted into the desired dsk format using [Linux StuffIt](http://web.archive.org/web/20060205025441/http://www.stuffit.com/downloads/files/stuffit520.611linux-i386.tar.gz), unar, and [dc2dsk](http://www.bigmessowires.com/dc2dsk.c), in that order. A shell script has been provided for convenience at [releases/bin2dsk.sh](releases/bin2dsk.sh).
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## Hard disk support
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This MacPlus core implements the SCSI interface of the Macintosh Plus together with a 20MB harddisk. The core implements only a subset of the SCSI commands. This is currently sufficient to read and write the disk, to boot from it and to format it using the setup tools that come with MacOS 6.0.8.
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The MacPlus core supports SCSI hard drive images up to 2GB (HFS) in size, with a .vhd extension. The core currently implements only a subset of the SCSI commands. This is sufficient to read and write the disk, to boot from it, and to format it using the setup tools that come with System 6.0.8.
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The harddisk image to be used can be selected from the "Mount *.vhd" entry in the on-screen-display. Copy the boot.vhd to MacPlus folder and it will be automatically mounted at start. The format of the disk image is the same as being used by the SCSI2SD project which is documented [here](http://www.codesrc.com/mediawiki/index.php?title=HFSFromScratch).
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The harddisk image to be used can be selected from the "Mount *.vhd" entry in the on-screen-display. Copy the boot.vhd to MacPlus folder and it will be automatically mounted at start. The format of the disk image is the same as the one used by the SCSI2SD project, documented [here](http://www.codesrc.com/mediawiki/index.php?title=HFSFromScratch).
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Unlike the floppy the SCSI disk is writable and data can be written to the disk from within the core.
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Unlike the floppy, the SCSI disk is writable and data can be written to the disk from within the core.
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It has been tested that OS 6.0.8 can format the SCSI disk as well as doing a full installation from floppy disk to the harddisk. But keep in mind that this is an early work in progress and expect data loss when working with HDD images.
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It has been tested that System 6.0.8 can format the SCSI disk, as well as doing a full installation from floppy disk to the harddisk. However, keep in mind the core is an early work in progress and expect data loss when working with HDD images.
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A matching harddisk image file can be found [here](https://github.com/MiSTer-devel/MacPlus_MiSTer/tree/master/releases). This is a 20MB harddisk image with correct partitioning information and a basic SCSI driver installed. The data partition itself is empty and unformatted. After booting the Mac will thus ask whether the disk is to be initialized. Saying yes and giving the disk a name will result im a usable file system. You don't need to use the Setup tool to format this disk as it is already formatted. But you can format it if you want to. This is only been tested with OS 6.0.8.
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A matching harddisk image file can be found [here](https://github.com/MiSTer-devel/MacPlus_MiSTer/tree/master/releases). This is a 20MB harddisk image with correct partitioning information and a basic SCSI driver installed. The data partition itself is empty and unformatted. After booting the Mac will thus ask whether the disk is to be initialized. Saying yes and giving the disk a name will result in a usable file system. You don't need to use the Setup tool to format this disk as it is already formatted, but you can format it if you want to. This has only been tested with System 6.0.8.
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A tool to create harddisk images (with working SCSI driver and partition table) is available [here](https://diskjockey.onegeekarmy.eu/).
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## CPU Speed
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The CPU speed can be adjusted from "normal" which is roughly Mac Plus speed to "Fast" which is about 2.5 times faster. Original core couldn't boot from SCSI in turbo mode. This port has workaround to let it boot even with turbo mode.
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The CPU speed can be adjusted to 8 MHz (original speed) or 16 MHz. This port implements a workaround to allow booting from SCSI when using the 16 MHz configuration.
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## Memory
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512KB, 1MB and 4MB memory configs are available. Cold boot with 4MB RAM selected takes some time before it start to boot from FDD/SCSI, so be patient. Warm boot won't take long time.
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1MB and 4MB memory configurations are available. Cold boot with 4MB RAM selected takes some time before it starts to boot from FDD/SCSI, so be patient. Warm boot won't take as long.
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## Keyboard
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The Alt key is mapped to the Mac's command key, and the Windows key is mapped to the Mac's option key. Core emulates keyboard with keypad.
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The Alt key is mapped to the Mac's Command (⌘) key, and the Windows key is mapped to the Mac's Option (⌥) key. Core emulates keyboard with numeric keypad.
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@ -226,7 +226,7 @@ video_calc video_calc
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.new_vmode(new_vmode),
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.video_rotated(video_rotated),
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.par_num(byte_cnt[3:0]),
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.par_num(byte_cnt[4:0]),
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.dout(vc_dout)
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);
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@ -502,7 +502,7 @@ always@(posedge clk_sys) begin : uio_block
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'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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//Video res.
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'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
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'h23: if(!byte_cnt[MAX_W:5]) io_dout <= vc_dout;
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//RTC
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'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
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@ -872,7 +872,7 @@ module video_calc
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input new_vmode,
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input video_rotated,
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input [3:0] par_num,
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input [4:0] par_num,
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output reg [15:0] dout
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);
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@ -893,6 +893,9 @@ always @(posedge clk_sys) begin
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13: dout <= vid_vtime_hdmi[31:16];
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14: dout <= vid_ccnt[15:0];
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15: dout <= vid_ccnt[31:16];
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16: dout <= vid_pixrep;
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17: dout <= vid_de_h;
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18: dout <= vid_de_v;
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default dout <= 0;
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endcase
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end
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@ -902,24 +905,44 @@ reg [31:0] vid_vcnt = 0;
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reg [31:0] vid_ccnt = 0;
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reg [7:0] vid_nres = 0;
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reg [1:0] vid_int = 0;
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reg [7:0] vid_pixrep;
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reg [15:0] vid_de_h;
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reg [7:0] vid_de_v;
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always @(posedge clk_vid) begin
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integer hcnt;
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integer vcnt;
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integer ccnt;
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reg old_vs= 0, old_de = 0, old_vmode = 0;
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reg [7:0] pcnt;
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reg [7:0] de_v;
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reg [15:0] de_h;
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reg old_vs = 0, old_hs = 0, old_hs_vclk = 0, old_de = 0, old_de_vclk = 0, old_de1 = 0, old_vmode = 0;
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reg [3:0] resto = 0;
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reg calch = 0;
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if(calch & de) ccnt <= ccnt + 1;
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pcnt <= pcnt + 1'd1;
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old_hs_vclk <= hs;
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de_h <= de_h + 1'd1;
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if(old_hs_vclk & ~hs) de_h <= 1;
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old_de_vclk <= de;
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if(calch & ~old_de_vclk & de) vid_de_h <= de_h;
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if(ce_pix) begin
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old_vs <= vs;
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old_hs <= hs;
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old_de <= de;
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old_de1 <= old_de;
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pcnt <= 1;
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if(~vs & ~old_de & de) vcnt <= vcnt + 1;
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if(calch & de) hcnt <= hcnt + 1;
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if(old_de & ~de) calch <= 0;
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if(~old_de1 & old_de) vid_pixrep <= pcnt;
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if(old_hs & ~hs) de_v <= de_v + 1'd1;
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if(calch & ~old_de & de) vid_de_v <= de_v;
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if(old_vs & ~vs) begin
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vid_int <= {vid_int[0],f1};
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@ -939,6 +962,7 @@ always @(posedge clk_vid) begin
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hcnt <= 0;
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ccnt <= 0;
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calch <= 1;
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de_v <= 0;
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end
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end
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end
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@ -8,7 +8,9 @@ module mcp23009
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output reg [2:0] btn,
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input [2:0] led,
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output reg sd_cd,
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output reg flg_sd_cd,
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output reg flg_present,
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output reg flg_mode,
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output scl,
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inout sda
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@ -50,7 +52,9 @@ always@(posedge clk) begin
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idx <= 0;
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btn <= 0;
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rw <= 0;
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sd_cd <= 1;
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flg_sd_cd <= 1;
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flg_present <= 0;
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flg_mode <= 1;
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end
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else begin
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if(~&init_data[idx]) begin
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@ -84,7 +88,10 @@ always@(posedge clk) begin
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state <= 0;
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rw <= 0;
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if(!error) begin
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if(rw) {sd_cd, btn} <= {dout[7], dout[5:3]};
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if(rw) begin
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{flg_sd_cd, flg_mode, btn} <= {dout[7:3]};
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flg_present <= 1;
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end
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rw <= ~rw;
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end
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end
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@ -1,44 +1,5 @@
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
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set_global_assignment -library "pll_cfg" -name MISC_FILE [file join $::quartus(qip_path) "pll_cfg.cmp"]
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_QSYS_MODE "UNKNOWN"
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set_global_assignment -name SYNTHESIS_ONLY_QIP ON
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_NAME "cGxsX2hkbWlfY2Zn"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
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set_global_assignment -entity "pll_cfg" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_NAME "YWx0ZXJhX3BsbF9yZWNvbmZpZ190b3A="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTCBSZWNvbmZpZw=="
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_INTERNAL "Off"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
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set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_VERSION "MTcuMA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIFJlY29uZmlndXJhdGlvbiBCbG9jayhBTFRFUkFfUExMX1JFQ09ORklHKQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "ZGV2aWNlX2ZhbWlseQ==::Q3ljbG9uZSBW::ZGV2aWNlX2ZhbWlseQ=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX01JRg==::ZmFsc2U=::RW5hYmxlIE1JRiBTdHJlYW1pbmc="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0JZVEVFTkFCTEU=::ZmFsc2U=::QWRkIGJ5dGVlbmFibGUgcG9ydA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "QllURUVOQUJMRV9XSURUSA==::NA==::QllURUVOQUJMRV9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfQUREUl9XSURUSA==::Ng==::UkVDT05GSUdfQUREUl9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "UkVDT05GSUdfREFUQV9XSURUSA==::MzI=::UkVDT05GSUdfREFUQV9XSURUSA=="
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "cmVjb25mX3dpZHRo::NjQ=::cmVjb25mX3dpZHRo"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_COMPONENT_PARAMETER "V0FJVF9GT1JfTE9DSw==::dHJ1ZQ==::V0FJVF9GT1JfTE9DSw=="
|
||||
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/pll_cfg_hdmi.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_top.v"]
|
||||
set_global_assignment -library "pll_cfg" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_cfg/altera_pll_reconfig_core.v"]
|
||||
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_NAME "altera_pll_reconfig"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_VERSION "17.0"
|
||||
set_global_assignment -entity "altera_pll_reconfig_top" -library "pll_cfg" -name IP_TOOL_ENV "mwpim"
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
module altera_pll_reconfig_core
|
||||
#(
|
||||
parameter reconf_width = 64,
|
||||
parameter device_family = "Stratix V",
|
||||
parameter device_family = "Cyclone V",
|
||||
// MIF Streaming parameters
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
|
|
@ -1883,7 +1883,7 @@ module fpll_dprio_init (
|
|||
endmodule
|
||||
module dyn_phase_shift
|
||||
#(
|
||||
parameter device_family = "Stratix V"
|
||||
parameter device_family = "Cyclone V"
|
||||
) (
|
||||
|
||||
input wire clk,
|
||||
|
|
@ -2112,7 +2112,7 @@ endmodule
|
|||
module generic_lcell_comb
|
||||
#(
|
||||
//parameter
|
||||
parameter family = "Stratix V",
|
||||
parameter family = "Cyclone V",
|
||||
parameter lut_mask = 64'hAAAAAAAAAAAAAAAA,
|
||||
parameter dont_touch = "on"
|
||||
) (
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
module altera_pll_reconfig_top
|
||||
#(
|
||||
parameter reconf_width = 64,
|
||||
parameter device_family = "Stratix V",
|
||||
parameter device_family = "Cyclone V",
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,86 @@
|
|||
// megafunction wizard: %Altera PLL Reconfig v17.0%
|
||||
// GENERATION: XML
|
||||
// pll_cfg.v
|
||||
|
||||
// Generated using ACDS version 17.0 598
|
||||
|
||||
`timescale 1 ps / 1 ps
|
||||
module pll_cfg #(
|
||||
parameter ENABLE_BYTEENABLE = 0,
|
||||
parameter BYTEENABLE_WIDTH = 4,
|
||||
parameter RECONFIG_ADDR_WIDTH = 6,
|
||||
parameter RECONFIG_DATA_WIDTH = 32,
|
||||
parameter reconf_width = 64,
|
||||
parameter WAIT_FOR_LOCK = 1
|
||||
) (
|
||||
input wire mgmt_clk, // mgmt_clk.clk
|
||||
input wire mgmt_reset, // mgmt_reset.reset
|
||||
output wire mgmt_waitrequest, // mgmt_avalon_slave.waitrequest
|
||||
input wire mgmt_read, // .read
|
||||
input wire mgmt_write, // .write
|
||||
output wire [31:0] mgmt_readdata, // .readdata
|
||||
input wire [5:0] mgmt_address, // .address
|
||||
input wire [31:0] mgmt_writedata, // .writedata
|
||||
output wire [63:0] reconfig_to_pll, // reconfig_to_pll.reconfig_to_pll
|
||||
input wire [63:0] reconfig_from_pll // reconfig_from_pll.reconfig_from_pll
|
||||
);
|
||||
|
||||
altera_pll_reconfig_top #(
|
||||
.device_family ("Cyclone V"),
|
||||
.ENABLE_MIF (0),
|
||||
.MIF_FILE_NAME ("sys/pll_cfg.mif"),
|
||||
.ENABLE_BYTEENABLE (ENABLE_BYTEENABLE),
|
||||
.BYTEENABLE_WIDTH (BYTEENABLE_WIDTH),
|
||||
.RECONFIG_ADDR_WIDTH (RECONFIG_ADDR_WIDTH),
|
||||
.RECONFIG_DATA_WIDTH (RECONFIG_DATA_WIDTH),
|
||||
.reconf_width (reconf_width),
|
||||
.WAIT_FOR_LOCK (WAIT_FOR_LOCK)
|
||||
) pll_cfg_inst (
|
||||
.mgmt_clk (mgmt_clk), // mgmt_clk.clk
|
||||
.mgmt_reset (mgmt_reset), // mgmt_reset.reset
|
||||
.mgmt_waitrequest (mgmt_waitrequest), // mgmt_avalon_slave.waitrequest
|
||||
.mgmt_read (mgmt_read), // .read
|
||||
.mgmt_write (mgmt_write), // .write
|
||||
.mgmt_readdata (mgmt_readdata), // .readdata
|
||||
.mgmt_address (mgmt_address), // .address
|
||||
.mgmt_writedata (mgmt_writedata), // .writedata
|
||||
.reconfig_to_pll (reconfig_to_pll), // reconfig_to_pll.reconfig_to_pll
|
||||
.reconfig_from_pll (reconfig_from_pll), // reconfig_from_pll.reconfig_from_pll
|
||||
.mgmt_byteenable (4'b0000) // (terminated)
|
||||
);
|
||||
|
||||
endmodule
|
||||
// Retrieval info: <?xml version="1.0"?>
|
||||
//<!--
|
||||
// Generated by Altera MegaWizard Launcher Utility version 1.0
|
||||
// ************************************************************
|
||||
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
// ************************************************************
|
||||
// Copyright (C) 1991-2018 Altera Corporation
|
||||
// Any megafunction design, and related net list (encrypted or decrypted),
|
||||
// support information, device programming or simulation file, and any other
|
||||
// associated documentation or information provided by Altera or a partner
|
||||
// under Altera's Megafunction Partnership Program may be used only to
|
||||
// program PLD devices (but not masked PLD devices) from Altera. Any other
|
||||
// use of such megafunction design, net list, support information, device
|
||||
// programming or simulation file, or any other related documentation or
|
||||
// information is prohibited for any other purpose, including, but not
|
||||
// limited to modification, reverse engineering, de-compiling, or use with
|
||||
// any other silicon devices, unless such use is explicitly licensed under
|
||||
// a separate agreement with Altera or a megafunction partner. Title to
|
||||
// the intellectual property, including patents, copyrights, trademarks,
|
||||
// trade secrets, or maskworks, embodied in any such megafunction design,
|
||||
// net list, support information, device programming or simulation file, or
|
||||
// any other related documentation or information provided by Altera or a
|
||||
// megafunction partner, remains with Altera, the megafunction partner, or
|
||||
// their respective licensors. No other licenses, including any licenses
|
||||
// needed under any third party's intellectual property, are provided herein.
|
||||
//-->
|
||||
// Retrieval info: <instance entity-name="altera_pll_reconfig" version="17.0" >
|
||||
// Retrieval info: <generic name="device_family" value="Cyclone V" />
|
||||
// Retrieval info: <generic name="ENABLE_MIF" value="false" />
|
||||
// Retrieval info: <generic name="MIF_FILE_NAME" value="sys/pll_cfg.mif" />
|
||||
// Retrieval info: <generic name="ENABLE_BYTEENABLE" value="false" />
|
||||
// Retrieval info: </instance>
|
||||
// IPFS_FILES : pll_cfg.vo
|
||||
// RELATED_FILES: pll_cfg.v, altera_pll_reconfig_top.v, altera_pll_reconfig_core.v, altera_std_synchronizer.v
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,6 +1,4 @@
|
|||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.13.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.13.qip ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_audio.13.qip ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_core.v ]
|
||||
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) pll_cfg/altera_pll_reconfig_top.v ]
|
||||
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]
|
||||
|
|
|
|||
|
|
@ -16,13 +16,6 @@ set_location_assignment PIN_V10 -to ADC_SCK
|
|||
set_location_assignment PIN_AC4 -to ADC_SDI
|
||||
set_location_assignment PIN_AD4 -to ADC_SDO
|
||||
|
||||
#============================================================
|
||||
# ARDUINO
|
||||
#============================================================
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ARDUINO_IO[*]
|
||||
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to ARDUINO_IO[*]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ARDUINO_IO[*]
|
||||
|
||||
#============================================================
|
||||
# I2C LEDS/BUTTONS
|
||||
#============================================================
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@ set_false_path -from [get_ports {KEY*}]
|
|||
set_false_path -from [get_ports {BTN_*}]
|
||||
set_false_path -to [get_ports {LED_*}]
|
||||
set_false_path -to [get_ports {VGA_*}]
|
||||
set_false_path -from [get_ports {VGA_EN}]
|
||||
set_false_path -to [get_ports {AUDIO_SPDIF}]
|
||||
set_false_path -to [get_ports {AUDIO_L}]
|
||||
set_false_path -to [get_ports {AUDIO_R}]
|
||||
|
|
@ -34,6 +35,7 @@ set_false_path -from {cfg[*]}
|
|||
set_false_path -from {VSET[*]}
|
||||
set_false_path -to {wcalc[*] hcalc[*]}
|
||||
set_false_path -to {hdmi_width[*] hdmi_height[*]}
|
||||
set_false_path -to {deb_* btn_en btn_up}
|
||||
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
|
||||
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
|
||||
|
|
@ -70,4 +72,5 @@ set_false_path -from {ascal|o_htotal* ascal|o_vtotal*}
|
|||
set_false_path -from {ascal|o_hsstart* ascal|o_vsstart* ascal|o_hsend* ascal|o_vsend*}
|
||||
set_false_path -from {ascal|o_hsize* ascal|o_vsize*}
|
||||
|
||||
set_false_path -from {mcp23009|sd_cd}
|
||||
set_false_path -from {mcp23009|flg_*}
|
||||
set_false_path -to {sysmem|fpga_interfaces|clocks_resets*}
|
||||
|
|
|
|||
435
sys/sys_top.v
435
sys/sys_top.v
|
|
@ -72,7 +72,7 @@ module sys_top
|
|||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
inout VGA_HS, // VGA_HS is secondary SD card detect when VGA_EN = 1 (inactive)
|
||||
inout VGA_HS,
|
||||
output VGA_VS,
|
||||
input VGA_EN, // active low
|
||||
|
||||
|
|
@ -125,28 +125,23 @@ module sys_top
|
|||
);
|
||||
|
||||
////////////////////// Secondary SD ///////////////////////////////////
|
||||
wire SD_CS, SD_CLK, SD_MOSI;
|
||||
wire SD_CS, SD_CLK, SD_MOSI, SD_MISO, SD_CD;
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire sd_miso = SW[3] | SDIO_DAT[0];
|
||||
`else
|
||||
wire sd_miso = 1;
|
||||
`endif
|
||||
wire SD_MISO = mcp_sdcd ? sd_miso : SD_SPI_MISO;
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
assign SDIO_DAT[2:1]= 2'bZZ;
|
||||
assign SDIO_DAT[3] = SW[3] ? 1'bZ : SD_CS;
|
||||
assign SDIO_CLK = SW[3] ? 1'bZ : SD_CLK;
|
||||
assign SDIO_CMD = SW[3] ? 1'bZ : SD_MOSI;
|
||||
assign SD_SPI_CS = mcp_sdcd ? ((~VGA_EN & sog & ~cs1) ? 1'b1 : 1'bZ) : SD_CS;
|
||||
assign SD_CD = mcp_en ? mcp_sdcd : SDCD_SPDIF;
|
||||
assign SD_MISO = SD_CD | (mcp_en ? SD_SPI_MISO : (VGA_EN | SDIO_DAT[0]));
|
||||
assign SD_SPI_CS = mcp_en ? (mcp_sdcd ? 1'bZ : SD_CS) : (sog & ~cs1 & ~VGA_EN) ? 1'b1 : 1'bZ;
|
||||
assign SD_SPI_CLK = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_CLK;
|
||||
assign SD_SPI_MOSI = (~mcp_en | mcp_sdcd) ? 1'bZ : SD_MOSI;
|
||||
assign {SDIO_CLK,SDIO_CMD,SDIO_DAT} = av_dis ? 6'bZZZZZZ : (mcp_en | (SDCD_SPDIF & ~SW[2])) ? {vga_g,vga_r,vga_b} : {SD_CLK,SD_MOSI,SD_CS,3'bZZZ};
|
||||
`else
|
||||
assign SD_CD = mcp_sdcd;
|
||||
assign SD_MISO = mcp_sdcd | SD_SPI_MISO;
|
||||
assign SD_SPI_CS = mcp_sdcd ? 1'bZ : SD_CS;
|
||||
assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK;
|
||||
assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI;
|
||||
`endif
|
||||
|
||||
assign SD_SPI_CLK = mcp_sdcd ? 1'bZ : SD_CLK;
|
||||
assign SD_SPI_MOSI = mcp_sdcd ? 1'bZ : SD_MOSI;
|
||||
|
||||
////////////////////// LEDs/Buttons ///////////////////////////////////
|
||||
|
||||
reg [7:0] led_overtake = 0;
|
||||
|
|
@ -157,36 +152,58 @@ wire led_d = led_disk[1] ? ~led_disk[0] : ~(led_disk[0] | gp_out[29]);
|
|||
wire led_u = ~led_user;
|
||||
wire led_locked;
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
assign LED_POWER = (SW[3] | led_p) ? 1'bZ : 1'b0;
|
||||
assign LED_HDD = (SW[3] | led_d) ? 1'bZ : 1'b0;
|
||||
assign LED_USER = (SW[3] | led_u) ? 1'bZ : 1'b0;
|
||||
`endif
|
||||
|
||||
//LEDs on main board
|
||||
//LEDs on de10-nano board
|
||||
assign LED = (led_overtake & led_state) | (~led_overtake & {1'b0,led_locked,1'b0, ~led_p, 1'b0, ~led_d, 1'b0, ~led_u});
|
||||
|
||||
wire btn_r, btn_o, btn_u;
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
assign {btn_r,btn_o,btn_u} = SW[3] ? {mcp_btn[1],mcp_btn[2],mcp_btn[0]} : ~{SDRAM2_DQ[9],SDRAM2_DQ[13],SDRAM2_DQ[11]};
|
||||
`else
|
||||
assign {btn_r,btn_o,btn_u} = ~{BTN_RESET,BTN_OSD,BTN_USER} | {mcp_btn[1],mcp_btn[2],mcp_btn[0]};
|
||||
`endif
|
||||
|
||||
wire [2:0] mcp_btn;
|
||||
wire mcp_sdcd;
|
||||
wire mcp_en;
|
||||
wire mcp_mode;
|
||||
mcp23009 mcp23009
|
||||
(
|
||||
.clk(FPGA_CLK2_50),
|
||||
|
||||
.btn(mcp_btn),
|
||||
.led({led_p, led_d, led_u}),
|
||||
.sd_cd(mcp_sdcd),
|
||||
.flg_sd_cd(mcp_sdcd),
|
||||
.flg_present(mcp_en),
|
||||
.flg_mode(mcp_mode),
|
||||
|
||||
.scl(IO_SCL),
|
||||
.sda(IO_SDA)
|
||||
);
|
||||
|
||||
wire io_dig = mcp_en ? mcp_mode : SW[3];
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire av_dis = io_dig | VGA_EN;
|
||||
assign LED_POWER = av_dis ? 1'bZ : mcp_en ? de1 : led_p ? 1'bZ : 1'b0;
|
||||
assign LED_HDD = av_dis ? 1'bZ : mcp_en ? (sog & ~cs1) : led_d ? 1'bZ : 1'b0;
|
||||
assign LED_USER = av_dis ? 1'bZ : mcp_en ? ~vga_tx_clk : led_u ? 1'bZ : 1'b0;
|
||||
wire BTN_DIS = VGA_EN;
|
||||
`else
|
||||
wire BTN_RESET = SDRAM2_DQ[9];
|
||||
wire BTN_OSD = SDRAM2_DQ[13];
|
||||
wire BTN_USER = SDRAM2_DQ[11];
|
||||
wire BTN_DIS = SDRAM2_DQ[15];
|
||||
`endif
|
||||
|
||||
reg BTN_EN = 0;
|
||||
reg [25:0] btn_timeout = 0;
|
||||
initial btn_timeout = 0;
|
||||
always @(posedge FPGA_CLK2_50) begin
|
||||
reg btn_up = 0;
|
||||
reg btn_en = 0;
|
||||
|
||||
btn_up <= BTN_RESET & BTN_OSD & BTN_USER;
|
||||
if(~reset & btn_up & ~&btn_timeout) btn_timeout <= btn_timeout + 1'd1;
|
||||
btn_en <= ~BTN_DIS;
|
||||
BTN_EN <= &btn_timeout & btn_en;
|
||||
end
|
||||
|
||||
wire btn_r = (mcp_en | SW[3]) ? mcp_btn[1] : (BTN_EN & ~BTN_RESET);
|
||||
wire btn_o = (mcp_en | SW[3]) ? mcp_btn[2] : (BTN_EN & ~BTN_OSD );
|
||||
wire btn_u = (mcp_en | SW[3]) ? mcp_btn[0] : (BTN_EN & ~BTN_USER );
|
||||
|
||||
reg btn_user, btn_osd;
|
||||
always @(posedge FPGA_CLK2_50) begin
|
||||
|
|
@ -212,7 +229,7 @@ end
|
|||
|
||||
// gp_in[31] = 0 - quick flag that FPGA is initialized (HPS reads 1 when FPGA is not in user mode)
|
||||
// used to avoid lockups while JTAG loading
|
||||
wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], SW[3], 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys};
|
||||
wire [31:0] gp_in = {1'b0, btn_user | btn[1], btn_osd | btn[0], io_dig, 8'd0, io_ver, io_ack, io_wide, io_dout | io_dout_sys};
|
||||
wire [31:0] gp_out;
|
||||
|
||||
wire [1:0] io_ver = 1; // 0 - obsolete. 1 - optimized HPS I/O. 2,3 - reserved for future.
|
||||
|
|
@ -226,7 +243,7 @@ wire io_ss1 = gp_outr[19];
|
|||
wire io_ss2 = gp_outr[20];
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire io_osd_hdmi = io_ss1 & ~io_ss0;
|
||||
wire io_osd_hdmi = io_ss1 & ~io_ss0;
|
||||
`endif
|
||||
|
||||
wire io_fpga = ~io_ss1 & io_ss0;
|
||||
|
|
@ -267,14 +284,14 @@ cyclonev_hps_interface_mpu_general_purpose h2f_gp
|
|||
|
||||
|
||||
reg [15:0] cfg;
|
||||
|
||||
reg cfg_set = 0;
|
||||
wire vga_fb = cfg[12] | vga_force_scaler;
|
||||
|
||||
`ifdef MISTER_DEBUG_NOHDMI
|
||||
wire direct_video = 1;
|
||||
wire vga_fb = 0;
|
||||
wire direct_video = 1;
|
||||
`else
|
||||
wire direct_video = cfg[10];
|
||||
wire vga_fb = cfg[12] | vga_force_scaler;
|
||||
wire direct_video = cfg[10];
|
||||
`endif
|
||||
|
||||
wire audio_96k = cfg[6];
|
||||
|
|
@ -283,7 +300,11 @@ wire io_osd_vga = io_ss1 & ~io_ss2;
|
|||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire ypbpr_en = cfg[5];
|
||||
wire sog = cfg[9];
|
||||
`ifdef MISTER_DEBUG_NOHDMI
|
||||
wire vga_scaler = 0;
|
||||
`else
|
||||
wire vga_scaler = cfg[2] | vga_force_scaler;
|
||||
`endif
|
||||
`endif
|
||||
|
||||
reg cfg_custom_t = 0;
|
||||
|
|
@ -657,35 +678,35 @@ wire hdmi_vs, hdmi_hs, hdmi_de, hdmi_vbl, hdmi_brd;
|
|||
wire freeze;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire clk_hdmi = hdmi_clk_out;
|
||||
wire clk_hdmi = hdmi_clk_out;
|
||||
|
||||
ascal
|
||||
#(
|
||||
ascal
|
||||
#(
|
||||
.RAMBASE(32'h20000000),
|
||||
`ifdef MISTER_SMALL_VBUF
|
||||
`ifdef MISTER_SMALL_VBUF
|
||||
.RAMSIZE(32'h00200000),
|
||||
`else
|
||||
`else
|
||||
.RAMSIZE(32'h00800000),
|
||||
`endif
|
||||
`ifndef MISTER_FB
|
||||
`endif
|
||||
`ifndef MISTER_FB
|
||||
.PALETTE2("false"),
|
||||
`else
|
||||
`else
|
||||
`ifndef MISTER_FB_PALETTE
|
||||
.PALETTE2("false"),
|
||||
`endif
|
||||
`endif
|
||||
`ifdef MISTER_DISABLE_ADAPTIVE
|
||||
`endif
|
||||
`ifdef MISTER_DISABLE_ADAPTIVE
|
||||
.ADAPTIVE("false"),
|
||||
`endif
|
||||
`ifdef MISTER_DOWNSCALE_NN
|
||||
`endif
|
||||
`ifdef MISTER_DOWNSCALE_NN
|
||||
.DOWNSCALE_NN("true"),
|
||||
`endif
|
||||
`endif
|
||||
.FRAC(8),
|
||||
.N_DW(128),
|
||||
.N_AW(28)
|
||||
)
|
||||
ascal
|
||||
(
|
||||
)
|
||||
ascal
|
||||
(
|
||||
.reset_na (~reset_req),
|
||||
.run (1),
|
||||
.freeze (freeze),
|
||||
|
|
@ -742,7 +763,7 @@ ascal
|
|||
.pal1_a (pal_a),
|
||||
.pal1_wr (pal_wr),
|
||||
|
||||
`ifdef MISTER_FB
|
||||
`ifdef MISTER_FB
|
||||
`ifdef MISTER_FB_PALETTE
|
||||
.pal2_clk (fb_pal_clk),
|
||||
.pal2_dw (fb_pal_d),
|
||||
|
|
@ -751,7 +772,7 @@ ascal
|
|||
.pal2_wr (fb_pal_wr),
|
||||
.pal_n (fb_en),
|
||||
`endif
|
||||
`endif
|
||||
`endif
|
||||
|
||||
.o_fb_ena (FB_EN),
|
||||
.o_fb_hsize (FB_WIDTH),
|
||||
|
|
@ -770,7 +791,7 @@ ascal
|
|||
.avl_write (vbuf_write),
|
||||
.avl_read (vbuf_read),
|
||||
.avl_byteenable (vbuf_byteenable)
|
||||
);
|
||||
);
|
||||
`endif
|
||||
|
||||
reg LFB_EN = 0;
|
||||
|
|
@ -811,8 +832,8 @@ always @(posedge clk_sys) begin
|
|||
end
|
||||
|
||||
`ifdef MISTER_FB
|
||||
reg fb_vbl;
|
||||
always @(posedge clk_vid) fb_vbl <= hdmi_vbl;
|
||||
reg fb_vbl;
|
||||
always @(posedge clk_vid) fb_vbl <= hdmi_vbl;
|
||||
`endif
|
||||
|
||||
reg ar_md_start;
|
||||
|
|
@ -938,9 +959,9 @@ always @(posedge clk_vid) begin
|
|||
end
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire [15:0] lltune;
|
||||
pll_hdmi_adj pll_hdmi_adj
|
||||
(
|
||||
wire [15:0] lltune;
|
||||
pll_hdmi_adj pll_hdmi_adj
|
||||
(
|
||||
.clk(FPGA_CLK1_50),
|
||||
.reset_na(~reset_req),
|
||||
|
||||
|
|
@ -955,7 +976,7 @@ pll_hdmi_adj pll_hdmi_adj
|
|||
.o_write(cfg_write),
|
||||
.o_address(cfg_address),
|
||||
.o_writedata(cfg_data)
|
||||
);
|
||||
);
|
||||
`else
|
||||
assign led_locked = 0;
|
||||
`endif
|
||||
|
|
@ -981,15 +1002,15 @@ end
|
|||
|
||||
///////////////////////// HDMI output /////////////////////////////////
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
wire hdmi_clk_out;
|
||||
pll_hdmi pll_hdmi
|
||||
(
|
||||
wire hdmi_clk_out;
|
||||
pll_hdmi pll_hdmi
|
||||
(
|
||||
.refclk(FPGA_CLK1_50),
|
||||
.rst(reset_req),
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll),
|
||||
.outclk_0(hdmi_clk_out)
|
||||
);
|
||||
);
|
||||
`endif
|
||||
|
||||
//1920x1080@60 PCLK=148.5MHz CEA
|
||||
|
|
@ -1014,22 +1035,20 @@ reg [5:0] adj_address;
|
|||
reg [31:0] adj_data;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
pll_cfg pll_cfg
|
||||
(
|
||||
pll_cfg_hdmi pll_cfg_hdmi
|
||||
(
|
||||
.mgmt_clk(FPGA_CLK1_50),
|
||||
.mgmt_reset(reset_req),
|
||||
.mgmt_waitrequest(cfg_waitrequest),
|
||||
.mgmt_read(0),
|
||||
.mgmt_readdata(),
|
||||
.mgmt_write(cfg_write),
|
||||
.mgmt_address(cfg_address),
|
||||
.mgmt_writedata(cfg_data),
|
||||
.reconfig_to_pll(reconfig_to_pll),
|
||||
.reconfig_from_pll(reconfig_from_pll)
|
||||
);
|
||||
);
|
||||
|
||||
reg cfg_got = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg cfg_got = 0;
|
||||
always @(posedge clk_sys) begin
|
||||
reg vsd, vsd2;
|
||||
if(~cfg_ready || ~cfg_set) cfg_got <= cfg_set;
|
||||
else begin
|
||||
|
|
@ -1037,10 +1056,10 @@ always @(posedge clk_sys) begin
|
|||
vsd2 <= vsd;
|
||||
if(~vsd2 & vsd) cfg_got <= cfg_set;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
reg cfg_ready = 0;
|
||||
always @(posedge FPGA_CLK1_50) begin
|
||||
reg cfg_ready = 0;
|
||||
always @(posedge FPGA_CLK1_50) begin
|
||||
reg gotd = 0, gotd2 = 0;
|
||||
reg custd = 0, custd2 = 0;
|
||||
reg old_wait = 0;
|
||||
|
|
@ -1066,12 +1085,9 @@ always @(posedge FPGA_CLK1_50) begin
|
|||
|
||||
old_wait <= adj_waitrequest;
|
||||
if(old_wait & ~adj_waitrequest & gotd) cfg_ready <= 1;
|
||||
end
|
||||
|
||||
end
|
||||
`else
|
||||
|
||||
wire cfg_ready = 1;
|
||||
|
||||
wire cfg_ready = 1;
|
||||
`endif
|
||||
|
||||
assign HDMI_I2C_SCL = hdmi_scl_en ? 1'b0 : 1'bZ;
|
||||
|
|
@ -1087,26 +1103,25 @@ cyclonev_hps_interface_peripheral_i2c hdmi_i2c
|
|||
);
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
|
||||
`ifdef MISTER_FB
|
||||
reg dis_output;
|
||||
always @(posedge clk_hdmi) begin
|
||||
`ifdef MISTER_FB
|
||||
reg dis_output;
|
||||
always @(posedge clk_hdmi) begin
|
||||
reg dis;
|
||||
dis <= fb_force_blank & ~LFB_EN;
|
||||
dis_output <= dis;
|
||||
end
|
||||
`else
|
||||
wire dis_output = 0;
|
||||
`endif
|
||||
end
|
||||
`else
|
||||
wire dis_output = 0;
|
||||
`endif
|
||||
|
||||
wire [23:0] hdmi_data_mask;
|
||||
wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;
|
||||
wire [23:0] hdmi_data_mask;
|
||||
wire hdmi_de_mask, hdmi_vs_mask, hdmi_hs_mask;
|
||||
|
||||
reg [15:0] shadowmask_data;
|
||||
reg shadowmask_wr = 0;
|
||||
reg [15:0] shadowmask_data;
|
||||
reg shadowmask_wr = 0;
|
||||
|
||||
shadowmask HDMI_shadowmask
|
||||
(
|
||||
shadowmask HDMI_shadowmask
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
|
|
@ -1124,13 +1139,13 @@ shadowmask HDMI_shadowmask
|
|||
.hs_out(hdmi_hs_mask),
|
||||
.vs_out(hdmi_vs_mask),
|
||||
.de_out(hdmi_de_mask)
|
||||
);
|
||||
);
|
||||
|
||||
wire [23:0] hdmi_data_osd;
|
||||
wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd;
|
||||
wire [23:0] hdmi_data_osd;
|
||||
wire hdmi_de_osd, hdmi_vs_osd, hdmi_hs_osd;
|
||||
|
||||
osd hdmi_osd
|
||||
(
|
||||
osd hdmi_osd
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
|
||||
.io_osd(io_osd_hdmi),
|
||||
|
|
@ -1147,11 +1162,11 @@ osd hdmi_osd
|
|||
.hs_out(hdmi_hs_osd),
|
||||
.vs_out(hdmi_vs_osd),
|
||||
.de_out(hdmi_de_osd)
|
||||
);
|
||||
`endif
|
||||
);
|
||||
|
||||
wire hdmi_cs_osd;
|
||||
csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
|
||||
wire hdmi_cs_osd;
|
||||
csync csync_hdmi(clk_hdmi, hdmi_hs_osd, hdmi_vs_osd, hdmi_cs_osd);
|
||||
`endif
|
||||
|
||||
reg [23:0] dv_data;
|
||||
reg dv_hs, dv_vs, dv_de;
|
||||
|
|
@ -1185,11 +1200,12 @@ always @(posedge clk_vid) begin
|
|||
end
|
||||
|
||||
dv_de1 <= !{hss,dv_hs_osd} && vde;
|
||||
dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd;
|
||||
dv_vs1 <= dv_vs_osd;
|
||||
end
|
||||
|
||||
dv_d1 <= dv_data_osd;
|
||||
dv_hs1 <= csync_en ? dv_cs_osd : dv_hs_osd;
|
||||
dv_vs1 <= dv_vs_osd;
|
||||
|
||||
dv_d2 <= dv_d1;
|
||||
dv_de2 <= dv_de1;
|
||||
dv_hs2 <= dv_hs1;
|
||||
|
|
@ -1202,21 +1218,21 @@ always @(posedge clk_vid) begin
|
|||
end
|
||||
|
||||
`ifndef MISTER_DISABLE_YC
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs };
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = ~yc_en ? {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd } : {yc_o, yc_hs, yc_vs, yc_cs };
|
||||
`else
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd };
|
||||
assign {dv_data_osd, dv_hs_osd, dv_vs_osd, dv_cs_osd } = {vga_data_osd, vga_hs_osd, vga_vs_osd, vga_cs_osd };
|
||||
`endif
|
||||
|
||||
wire hdmi_tx_clk;
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
cyclonev_clkselect hdmi_clk_sw
|
||||
(
|
||||
cyclonev_clkselect hdmi_clk_sw
|
||||
(
|
||||
.clkselect({1'b1, ~vga_fb & direct_video}),
|
||||
.inclk({clk_vid, hdmi_clk_out, 2'b00}),
|
||||
.outclk(hdmi_tx_clk)
|
||||
);
|
||||
);
|
||||
`else
|
||||
assign hdmi_tx_clk = clk_vid;
|
||||
assign hdmi_tx_clk = clk_vid;
|
||||
`endif
|
||||
|
||||
altddio_out
|
||||
|
|
@ -1261,10 +1277,17 @@ always @(posedge hdmi_tx_clk) begin
|
|||
hdmi_dv_vs <= dv_vs;
|
||||
hdmi_dv_de <= dv_de;
|
||||
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
hs <= (~vga_fb & direct_video) ? hdmi_dv_hs : (direct_video & csync_en) ? hdmi_cs_osd : hdmi_hs_osd;
|
||||
vs <= (~vga_fb & direct_video) ? hdmi_dv_vs : hdmi_vs_osd;
|
||||
de <= (~vga_fb & direct_video) ? hdmi_dv_de : hdmi_de_osd;
|
||||
d <= (~vga_fb & direct_video) ? hdmi_dv_data : hdmi_data_osd;
|
||||
`else
|
||||
hs <= hdmi_dv_hs;
|
||||
vs <= hdmi_dv_vs;
|
||||
de <= hdmi_dv_de;
|
||||
d <= hdmi_dv_data;
|
||||
`endif
|
||||
|
||||
hdmi_out_hs <= hs;
|
||||
hdmi_out_vs <= vs;
|
||||
|
|
@ -1279,6 +1302,20 @@ assign HDMI_TX_D = hdmi_out_d;
|
|||
|
||||
///////////////////////// VGA output //////////////////////////////////
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire vga_tx_clk;
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
cyclonev_clkselect vga_clk_sw
|
||||
(
|
||||
.clkselect({1'b1, ~vga_fb & ~vga_scaler}),
|
||||
.inclk({clk_vid, hdmi_clk_out, 2'b00}),
|
||||
.outclk(vga_tx_clk)
|
||||
);
|
||||
`else
|
||||
assign vga_tx_clk = clk_vid;
|
||||
`endif
|
||||
`endif
|
||||
|
||||
wire [23:0] vga_data_sl;
|
||||
wire vga_de_sl, vga_ce_sl, vga_vs_sl, vga_hs_sl;
|
||||
scanlines #(0) VGA_scanlines
|
||||
|
|
@ -1300,7 +1337,7 @@ scanlines #(0) VGA_scanlines
|
|||
);
|
||||
|
||||
wire [23:0] vga_data_osd;
|
||||
wire vga_vs_osd, vga_hs_osd;
|
||||
wire vga_vs_osd, vga_hs_osd, vga_de_osd;
|
||||
osd vga_osd
|
||||
(
|
||||
.clk_sys(clk_sys),
|
||||
|
|
@ -1318,46 +1355,13 @@ osd vga_osd
|
|||
|
||||
.dout(vga_data_osd),
|
||||
.hs_out(vga_hs_osd),
|
||||
.vs_out(vga_vs_osd)
|
||||
.vs_out(vga_vs_osd),
|
||||
.de_out(vga_de_osd)
|
||||
);
|
||||
|
||||
wire vga_cs_osd;
|
||||
csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire VGA_DISABLE;
|
||||
wire [23:0] vgas_o;
|
||||
wire vgas_hs, vgas_vs, vgas_cs;
|
||||
vga_out vga_scaler_out
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(hdmi_hs_osd),
|
||||
.vsync(hdmi_vs_osd),
|
||||
.csync(hdmi_cs_osd),
|
||||
.dout(vgas_o),
|
||||
.din({24{hdmi_de_osd}} & hdmi_data_osd),
|
||||
.hsync_o(vgas_hs),
|
||||
.vsync_o(vgas_vs),
|
||||
.csync_o(vgas_cs)
|
||||
);
|
||||
|
||||
wire [23:0] vga_o, vga_o_t;
|
||||
wire vga_hs, vga_vs, vga_cs, vga_hs_t, vga_vs_t, vga_cs_t;
|
||||
vga_out vga_out
|
||||
(
|
||||
.clk(clk_vid),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(vga_hs_osd),
|
||||
.vsync(vga_vs_osd),
|
||||
.csync(vga_cs_osd),
|
||||
.dout(vga_o_t),
|
||||
.din(vga_data_osd),
|
||||
.hsync_o(vga_hs_t),
|
||||
.vsync_o(vga_vs_t),
|
||||
.csync_o(vga_cs_t)
|
||||
);
|
||||
|
||||
`ifndef MISTER_DISABLE_YC
|
||||
reg pal_en;
|
||||
reg yc_en;
|
||||
|
|
@ -1365,7 +1369,7 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
|||
reg [16:0] ColorBurst_Range;
|
||||
reg [39:0] PhaseInc;
|
||||
wire [23:0] yc_o;
|
||||
wire yc_hs, yc_vs, yc_cs;
|
||||
wire yc_hs, yc_vs, yc_cs, yc_de;
|
||||
|
||||
yc_out yc_out
|
||||
(
|
||||
|
|
@ -1377,25 +1381,78 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
|
|||
.hsync(vga_hs_osd),
|
||||
.vsync(vga_vs_osd),
|
||||
.csync(vga_cs_osd),
|
||||
.de(vga_de_osd),
|
||||
.dout(yc_o),
|
||||
.din(vga_data_osd),
|
||||
.hsync_o(yc_hs),
|
||||
.vsync_o(yc_vs),
|
||||
.csync_o(yc_cs)
|
||||
.csync_o(yc_cs),
|
||||
.de_o(yc_de)
|
||||
);
|
||||
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } : {yc_o, yc_hs, yc_vs, yc_cs };
|
||||
`else
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t } ;
|
||||
`endif
|
||||
|
||||
wire cs1 = (vga_fb | vga_scaler) ? vgas_cs : vga_cs;
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire VGA_DISABLE;
|
||||
wire [23:0] vgas_o;
|
||||
wire vgas_hs, vgas_vs, vgas_cs, vgas_de;
|
||||
`ifndef MISTER_DEBUG_NOHDMI
|
||||
vga_out vga_scaler_out
|
||||
(
|
||||
.clk(clk_hdmi),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(hdmi_hs_osd),
|
||||
.vsync(hdmi_vs_osd),
|
||||
.csync(hdmi_cs_osd),
|
||||
.de(hdmi_de_osd),
|
||||
.dout(vgas_o),
|
||||
.din({24{hdmi_de_osd}} & hdmi_data_osd),
|
||||
.hsync_o(vgas_hs),
|
||||
.vsync_o(vgas_vs),
|
||||
.csync_o(vgas_cs),
|
||||
.de_o(vgas_de)
|
||||
);
|
||||
`else
|
||||
assign {vgas_o, vgas_hs, vgas_vs, vgas_cs, vgas_de} = 0;
|
||||
`endif
|
||||
|
||||
assign VGA_VS = (VGA_EN | SW[3]) ? 1'bZ : (((vga_fb | vga_scaler) ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en);
|
||||
assign VGA_HS = (VGA_EN | SW[3]) ? 1'bZ : ((vga_fb | vga_scaler) ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs));
|
||||
assign VGA_R = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18];
|
||||
assign VGA_G = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10];
|
||||
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : (vga_fb | vga_scaler) ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ;
|
||||
wire [23:0] vga_o, vga_o_t;
|
||||
wire vga_hs, vga_vs, vga_cs, vga_de, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t;
|
||||
vga_out vga_out
|
||||
(
|
||||
.clk(clk_vid),
|
||||
.ypbpr_en(ypbpr_en),
|
||||
.hsync(vga_hs_osd),
|
||||
.vsync(vga_vs_osd),
|
||||
.csync(vga_cs_osd),
|
||||
.de(vga_de_osd),
|
||||
.dout(vga_o_t),
|
||||
.din(vga_data_osd),
|
||||
.hsync_o(vga_hs_t),
|
||||
.vsync_o(vga_vs_t),
|
||||
.csync_o(vga_cs_t),
|
||||
.de_o(vga_de_t)
|
||||
);
|
||||
|
||||
`ifndef MISTER_DISABLE_YC
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = ~yc_en ? {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } : {yc_o, yc_hs, yc_vs, yc_cs, yc_de };
|
||||
`else
|
||||
assign {vga_o, vga_hs, vga_vs, vga_cs, vga_de } = {vga_o_t, vga_hs_t, vga_vs_t, vga_cs_t, vga_de_t } ;
|
||||
`endif
|
||||
|
||||
wire vgas_en = vga_fb | vga_scaler;
|
||||
|
||||
wire cs1 = vgas_en ? vgas_cs : vga_cs;
|
||||
wire de1 = vgas_en ? vgas_de : vga_de;
|
||||
|
||||
assign VGA_VS = av_dis ? 1'bZ : ((vgas_en ? (~vgas_vs ^ VS[12]) : VGA_DISABLE ? 1'd1 : ~vga_vs) | csync_en);
|
||||
assign VGA_HS = av_dis ? 1'bZ : (vgas_en ? ((csync_en ? ~vgas_cs : ~vgas_hs) ^ HS[12]) : VGA_DISABLE ? 1'd1 : (csync_en ? ~vga_cs : ~vga_hs));
|
||||
assign VGA_R = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[23:18] : VGA_DISABLE ? 6'd0 : vga_o[23:18];
|
||||
assign VGA_G = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[15:10] : VGA_DISABLE ? 6'd0 : vga_o[15:10];
|
||||
assign VGA_B = av_dis ? 6'bZZZZZZ : vgas_en ? vgas_o[7:2] : VGA_DISABLE ? 6'd0 : vga_o[7:2] ;
|
||||
|
||||
wire [1:0] vga_r = vgas_en ? vgas_o[17:16] : VGA_DISABLE ? 2'd0 : vga_o[17:16];
|
||||
wire [1:0] vga_g = vgas_en ? vgas_o[9:8] : VGA_DISABLE ? 2'd0 : vga_o[9:8];
|
||||
wire [1:0] vga_b = vgas_en ? vgas_o[1:0] : VGA_DISABLE ? 2'd0 : vga_o[1:0];
|
||||
`endif
|
||||
|
||||
reg video_sync = 0;
|
||||
|
|
@ -1425,14 +1482,14 @@ end
|
|||
|
||||
///////////////////////// Audio output ////////////////////////////////
|
||||
|
||||
assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;
|
||||
assign SDCD_SPDIF = (mcp_en & ~spdif) ? 1'b0 : 1'bZ;
|
||||
|
||||
`ifndef MISTER_DUAL_SDRAM
|
||||
wire analog_l, analog_r;
|
||||
|
||||
assign AUDIO_SPDIF = SW[3] ? 1'bZ : SW[0] ? HDMI_LRCLK : spdif;
|
||||
assign AUDIO_R = SW[3] ? 1'bZ : SW[0] ? HDMI_I2S : analog_r;
|
||||
assign AUDIO_L = SW[3] ? 1'bZ : SW[0] ? HDMI_SCLK : analog_l;
|
||||
assign AUDIO_SPDIF = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_LRCLK : spdif;
|
||||
assign AUDIO_R = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_I2S : analog_r;
|
||||
assign AUDIO_L = av_dis ? 1'bZ : (SW[0] | mcp_en) ? HDMI_SCLK : analog_l;
|
||||
`endif
|
||||
|
||||
assign HDMI_MCLK = clk_audio;
|
||||
|
|
@ -1485,27 +1542,27 @@ audio_out audio_out
|
|||
|
||||
|
||||
`ifndef MISTER_DISABLE_ALSA
|
||||
wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
|
||||
cyclonev_hps_interface_peripheral_spi_master spi
|
||||
(
|
||||
wire aspi_sck,aspi_mosi,aspi_ss,aspi_miso;
|
||||
cyclonev_hps_interface_peripheral_spi_master spi
|
||||
(
|
||||
.sclk_out(aspi_sck),
|
||||
.txd(aspi_mosi), // mosi
|
||||
.rxd(aspi_miso), // miso
|
||||
|
||||
.ss_0_n(aspi_ss),
|
||||
.ss_in_n(1)
|
||||
);
|
||||
);
|
||||
|
||||
wire [28:0] alsa_address;
|
||||
wire [63:0] alsa_readdata;
|
||||
wire alsa_ready;
|
||||
wire alsa_req;
|
||||
wire alsa_late;
|
||||
wire [28:0] alsa_address;
|
||||
wire [63:0] alsa_readdata;
|
||||
wire alsa_ready;
|
||||
wire alsa_req;
|
||||
wire alsa_late;
|
||||
|
||||
wire [15:0] alsa_l, alsa_r;
|
||||
wire [15:0] alsa_l, alsa_r;
|
||||
|
||||
alsa alsa
|
||||
(
|
||||
alsa alsa
|
||||
(
|
||||
.reset(reset),
|
||||
.clk(clk_audio),
|
||||
|
||||
|
|
@ -1521,7 +1578,7 @@ alsa alsa
|
|||
|
||||
.pcm_l(alsa_l),
|
||||
.pcm_r(alsa_r)
|
||||
);
|
||||
);
|
||||
`endif
|
||||
|
||||
//////////////// User I/O (USB 3.0 connector) /////////////////////////
|
||||
|
|
@ -1722,7 +1779,7 @@ emu emu
|
|||
.SDRAM2_nRAS(SDRAM2_nRAS),
|
||||
.SDRAM2_nCAS(SDRAM2_nCAS),
|
||||
.SDRAM2_CLK(SDRAM2_CLK),
|
||||
.SDRAM2_EN(SW[3]),
|
||||
.SDRAM2_EN(io_dig),
|
||||
`endif
|
||||
|
||||
.BUTTONS(btn),
|
||||
|
|
@ -1732,11 +1789,7 @@ emu emu
|
|||
.SD_MOSI(SD_MOSI),
|
||||
.SD_MISO(SD_MISO),
|
||||
.SD_CS(SD_CS),
|
||||
`ifdef MISTER_DUAL_SDRAM
|
||||
.SD_CD(mcp_sdcd),
|
||||
`else
|
||||
.SD_CD(mcp_sdcd & (SW[0] ? VGA_HS : (SW[3] | SDCD_SPDIF))),
|
||||
`endif
|
||||
.SD_CD(SD_CD),
|
||||
|
||||
.UART_CTS(uart_rts),
|
||||
.UART_RTS(uart_cts),
|
||||
|
|
@ -1765,19 +1818,17 @@ assign sync_out = sync_in ^ pol;
|
|||
|
||||
reg pol;
|
||||
always @(posedge clk) begin
|
||||
integer pos = 0, neg = 0, cnt = 0;
|
||||
reg [31:0] cnt;
|
||||
reg s1,s2;
|
||||
|
||||
s1 <= sync_in;
|
||||
s2 <= s1;
|
||||
cnt <= s2 ? (cnt - 1) : (cnt + 1);
|
||||
|
||||
if(~s2 & s1) neg <= cnt;
|
||||
if(s2 & ~s1) pos <= cnt;
|
||||
|
||||
cnt <= cnt + 1;
|
||||
if(s2 != s1) cnt <= 0;
|
||||
|
||||
pol <= pos > neg;
|
||||
if(~s2 & s1) begin
|
||||
cnt <= 0;
|
||||
pol <= cnt[31];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -7,23 +7,27 @@ module vga_out
|
|||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
input de,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
output reg csync_o,
|
||||
output reg de_o
|
||||
);
|
||||
|
||||
wire [5:0] red = din[23:18];
|
||||
wire [5:0] green = din[15:10];
|
||||
wire [5:0] blue = din[7:2];
|
||||
wire [7:0] red = din[23:16];
|
||||
wire [7:0] green = din[15:8];
|
||||
wire [7:0] blue = din[7:0];
|
||||
|
||||
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
|
||||
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
|
||||
// Y = 0.301*R + 0.586*G + 0.113*B (Y = 0.299*R + 0.587*G + 0.114*B)
|
||||
// Pb = 128 - 0.168*R - 0.332*G + 0.500*B (Pb = -0.169*R - 0.331*G + 0.500*B)
|
||||
// Pr = 128 + 0.500*R - 0.418*G - 0.082*B (Pr = 0.500*R - 0.419*G - 0.081*B)
|
||||
|
||||
reg [7:0] y, pb, pr;
|
||||
reg [23:0] rgb;
|
||||
|
|
@ -33,32 +37,33 @@ always @(posedge clk) begin
|
|||
reg [18:0] y_1b, pb_1b, pr_1b;
|
||||
reg [18:0] y_2, pb_2, pr_2;
|
||||
reg [23:0] din1, din2;
|
||||
reg hsync2, vsync2, csync2;
|
||||
reg hsync1, vsync1, csync1;
|
||||
reg hsync2, vsync2, csync2, de2;
|
||||
reg hsync1, vsync1, csync1, de1;
|
||||
|
||||
y_1r <= 19'd04096 + ({red, 8'd0} + {red, 3'd0});
|
||||
pb_1r <= 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0});
|
||||
pr_1r <= 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0});
|
||||
y_1r <= {red, 6'd0} + {red, 3'd0} + {red, 2'd0} + red;
|
||||
pb_1r <= 19'd32768 - ({red, 5'd0} + {red, 3'd0} + {red, 1'd0});
|
||||
pr_1r <= 19'd32768 + {red, 7'd0};
|
||||
|
||||
y_1g <= {green, 9'd0} + {green, 2'd0};
|
||||
pb_1g <= {green, 8'd0} + {green, 5'd0} + {green, 3'd0};
|
||||
pr_1g <= {green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0};
|
||||
y_1g <= {green, 7'd0} + {green, 4'd0} + {green, 2'd0} + {green, 1'd0};
|
||||
pb_1g <= {green, 6'd0} + {green, 4'd0} + {green, 2'd0} + green;
|
||||
pr_1g <= {green, 6'd0} + {green, 5'd0} + {green, 3'd0} + {green, 1'd0};
|
||||
|
||||
y_1b <= {blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0};
|
||||
pb_1b <= {blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0};
|
||||
pr_1b <= {blue, 6'd0} + {blue, 3'd0};
|
||||
y_1b <= {blue, 4'd0} + {blue, 3'd0} + {blue, 2'd0} + blue;
|
||||
pb_1b <= {blue, 7'd0};
|
||||
pr_1b <= {blue, 4'd0} + {blue, 2'd0} + blue;
|
||||
|
||||
y_2 <= y_1r + y_1g + y_1b;
|
||||
pb_2 <= pb_1r - pb_1g + pb_1b;
|
||||
pr_2 <= pr_1r - pr_1g - pr_1b;
|
||||
|
||||
y <= ( y_2[18] || !y_2[17:12]) ? 8'd16 : (y_2[17:8] > 235) ? 8'd235 : y_2[15:8];
|
||||
pb <= (pb_2[18] || !pb_2[17:12]) ? 8'd16 : (&pb_2[17:12]) ? 8'd240 : pb_2[15:8];
|
||||
pr <= (pr_2[18] || !pr_2[17:12]) ? 8'd16 : (&pr_2[17:12]) ? 8'd240 : pr_2[15:8];
|
||||
y <= y_2[18] ? 8'd0 : y_2[16] ? 8'd255 : y_2[15:8];
|
||||
pb <= pb_2[18] ? 8'd0 : pb_2[16] ? 8'd255 : pb_2[15:8];
|
||||
pr <= pr_2[18] ? 8'd0 : pr_2[16] ? 8'd255 : pr_2[15:8];
|
||||
|
||||
hsync_o <= hsync2; hsync2 <= hsync1; hsync1 <= hsync;
|
||||
vsync_o <= vsync2; vsync2 <= vsync1; vsync1 <= vsync;
|
||||
csync_o <= csync2; csync2 <= csync1; csync1 <= csync;
|
||||
de_o <= de2; de2 <= de1; de1 <= de;
|
||||
|
||||
rgb <= din2; din2 <= din1; din1 <= din;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -170,10 +170,8 @@ reg [11:0] mul_arg1, mul_arg2;
|
|||
wire [23:0] mul_res;
|
||||
sys_umul #(12,12) mul(CLK_VIDEO,mul_start,mul_run, mul_arg1,mul_arg2,mul_res);
|
||||
|
||||
wire [11:0] wideres = mul_res[11:0] + hsize;
|
||||
|
||||
always @(posedge CLK_VIDEO) begin
|
||||
reg [11:0] oheight,wres;
|
||||
reg [11:0] oheight,htarget,wres,hinteger,wideres;
|
||||
reg [12:0] arxf,aryf;
|
||||
reg [3:0] cnt;
|
||||
reg narrow;
|
||||
|
|
@ -188,11 +186,18 @@ always @(posedge CLK_VIDEO) begin
|
|||
else if(~div_start & ~div_run & ~mul_start & ~mul_run) begin
|
||||
cnt <= cnt + 1'd1;
|
||||
case(cnt)
|
||||
// example ideal and non-ideal cases:
|
||||
// [1] 720x400 4:3 VGA 80x25 text-mode (non-square pixels)
|
||||
// [2] 640x480 4:3 VGA graphics mode (square pixels)
|
||||
// [3] 512x512 4:3 X68000 graphics mode (non-square pixels)
|
||||
0: begin
|
||||
div_num <= HDMI_HEIGHT;
|
||||
div_den <= vsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 -> 2
|
||||
// [2] 1080 / 480 -> 2
|
||||
// [3] 1080 / 512 -> 2
|
||||
|
||||
1: if(!div_res[11:0]) begin
|
||||
// screen resolution is lower than video resolution.
|
||||
|
|
@ -206,6 +211,9 @@ always @(posedge CLK_VIDEO) begin
|
|||
mul_arg2 <= div_res[11:0];
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 * 400 -> 800
|
||||
// [2] 1080 / 480 * 480 -> 960
|
||||
// [3] 1080 / 512 * 512 -> 1024
|
||||
|
||||
2: begin
|
||||
oheight <= mul_res[11:0];
|
||||
|
|
@ -219,27 +227,43 @@ always @(posedge CLK_VIDEO) begin
|
|||
mul_arg2 <= arx_i;
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 * 400 * 4 -> 3200
|
||||
// [2] 1080 / 480 * 480 * 4 -> 3840
|
||||
// [3] 1080 / 512 * 512 * 4 -> 4096
|
||||
|
||||
4: begin
|
||||
div_num <= mul_res;
|
||||
div_den <= ary_i;
|
||||
div_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 480 * 480 * 4 / 3 -> 1066
|
||||
// [2] 1080 / 480 * 480 * 4 / 3 -> 1280
|
||||
// [3] 1080 / 512 * 512 * 4 / 3 -> 1365
|
||||
// saved as htarget
|
||||
|
||||
5: begin
|
||||
htarget <= div_res[11:0];
|
||||
div_num <= div_res;
|
||||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
// computes wide scaling factor as a ceiling division
|
||||
// [1] 1080 / 400 * 400 * 4 / 3 / 720 -> 1
|
||||
// [2] 1080 / 480 * 480 * 4 / 3 / 640 -> 2
|
||||
// [3] 1080 / 512 * 512 * 4 / 3 / 512 -> 2
|
||||
|
||||
6: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1080 / 400 * 400 * 4 / 3 / 720 * 720 -> 720
|
||||
// [2] 1080 / 480 * 480 * 4 / 3 / 640 * 640 -> 1280
|
||||
// [3] 1080 / 512 * 512 * 4 / 3 / 512 * 512 -> 1024
|
||||
|
||||
7: if(mul_res <= HDMI_WIDTH) begin
|
||||
cnt <= 10;
|
||||
hinteger = mul_res[11:0];
|
||||
cnt <= 12;
|
||||
end
|
||||
|
||||
8: begin
|
||||
|
|
@ -247,23 +271,50 @@ always @(posedge CLK_VIDEO) begin
|
|||
div_den <= hsize;
|
||||
div_start <= 1;
|
||||
end
|
||||
// [1] 1920 / 720 -> 2
|
||||
// [2] 1920 / 640 -> 3
|
||||
// [3] 1920 / 512 -> 3
|
||||
|
||||
9: begin
|
||||
mul_arg1 <= hsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
// [1] 1920 / 720 * 720 -> 1440
|
||||
// [2] 1920 / 640 * 640 -> 1920
|
||||
// [3] 1920 / 512 * 512 -> 1536
|
||||
|
||||
10: begin
|
||||
narrow <= ((div_num[11:0] - mul_res[11:0]) <= (wideres - div_num[11:0])) || (wideres > HDMI_WIDTH);
|
||||
wres <= wideres;
|
||||
hinteger <= mul_res[11:0];
|
||||
mul_arg1 <= vsize;
|
||||
mul_arg2 <= div_res[11:0] ? div_res[11:0] : 12'd1;
|
||||
mul_start <= 1;
|
||||
end
|
||||
|
||||
11: begin
|
||||
oheight <= mul_res[11:0];
|
||||
end
|
||||
|
||||
12: begin
|
||||
wideres <= hinteger + hsize;
|
||||
narrow <= ((htarget - hinteger) <= (wideres - htarget)) || (wideres > HDMI_WIDTH);
|
||||
wres <= hinteger == htarget ? hinteger : wideres;
|
||||
end
|
||||
// [1] 1066 - 720 = 346 <= 1440 - 1066 = 374 || 1440 > 1920 -> true
|
||||
// [2] 1280 - 1280 = 0 <= 1920 - 1280 = 640 || 1920 > 1920 -> true
|
||||
// [3] 1365 - 1024 = 341 <= 1536 - 1365 = 171 || 1536 > 1920 -> false
|
||||
// 1. narrow flag is true when mul_res[11:0] narrow width is closer to
|
||||
// htarget aspect ratio target width or when wideres wider width
|
||||
// does not fit to the screen.
|
||||
// 2. wres becomes wideres only when mul_res[11:0] narrow width not equal
|
||||
// to target width, meaning it is not optimal for source aspect ratio.
|
||||
// otherwise it is set to narrow width that is optimal.
|
||||
|
||||
13: begin
|
||||
case(SCALE)
|
||||
2: arxf <= {1'b1, mul_res[11:0]};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? mul_res[11:0] : wres};
|
||||
4: arxf <= {1'b1, narrow ? mul_res[11:0] : wres};
|
||||
2: arxf <= {1'b1, hinteger};
|
||||
3: arxf <= {1'b1, (wres > HDMI_WIDTH) ? hinteger : wres};
|
||||
4: arxf <= {1'b1, narrow ? hinteger : wres};
|
||||
default: arxf <= {1'b1, div_num[11:0]};
|
||||
endcase
|
||||
aryf <= {1'b1, oheight};
|
||||
|
|
|
|||
|
|
@ -36,13 +36,15 @@ module yc_out
|
|||
input hsync,
|
||||
input vsync,
|
||||
input csync,
|
||||
input de,
|
||||
|
||||
input [23:0] din,
|
||||
output [23:0] dout,
|
||||
|
||||
output reg hsync_o,
|
||||
output reg vsync_o,
|
||||
output reg csync_o
|
||||
output reg csync_o,
|
||||
output reg de_o
|
||||
);
|
||||
|
||||
wire [7:0] red = din[23:16];
|
||||
|
|
@ -61,6 +63,7 @@ typedef struct {
|
|||
logic hsync;
|
||||
logic vsync;
|
||||
logic csync;
|
||||
logic de;
|
||||
} phase_t;
|
||||
|
||||
localparam MAX_PHASES = 7'd8;
|
||||
|
|
@ -211,11 +214,11 @@ always_ff @(posedge clk) begin
|
|||
end
|
||||
|
||||
// Adjust sync timing correctly
|
||||
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync;
|
||||
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync;
|
||||
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync;
|
||||
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync;
|
||||
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync;
|
||||
phase[1].hsync <= hsync; phase[1].vsync <= vsync; phase[1].csync <= csync; phase[1].de <= de;
|
||||
phase[2].hsync <= phase[1].hsync; phase[2].vsync <= phase[1].vsync; phase[2].csync <= phase[1].csync; phase[2].de <= phase[1].de;
|
||||
phase[3].hsync <= phase[2].hsync; phase[3].vsync <= phase[2].vsync; phase[3].csync <= phase[2].csync; phase[3].de <= phase[2].de;
|
||||
phase[4].hsync <= phase[3].hsync; phase[4].vsync <= phase[3].vsync; phase[4].csync <= phase[3].csync; phase[4].de <= phase[3].de;
|
||||
hsync_o <= phase[4].hsync; vsync_o <= phase[4].vsync; csync_o <= phase[4].csync; de_o <= phase[4].de;
|
||||
|
||||
phase[1].y <= phase[0].y; phase[2].y <= phase[1].y; phase[3].y <= phase[2].y; phase[4].y <= phase[3].y; phase[5].y <= phase[4].y;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue