Update sys. Re-organizing the sources.

MacPlus.sdc

@@ -0,0 +1,5 @@
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_multicycle_path -from {emu|m68k|*} -setup 2
+set_multicycle_path -from {emu|m68k|*} -hold 1

files.qip

@@ -1,16 +1,17 @@
-set_global_assignment -name QIP_FILE src/tg68k/TG68K.qip
-set_global_assignment -name SYSTEMVERILOG_FILE src/sdram.sv
-set_global_assignment -name VERILOG_FILE src/scsi.v
-set_global_assignment -name VERILOG_FILE src/ncr5380.v
-set_global_assignment -name VERILOG_FILE src/floppy_track_encoder.v
-set_global_assignment -name VERILOG_FILE src/floppy.v
-set_global_assignment -name SYSTEMVERILOG_FILE src/ps2_kbd.sv
-set_global_assignment -name VERILOG_FILE src/ps2_mouse.v
-set_global_assignment -name VERILOG_FILE src/scc.v
-set_global_assignment -name VERILOG_FILE src/iwm.v
-set_global_assignment -name VERILOG_FILE src/via.v
-set_global_assignment -name VERILOG_FILE src/addrDecoder.v
-set_global_assignment -name VERILOG_FILE src/addrController_top.v
-set_global_assignment -name VERILOG_FILE src/dataController_top.v
-set_global_assignment -name VERILOG_FILE src/video.v
+set_global_assignment -name QIP_FILE rtl/tg68k/TG68K.qip
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
+set_global_assignment -name VERILOG_FILE rtl/scsi.v
+set_global_assignment -name VERILOG_FILE rtl/ncr5380.v
+set_global_assignment -name VERILOG_FILE rtl/floppy_track_encoder.v
+set_global_assignment -name VERILOG_FILE rtl/floppy.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ps2_kbd.sv
+set_global_assignment -name VERILOG_FILE rtl/ps2_mouse.v
+set_global_assignment -name VERILOG_FILE rtl/scc.v
+set_global_assignment -name VERILOG_FILE rtl/iwm.v
+set_global_assignment -name VERILOG_FILE rtl/via.v
+set_global_assignment -name VERILOG_FILE rtl/addrDecoder.v
+set_global_assignment -name VERILOG_FILE rtl/addrController_top.v
+set_global_assignment -name VERILOG_FILE rtl/dataController_top.v
+set_global_assignment -name VERILOG_FILE rtl/video.v
+set_global_assignment -name SDC_FILE MacPlus.sdc
 set_global_assignment -name SYSTEMVERILOG_FILE MacPlus.sv

sys/osd.v

@@ -38,7 +38,7 @@ reg        osd_enable;
 reg        info = 0;
 reg  [8:0] infoh;
 reg  [8:0] infow;
-reg [11:0] infox;
+reg [21:0] infox;
 reg [21:0] infoy;
 reg [21:0] osd_h;
 reg [21:0] osd_t;
@@ -123,31 +123,39 @@ end
 reg  [2:0] osd_de;
 reg        osd_pixel;
 reg [21:0] v_cnt;
-
-reg v_cnt_half, v_cnt_single, v_cnt_double, v_cnt_triple;
-
-reg [21:0] v_osd_start_h, v_osd_start_s, v_osd_start_d, v_osd_start_t, v_osd_start_q;
+reg        v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4;
+reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5;
+reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5;
 
 wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
 
 // pipeline the comparisons a bit
 always @(posedge clk_video) if(ce_pix) begin
-	v_cnt_half    <= v_cnt < osd_t;
-	v_cnt_single  <= v_cnt < 320;
-	v_cnt_double  <= v_cnt < 640;
-	v_cnt_triple  <= v_cnt < 960;
+	v_cnt_h <= v_cnt < osd_t;
+	v_cnt_1 <= v_cnt < 320;
+	v_cnt_2 <= v_cnt < 640;
+	v_cnt_3 <= v_cnt < 960;
+	v_cnt_4 <= v_cnt < 1280;
 
-	v_osd_start_h <= ((v_cnt-(osd_h_hdr>>1))>>1);
-	v_osd_start_s <= ((v_cnt-osd_h_hdr)>>1);
-	v_osd_start_d <= ((v_cnt-(osd_h_hdr<<1))>>1);
-	v_osd_start_t <= ((v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1);
-	v_osd_start_q <= ((v_cnt-(osd_h_hdr<<2))>>1);
+	v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1;
+	v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1;
+	v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1;
+	v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1;
+	v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1;
+	v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1;
+
+	v_info_start_h <= rot[0] ? infox : infoy;
+	v_info_start_1 <= rot[0] ? infox : infoy;
+	v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1);
+	v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1));
+	v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2);
+	v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2));
 end
 
 always @(posedge clk_video) begin
 	reg        deD;
-	reg  [1:0] osd_div;
-	reg  [1:0] multiscan;
+	reg  [2:0] osd_div;
+	reg  [2:0] multiscan;
 	reg  [7:0] osd_byte; 
 	reg [23:0] h_cnt;
 	reg [21:0] dsp_width;
@@ -199,26 +207,30 @@ always @(posedge clk_video) begin
 					if(~osd_enable) osd_en <= 0;
 
 					half <= 0;
-					if(v_cnt_half) begin
+					if(v_cnt_h) begin
 						multiscan <= 0;
-						v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_h;
+						v_osd_start <= info ? v_info_start_h : v_osd_start_h;
 						half <= 1;
 					end
-					else if(v_cnt_single | (rot[0] & v_cnt_double)) begin
+					else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin
 						multiscan <= 0;
-						v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_s;
+						v_osd_start <= info ? v_info_start_1 : v_osd_start_1;
 					end
-					else if(rot[0] ? v_cnt_triple : v_cnt_double) begin
+					else if(rot[0] ? v_cnt_3 : v_cnt_2) begin
 						multiscan <= 1;
-						v_osd_start <= info ? (rot[0] ? (infox<<1) : (infoy<<1)) : v_osd_start_d;
+						v_osd_start <= info ? v_info_start_2 : v_osd_start_2;
 					end
-					else if(v_cnt_triple | rot[0]) begin
+					else if(rot[0] ? v_cnt_4 : v_cnt_3) begin
 						multiscan <= 2;
-						v_osd_start <= info ? (rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1))) : v_osd_start_t;
+						v_osd_start <= info ? v_info_start_3 : v_osd_start_3;
+					end
+					else if(rot[0] | v_cnt_4) begin
+						multiscan <= 3;
+						v_osd_start <= info ? v_info_start_4 : v_osd_start_4;
 					end
 					else begin
-						multiscan <= 3;
-						v_osd_start <= info ? (rot[0] ? (infox<<2) : (infoy<<2)) : v_osd_start_q;
+						multiscan <= 4;
+						v_osd_start <= info ? v_info_start_5 : v_osd_start_5;
 					end
 				end
 			end

sys/pll.13.qip

@@ -4,9 +4,13 @@ set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
 set_global_assignment -name SYNTHESIS_ONLY_QIP ON
 
-set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
-set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
-set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"]
+set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v
+set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v
+
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*" 
 
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
 set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"

sys/pll/pll_0002_q13.qip

@@ -1,4 +0,0 @@
-set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

sys/pll_hdmi.13.qip

@@ -6,7 +6,11 @@ set_global_assignment -name SYNTHESIS_ONLY_QIP ON
 
 set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
 set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
-set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
+
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
 
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"

sys/pll_hdmi/pll_hdmi_0002_q13.qip

@@ -1,4 +0,0 @@
-set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
-set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

sys/pll_q17.qip

@@ -1,3 +1,3 @@
-set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll.qip ]
+set_global_assignment -name QIP_FILE           rtl/pll.qip
 set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_hdmi.qip ]
 set_global_assignment -name QIP_FILE           [file join $::quartus(qip_path) pll_cfg.qip ]

sys/sys_top.sdc

@@ -28,13 +28,16 @@ set_false_path -to {cfg[*]}
 set_false_path -from {cfg[*]}
 set_false_path -from {VSET[*]}
 set_false_path -to {wcalc[*] hcalc[*]}
+set_false_path -to {width[*] height[*]}
 
 set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
-set_multicycle_path -to {*_osd|osd_vcnt*} -hold 2
+set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
 set_false_path -to {*_osd|v_cnt*}
 set_false_path -to {*_osd|v_osd_start*}
+set_false_path -to {*_osd|v_info_start*}
 set_false_path -to {*_osd|h_osd_start*}
 set_false_path -from {*_osd|v_osd_start*}
+set_false_path -from {*_osd|v_info_start*}
 set_false_path -from {*_osd|h_osd_start*}
 set_false_path -from {*_osd|rot*}
 set_false_path -from {*_osd|dsp_width*}

sys/sys_top.v

@@ -235,7 +235,6 @@ wire        io_clk = gp_outr[17];
 wire        io_ss0 = gp_outr[18];
 wire        io_ss1 = gp_outr[19];
 wire        io_ss2 = gp_outr[20];
-//wire        io_sdd    = gp_outr[21]; // used only in ST core
 
 wire io_osd_hdmi = io_ss1 & ~io_ss0;
 wire io_fpga     = ~io_ss1 & io_ss0;
@@ -303,13 +302,16 @@ reg  [8:0] coef_data;
 reg        coef_wr = 0;
 
 wire [7:0] ARX, ARY;
-reg [11:0] VSET = 0;
+reg [11:0] VSET = 0, HSET = 0;
+reg        FREESCALE = 0;
 reg  [2:0] scaler_flt;
 reg        lowlat = 0;
 reg        cfg_dis = 0;
 
 reg        vs_wait = 0;
+reg [11:0] vs_line = 0;
 
+reg        scaler_out = 0;
 always@(posedge clk_sys) begin
 	reg  [7:0] cmd;
 	reg        has_cmd;
@@ -336,6 +338,7 @@ always@(posedge clk_sys) begin
 			if(cmd == 1) begin
 				cfg <= io_din;
 				cfg_set <= 1;
+				scaler_out <= 1;
 			end
 			if(cmd == 'h20) begin
 				cfg_set <= 0;
@@ -384,12 +387,14 @@ always@(posedge clk_sys) begin
 			end
 			if(cmd == 'h25) {led_overtake, led_state} <= io_din;
 			if(cmd == 'h26) vol_att <= io_din[4:0];
-			if(cmd == 'h27) VSET    <= io_din[11:0];
+			if(cmd == 'h27) VSET <= io_din[11:0];
 			if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
 			if(cmd == 'h2B) scaler_flt <= io_din[2:0];
+			if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
+			if(cmd == 'h38) vs_line <= io_din[11:0];
 		end
 	end
-	
+
 	vs_d0 <= HDMI_TX_VS;
 	if(vs_d0 == HDMI_TX_VS) vs_d1 <= vs_d0;
 
@@ -434,7 +439,7 @@ cyclonev_hps_interface_peripheral_spi_master spi
 	.ss_in_n(1)
 );
 
-wire [63:0] f2h_irq = {HDMI_TX_VS};
+wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS};
 cyclonev_hps_interface_interrupts interrupts
 (
 	.irq(f2h_irq)
@@ -599,7 +604,7 @@ ascal
 	.vimax    (0),
 
 	.o_clk    (clk_hdmi),
-	.o_ce     (1),
+	.o_ce     (scaler_out),
 	.o_r      (hdmi_data[23:16]),
 	.o_g      (hdmi_data[15:8]),
 	.o_b      (hdmi_data[7:0]),
@@ -671,7 +676,12 @@ always @(posedge clk_vid) begin
 	reg  [2:0] state;
 	reg [11:0] videow;
 	reg [11:0] videoh;
-	
+	reg [11:0] height;
+	reg [11:0] width;
+
+	height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
+	width  <= (HSET && (HSET < WIDTH))  ? HSET : WIDTH;
+
 	state <= state + 1'd1;
 	case(state)
 		0: if(FB_EN) begin
@@ -681,22 +691,17 @@ always @(posedge clk_vid) begin
 				vmax <= FB_VMAX;
 				state<= 0;
 			end
-			else if(ARX && ARY) begin
-				wcalc <= VSET ? (VSET*ARX)/ARY : (HEIGHT*ARX)/ARY;
-				hcalc <= (WIDTH*ARY)/ARX;
+			else if(ARX && ARY && !FREESCALE) begin
+				wcalc <= (height*ARX)/ARY;
+				hcalc <= (width*ARY)/ARX;
 			end
 			else begin
-				hmin <= 0;
-				hmax <= WIDTH - 1'd1;
-				vmin <= 0;
-				vmax <= HEIGHT - 1'd1;
-				wcalc<= WIDTH;
-				hcalc<= HEIGHT;
-				state<= 0;
+				wcalc <= width;
+				hcalc <= height;
 			end
 		6: begin
-				videow <= (!VSET && (wcalc > WIDTH))     ? WIDTH  : wcalc[11:0];
-				videoh <= VSET ? VSET : (hcalc > HEIGHT) ? HEIGHT : hcalc[11:0];
+				videow <= (wcalc > width)  ? width  : wcalc[11:0];
+				videoh <= (hcalc > height) ? height : hcalc[11:0];
 			end
 		7: begin
 				hmin <= ((WIDTH  - videow)>>1);
@@ -1047,6 +1052,31 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
 	assign VGA_B  = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2];
 `endif
 
+reg video_sync = 0;
+always @(posedge clk_vid) begin
+	reg [11:0] line_cnt  = 0;
+	reg [11:0] sync_line = 0;
+	reg  [1:0] hs_cnt = 0;
+	reg        old_hs;
+
+	old_hs <= hs_fix;
+	if(~old_hs & hs_fix) begin
+
+		video_sync <= (sync_line == line_cnt);
+
+		line_cnt <= line_cnt + 1'd1;
+		if(~hs_cnt[1]) begin	
+			hs_cnt <= hs_cnt + 1'd1;
+			if(hs_cnt[0]) begin
+				sync_line <= (line_cnt - vs_line);
+				line_cnt <= 0;
+			end
+		end
+	end
+
+	if(de_emu) hs_cnt <= 0;
+end
+
 /////////////////////////  Audio output  ////////////////////////////////
 
 assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;

sys/video_mixer.sv

@@ -185,41 +185,54 @@ end
 wire hde = scandoubler ? ~hb_sd : ~hb_g;
 wire vde = scandoubler ? ~vb_sd : ~vb_g;
 
+reg [7:0] v_r,v_g,v_b;
+reg       v_vs,v_hs,v_de;
 always @(posedge clk_vid) begin
 	reg old_hde;
 
-	case(scanlines & {scanline, scanline})
-		1: begin // reduce 25% = 1/2 + 1/4
-			VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
-			VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
-			VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
-		end
+	if(ce_pix_out) begin
+		case(scanlines & {scanline, scanline})
+			1: begin // reduce 25% = 1/2 + 1/4
+				v_r <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
+				v_g <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
+				v_b <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
+			end
 
-		2: begin // reduce 50% = 1/2
-			VGA_R <= {1'b0, r[7:1]};
-			VGA_G <= {1'b0, g[7:1]};
-			VGA_B <= {1'b0, b[7:1]};
-		end
+			2: begin // reduce 50% = 1/2
+				v_r <= {1'b0, r[7:1]};
+				v_g <= {1'b0, g[7:1]};
+				v_b <= {1'b0, b[7:1]};
+			end
 
-		3: begin // reduce 75% = 1/4
-			VGA_R <= {2'b00, r[7:2]};
-			VGA_G <= {2'b00, g[7:2]};
-			VGA_B <= {2'b00, b[7:2]};
-		end
+			3: begin // reduce 75% = 1/4
+				v_r <= {2'b00, r[7:2]};
+				v_g <= {2'b00, g[7:2]};
+				v_b <= {2'b00, b[7:2]};
+			end
 
-		default: begin
-			VGA_R <= r;
-			VGA_G <= g;
-			VGA_B <= b;
-		end
-	endcase
+			default: begin
+				v_r <= r;
+				v_g <= g;
+				v_b <= b;
+			end
+		endcase
 
-	VGA_VS <= vs;
-	VGA_HS <= hs;
+		v_vs <= vs;
+		v_hs <= hs;
 
-	old_hde <= hde;
-	if(~old_hde && hde) VGA_DE <= vde;
-	if(old_hde && ~hde) VGA_DE <= 0;
+		old_hde <= hde;
+		if(~old_hde && hde) v_de <= vde;
+		if(old_hde && ~hde) v_de <= 0;
+	end
+end
+
+always @(posedge clk_vid) if(ce_pix_out) begin
+	VGA_R  <= v_r;
+	VGA_G  <= v_g;
+	VGA_B  <= v_b;
+	VGA_HS <= v_hs;
+	VGA_VS <= v_vs;
+	VGA_DE <= v_de;
 end
 
 endmodule