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Update sys. Re-organizing the sources.

This commit is contained in:
sorgelig 2020-05-11 02:35:08 +08:00
parent 1b5314cc30
commit c996f472ab
34 changed files with 1052 additions and 1056 deletions
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5
MacPlus.sdc Normal file
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@ -0,0 +1,5 @@
derive_pll_clocks
derive_clock_uncertainty
set_multicycle_path -from {emu|m68k|*} -setup 2
set_multicycle_path -from {emu|m68k|*} -hold 1

31
files.qip
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@ -1,16 +1,17 @@
set_global_assignment -name QIP_FILE src/tg68k/TG68K.qip
set_global_assignment -name SYSTEMVERILOG_FILE src/sdram.sv
set_global_assignment -name VERILOG_FILE src/scsi.v
set_global_assignment -name VERILOG_FILE src/ncr5380.v
set_global_assignment -name VERILOG_FILE src/floppy_track_encoder.v
set_global_assignment -name VERILOG_FILE src/floppy.v
set_global_assignment -name SYSTEMVERILOG_FILE src/ps2_kbd.sv
set_global_assignment -name VERILOG_FILE src/ps2_mouse.v
set_global_assignment -name VERILOG_FILE src/scc.v
set_global_assignment -name VERILOG_FILE src/iwm.v
set_global_assignment -name VERILOG_FILE src/via.v
set_global_assignment -name VERILOG_FILE src/addrDecoder.v
set_global_assignment -name VERILOG_FILE src/addrController_top.v
set_global_assignment -name VERILOG_FILE src/dataController_top.v
set_global_assignment -name VERILOG_FILE src/video.v
set_global_assignment -name QIP_FILE rtl/tg68k/TG68K.qip
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/scsi.v
set_global_assignment -name VERILOG_FILE rtl/ncr5380.v
set_global_assignment -name VERILOG_FILE rtl/floppy_track_encoder.v
set_global_assignment -name VERILOG_FILE rtl/floppy.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ps2_kbd.sv
set_global_assignment -name VERILOG_FILE rtl/ps2_mouse.v
set_global_assignment -name VERILOG_FILE rtl/scc.v
set_global_assignment -name VERILOG_FILE rtl/iwm.v
set_global_assignment -name VERILOG_FILE rtl/via.v
set_global_assignment -name VERILOG_FILE rtl/addrDecoder.v
set_global_assignment -name VERILOG_FILE rtl/addrController_top.v
set_global_assignment -name VERILOG_FILE rtl/dataController_top.v
set_global_assignment -name VERILOG_FILE rtl/video.v
set_global_assignment -name SDC_FILE MacPlus.sdc
set_global_assignment -name SYSTEMVERILOG_FILE MacPlus.sv

0
src/addrController_top.v → rtl/addrController_top.v
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src/addrDecoder.v → rtl/addrDecoder.v
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src/dataController_top.v → rtl/dataController_top.v
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src/floppy.v → rtl/floppy.v
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src/floppy_track_encoder.v → rtl/floppy_track_encoder.v
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src/iwm.v → rtl/iwm.v
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src/ncr5380.v → rtl/ncr5380.v
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sys/pll.qip → rtl/pll.qip
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sys/pll.v → rtl/pll.v
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sys/pll/pll_0002.qip → rtl/pll/pll_0002.qip
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sys/pll/pll_0002.v → rtl/pll/pll_0002.v
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src/ps2_kbd.sv → rtl/ps2_kbd.sv
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src/ps2_mouse.v → rtl/ps2_mouse.v
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src/scc.v → rtl/scc.v
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src/scsi.v → rtl/scsi.v
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src/sdram.sv → rtl/sdram.sv
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src/tg68k/TG68K.qip → rtl/tg68k/TG68K.qip
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src/tg68k/TG68K_ALU.vhd → rtl/tg68k/TG68K_ALU.vhd
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src/tg68k/TG68K_Pack.vhd → rtl/tg68k/TG68K_Pack.vhd
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src/tg68k/TG68KdotC_Kernel.vhd → rtl/tg68k/TG68KdotC_Kernel.vhd
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src/via.v → rtl/via.v
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src/video.v → rtl/video.v
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210
sys/hps_io.v
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@ -2,7 +2,7 @@
// hps_io.v
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017-2019 Alexey Melnikov
// Copyright (c) 2017-2020 Alexey Melnikov
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
@ -18,14 +18,11 @@
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
// altera message_off 10665
//
// Use buffer to access SD card. It's time-critical part.
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = CLK_SYS/(PS2DIV*2)
//
// WIDE=1 for 16 bit file I/O
// VDNUM 1-4
module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
@ -36,12 +33,15 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// buttons up to 32
output reg [31:0] joystick_0,
output reg [31:0] joystick_1,
output reg [31:0] joystick_2,
output reg [31:0] joystick_3,
output reg [31:0] joystick_4,
output reg [31:0] joystick_5,
// analog -127..+127, Y: [15:8], X: [7:0]
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output reg [15:0] joystick_analog_2,
@ -49,6 +49,22 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
output reg [15:0] joystick_analog_4,
output reg [15:0] joystick_analog_5,
// paddle 0..255
output reg [7:0] paddle_0,
output reg [7:0] paddle_1,
output reg [7:0] paddle_2,
output reg [7:0] paddle_3,
output reg [7:0] paddle_4,
output reg [7:0] paddle_5,
// spinner [7:0] -128..+127, [8] - toggle with every update
output reg [8:0] spinner_0,
output reg [8:0] spinner_1,
output reg [8:0] spinner_2,
output reg [8:0] spinner_3,
output reg [8:0] spinner_4,
output reg [8:0] spinner_5,
output [1:0] buttons,
output forced_scandoubler,
output direct_video,
@ -109,10 +125,6 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
// UART flags
input [15:0] uart_mode,
// CD interface
input [48:0] cd_in,
output reg [48:0] cd_out,
// ps2 keyboard emulation
output ps2_kbd_clk_out,
output ps2_kbd_data_out,
@ -136,24 +148,32 @@ module hps_io #(parameter STRLEN=0, PS2DIV=0, WIDE=0, VDNUM=1, PS2WE=0)
output reg [24:0] ps2_mouse = 0,
output reg [15:0] ps2_mouse_ext = 0, // 15:8 - reserved(additional buttons), 7:0 - wheel movements
inout [21:0] gamma_bus
inout [21:0] gamma_bus,
// for core-specific extensions
inout [35:0] EXT_BUS
);
assign EXT_BUS[31:16] = HPS_BUS[31:16];
assign EXT_BUS[35:33] = HPS_BUS[35:33];
localparam MAX_W = $clog2((512 > (STRLEN+1)) ? 512 : (STRLEN+1))-1;
localparam DW = (WIDE) ? 15 : 7;
localparam AW = (WIDE) ? 7 : 8;
localparam VD = VDNUM-1;
wire io_wait = ioctl_wait;
wire io_enable= |HPS_BUS[35:34];
wire io_strobe= HPS_BUS[33];
wire io_enable= HPS_BUS[34];
wire fp_enable= HPS_BUS[35];
wire io_wide = (WIDE) ? 1'b1 : 1'b0;
wire [15:0] io_din = HPS_BUS[31:16];
reg [15:0] io_dout;
assign HPS_BUS[37] = io_wait;
assign HPS_BUS[37] = ioctl_wait;
assign HPS_BUS[36] = clk_sys;
assign HPS_BUS[32] = io_wide;
assign HPS_BUS[15:0] = io_dout;
assign HPS_BUS[15:0] = EXT_BUS[32] ? EXT_BUS[15:0] : io_dout;
reg [15:0] cfg;
assign buttons = cfg[1:0];
@ -212,18 +232,17 @@ reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
reg [9:0] byte_cnt;
reg [MAX_W:0] byte_cnt;
always@(posedge clk_sys) begin
reg [15:0] cmd;
reg [2:0] b_wr;
reg [2:0] stick_idx;
reg [3:0] stick_idx;
reg [3:0] pdsp_idx;
reg ps2skip = 0;
reg [3:0] stflg = 0;
reg [63:0] status_req;
reg old_status_set = 0;
reg [7:0] cd_req = 0;
reg old_cd = 0;
reg old_info = 0;
reg [7:0] info_n = 0;
@ -236,9 +255,6 @@ always@(posedge clk_sys) begin
old_info <= info_req;
if(~old_info & info_req) info_n <= info;
old_cd <= cd_in[48];
if(old_cd ^ cd_in[48]) cd_req <= cd_req + 1'd1;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
@ -257,15 +273,14 @@ always@(posedge clk_sys) begin
end
if(cmd == 'h22) RTC[64] <= ~RTC[64];
if(cmd == 'h24) TIMESTAMP[32] <= ~TIMESTAMP[32];
if(cmd == 'h35) cd_out[48] <= ~cd_out[48];
cmd <= 0;
byte_cnt <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
io_dout <= 0;
ps2skip <= 0;
end else begin
if(io_strobe) begin
end
else if(io_strobe) begin
io_dout <= 0;
if(~&byte_cnt) byte_cnt <= byte_cnt + 1'd1;
@ -281,7 +296,6 @@ always@(posedge clk_sys) begin
'h2B: io_dout <= 1;
'h2F: io_dout <= 1;
'h32: io_dout <= gamma_bus[21];
'h34: io_dout <= cd_req;
'h36: begin io_dout <= info_n; info_n <= 0; end
endcase
@ -307,13 +321,13 @@ always@(posedge clk_sys) begin
mouse_we <= 1;
end
if(&io_din[15:8]) ps2skip <= 1;
if(~&io_din[15:8] & ~ps2skip) begin
case(byte_cnt)
if(~&io_din[15:8] && ~ps2skip && !byte_cnt[MAX_W:2]) begin
case(byte_cnt[1:0])
1: ps2_mouse[7:0] <= io_din[7:0];
2: ps2_mouse[15:8] <= io_din[7:0];
3: ps2_mouse[23:16] <= io_din[7:0];
endcase
case(byte_cnt)
case(byte_cnt[1:0])
1: ps2_mouse_ext[7:0] <= {io_din[14], io_din[14:8]};
2: ps2_mouse_ext[11:8] <= io_din[11:8];
3: ps2_mouse_ext[15:12]<= io_din[11:8];
@ -335,12 +349,14 @@ always@(posedge clk_sys) begin
'h14: if(byte_cnt < STRLEN + 1) io_dout[7:0] <= conf_str[(STRLEN - byte_cnt)<<3 +:8];
// reading sd card status
'h16: case(byte_cnt)
'h16: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: io_dout <= sd_cmd;
2: io_dout <= sd_lba[15:0];
3: io_dout <= sd_lba[31:16];
4: io_dout <= sd_req_type;
endcase
end
// send SD config IO -> FPGA
// flag that download begins
@ -361,8 +377,9 @@ always@(posedge clk_sys) begin
end
// joystick analog
'h1a: case(byte_cnt)
1: stick_idx <= io_din[2:0]; // first byte is joystick index
'h1a: if(!byte_cnt[MAX_W:2]) begin
case(byte_cnt[1:0])
1: {pdsp_idx,stick_idx} <= io_din[7:0]; // first byte is joystick index
2: case(stick_idx)
0: joystick_analog_0 <= io_din;
1: joystick_analog_1 <= io_din;
@ -370,8 +387,23 @@ always@(posedge clk_sys) begin
3: joystick_analog_3 <= io_din;
4: joystick_analog_4 <= io_din;
5: joystick_analog_5 <= io_din;
15: case(pdsp_idx)
0: paddle_0 <= io_din[7:0];
1: paddle_1 <= io_din[7:0];
2: paddle_2 <= io_din[7:0];
3: paddle_3 <= io_din[7:0];
4: paddle_4 <= io_din[7:0];
5: paddle_5 <= io_din[7:0];
8: spinner_0 <= {~spinner_0[8],io_din[7:0]};
9: spinner_1 <= {~spinner_1[8],io_din[7:0]};
10: spinner_2 <= {~spinner_2[8],io_din[7:0]};
11: spinner_3 <= {~spinner_3[8],io_din[7:0]};
12: spinner_4 <= {~spinner_4[8],io_din[7:0]};
13: spinner_5 <= {~spinner_5[8],io_din[7:0]};
endcase
endcase
endcase
end
// notify image selection
'h1c: begin
@ -383,12 +415,14 @@ always@(posedge clk_sys) begin
'h1d: if(byte_cnt<5) img_size[{byte_cnt-1'b1, 4'b0000} +:16] <= io_din;
// status, 64bit version
'h1e: case(byte_cnt)
'h1e: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: status[15:00] <= io_din;
2: status[31:16] <= io_din;
3: status[47:32] <= io_din;
4: status[63:48] <= io_din;
endcase
end
// reading keyboard LED status
'h1f: io_dout <= {|PS2WE, 2'b01, ps2_kbd_led_status[2], ps2_kbd_led_use[2], ps2_kbd_led_status[1], ps2_kbd_led_use[1], ps2_kbd_led_status[0], ps2_kbd_led_use[0]};
@ -410,7 +444,7 @@ always@(posedge clk_sys) begin
'h22: RTC[(byte_cnt-6'd1)<<4 +:16] <= io_din;
//Video res.
'h23: if(!byte_cnt[9:4]) io_dout <= vc_dout;
'h23: if(!byte_cnt[MAX_W:4]) io_dout <= vc_dout;
//RTC
'h24: TIMESTAMP[(byte_cnt-6'd1)<<4 +:16] <= io_din;
@ -419,12 +453,14 @@ always@(posedge clk_sys) begin
'h28: io_dout <= uart_mode;
//status set
'h29: case(byte_cnt)
'h29: if(!byte_cnt[MAX_W:3]) begin
case(byte_cnt[2:0])
1: io_dout <= status_req[15:00];
2: io_dout <= status_req[31:16];
3: io_dout <= status_req[47:32];
4: io_dout <= status_req[63:48];
endcase
end
//menu mask
'h2E: if(byte_cnt == 1) io_dout <= status_menumask;
@ -439,22 +475,7 @@ always@(posedge clk_sys) begin
{gamma_wr, gamma_value} <= {1'b1,io_din[7:0]};
if (byte_cnt[1:0] == 3) byte_cnt <= 1;
end
//CD get
'h34: case(byte_cnt)
1: io_dout <= cd_in[15:0];
2: io_dout <= cd_in[31:16];
3: io_dout <= cd_in[47:32];
endcase
//CD set
'h35: case(byte_cnt)
1: cd_out[15:0] <= io_din;
2: cd_out[31:16] <= io_din;
3: cd_out[47:32] <= io_din;
endcase
endcase
end
end
end
end
@ -544,7 +565,7 @@ always@(posedge clk_sys) begin
ioctl_wr <= wr;
wr <= 0;
if(~io_enable) has_cmd <= 0;
if(~fp_enable) has_cmd <= 0;
else begin
if(io_strobe) begin
@ -873,92 +894,3 @@ always @(posedge clk_100) begin
end
endmodule
//
// Phase shift helper module for better 64MB/128MB modules support.
//
// Copyright (c) 2019 Alexey Melnikov
//
module phase_shift #(parameter M32MB=0, M64MB=0, M128MB=0)
(
input reset,
input clk,
input pll_locked,
output reg phase_en,
output reg updn,
input phase_done,
input [15:0] sdram_sz,
output reg ready
);
localparam ph32 = ($signed(M32MB ) >= 0) ? M32MB : (0 - M32MB);
localparam ph64 = ($signed(M64MB ) >= 0) ? M64MB : (0 - M64MB);
localparam ph128 = ($signed(M128MB) >= 0) ? M128MB : (0 - M128MB);
localparam up32 = ($signed(M32MB ) >= 0) ? 1'b1 : 1'b0;
localparam up64 = ($signed(M64MB ) >= 0) ? 1'b1 : 1'b0;
localparam up128 = ($signed(M128MB) >= 0) ? 1'b1 : 1'b0;
always @(posedge clk, posedge reset) begin
reg [2:0] state = 0;
reg [7:0] cnt;
reg [8:0] ph;
if(reset) begin
state <= 0;
ready <= 0;
end
else begin
case(state)
0: begin
ready <= 0;
if(pll_locked) state <= state + 1'd1;
end
1: if(sdram_sz[15]) begin
cnt <= 0;
if(sdram_sz[14]) ph <= sdram_sz[8:0];
else begin
case(sdram_sz[1:0])
0: ph <= 0;
1: ph <= {up32[0],ph32[7:0]};
2: ph <= {up64[0],ph64[7:0]};
3: ph <= {up128[0],ph128[7:0]};
endcase
end
state <= state + 1'd1;
end
2: if(ph[7:0]) begin
ph[7:0] <= ph[7:0] - 1'd1;
updn <= ph[8];
state <= state + 1'd1;
end
else begin
state <= 6;
end
3: begin
phase_en <= 1;
state <= state + 1'd1;
end
4: if(~phase_done) begin
phase_en <= 0;
state <= state + 1'd1;
end
5: if(phase_done) begin
cnt <= cnt + 1'd1;
if(cnt == ph[7:0]) state <= state + 1'd1;
else state <= 3;
end
6: begin
ready <= 1;
if(!sdram_sz[15]) state <= 0;
end
endcase
end
end
endmodule

64
sys/osd.v
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@ -38,7 +38,7 @@ reg osd_enable;
reg info = 0;
reg [8:0] infoh;
reg [8:0] infow;
reg [11:0] infox;
reg [21:0] infox;
reg [21:0] infoy;
reg [21:0] osd_h;
reg [21:0] osd_t;
@ -123,31 +123,39 @@ end
reg [2:0] osd_de;
reg osd_pixel;
reg [21:0] v_cnt;
reg v_cnt_half, v_cnt_single, v_cnt_double, v_cnt_triple;
reg [21:0] v_osd_start_h, v_osd_start_s, v_osd_start_d, v_osd_start_t, v_osd_start_q;
reg v_cnt_h, v_cnt_1, v_cnt_2, v_cnt_3, v_cnt_4;
reg [21:0] v_osd_start_h, v_osd_start_1, v_osd_start_2, v_osd_start_3, v_osd_start_4, v_osd_start_5;
reg [21:0] v_info_start_h, v_info_start_1, v_info_start_2, v_info_start_3, v_info_start_4, v_info_start_5;
wire [21:0] osd_h_hdr = (info || rot) ? osd_h : (osd_h + OSD_HDR);
// pipeline the comparisons a bit
always @(posedge clk_video) if(ce_pix) begin
v_cnt_half <= v_cnt < osd_t;
v_cnt_single <= v_cnt < 320;
v_cnt_double <= v_cnt < 640;
v_cnt_triple <= v_cnt < 960;
v_cnt_h <= v_cnt < osd_t;
v_cnt_1 <= v_cnt < 320;
v_cnt_2 <= v_cnt < 640;
v_cnt_3 <= v_cnt < 960;
v_cnt_4 <= v_cnt < 1280;
v_osd_start_h <= ((v_cnt-(osd_h_hdr>>1))>>1);
v_osd_start_s <= ((v_cnt-osd_h_hdr)>>1);
v_osd_start_d <= ((v_cnt-(osd_h_hdr<<1))>>1);
v_osd_start_t <= ((v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1);
v_osd_start_q <= ((v_cnt-(osd_h_hdr<<2))>>1);
v_osd_start_h <= (v_cnt-(osd_h_hdr>>1))>>1;
v_osd_start_1 <= (v_cnt-osd_h_hdr)>>1;
v_osd_start_2 <= (v_cnt-(osd_h_hdr<<1))>>1;
v_osd_start_3 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<1)))>>1;
v_osd_start_4 <= (v_cnt-(osd_h_hdr<<2))>>1;
v_osd_start_5 <= (v_cnt-(osd_h_hdr + (osd_h_hdr<<2)))>>1;
v_info_start_h <= rot[0] ? infox : infoy;
v_info_start_1 <= rot[0] ? infox : infoy;
v_info_start_2 <= rot[0] ? (infox<<1) : (infoy<<1);
v_info_start_3 <= rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1));
v_info_start_4 <= rot[0] ? (infox << 2) : (infoy << 2);
v_info_start_5 <= rot[0] ? (infox + (infox << 2)) : (infoy + (infoy << 2));
end
always @(posedge clk_video) begin
reg deD;
reg [1:0] osd_div;
reg [1:0] multiscan;
reg [2:0] osd_div;
reg [2:0] multiscan;
reg [7:0] osd_byte;
reg [23:0] h_cnt;
reg [21:0] dsp_width;
@ -199,26 +207,30 @@ always @(posedge clk_video) begin
if(~osd_enable) osd_en <= 0;
half <= 0;
if(v_cnt_half) begin
if(v_cnt_h) begin
multiscan <= 0;
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_h;
v_osd_start <= info ? v_info_start_h : v_osd_start_h;
half <= 1;
end
else if(v_cnt_single | (rot[0] & v_cnt_double)) begin
else if(v_cnt_1 | (rot[0] & v_cnt_2)) begin
multiscan <= 0;
v_osd_start <= info ? (rot[0] ? infox : infoy) : v_osd_start_s;
v_osd_start <= info ? v_info_start_1 : v_osd_start_1;
end
else if(rot[0] ? v_cnt_triple : v_cnt_double) begin
else if(rot[0] ? v_cnt_3 : v_cnt_2) begin
multiscan <= 1;
v_osd_start <= info ? (rot[0] ? (infox<<1) : (infoy<<1)) : v_osd_start_d;
v_osd_start <= info ? v_info_start_2 : v_osd_start_2;
end
else if(v_cnt_triple | rot[0]) begin
else if(rot[0] ? v_cnt_4 : v_cnt_3) begin
multiscan <= 2;
v_osd_start <= info ? (rot[0] ? (infox + (infox << 1)) : (infoy + (infoy << 1))) : v_osd_start_t;
v_osd_start <= info ? v_info_start_3 : v_osd_start_3;
end
else if(rot[0] | v_cnt_4) begin
multiscan <= 3;
v_osd_start <= info ? v_info_start_4 : v_osd_start_4;
end
else begin
multiscan <= 3;
v_osd_start <= info ? (rot[0] ? (infox<<2) : (infoy<<2)) : v_osd_start_q;
multiscan <= 4;
v_osd_start <= info ? v_info_start_5 : v_osd_start_5;
end
end
end

10
sys/pll.13.qip
View File

@ -4,9 +4,13 @@ set_global_assignment -entity "pll" -library "pll" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "pll" -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -library "pll" -name VERILOG_FILE [file join $::quartus(qip_path) "pll/pll_0002.v"]
set_global_assignment -library "pll" -name QIP_FILE [file join $::quartus(qip_path) "pll/pll_0002_q13.qip"]
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll.v
set_global_assignment -library "pll" -name VERILOG_FILE rtl/pll/pll_0002.v
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_0002" -library "pll" -name IP_TOOL_VERSION "13.1"

4
sys/pll/pll_0002_q13.qip
View File

@ -1,4 +0,0 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_0002*|altera_pll:altera_pll_i*|*"

6
sys/pll_hdmi.13.qip
View File

@ -6,7 +6,11 @@ set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi.v"]
set_global_assignment -library "pll_hdmi" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.v"]
set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002_q13.qip"]
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "13.1"

4
sys/pll_hdmi/pll_hdmi_0002_q13.qip
View File

@ -1,4 +0,0 @@
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"

2
sys/pll_q17.qip
View File

@ -1,3 +1,3 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll.qip ]
set_global_assignment -name QIP_FILE rtl/pll.qip
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_hdmi.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) pll_cfg.qip ]

5
sys/sys_top.sdc
View File

@ -28,13 +28,16 @@ set_false_path -to {cfg[*]}
set_false_path -from {cfg[*]}
set_false_path -from {VSET[*]}
set_false_path -to {wcalc[*] hcalc[*]}
set_false_path -to {width[*] height[*]}
set_multicycle_path -to {*_osd|osd_vcnt*} -setup 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 2
set_multicycle_path -to {*_osd|osd_vcnt*} -hold 1
set_false_path -to {*_osd|v_cnt*}
set_false_path -to {*_osd|v_osd_start*}
set_false_path -to {*_osd|v_info_start*}
set_false_path -to {*_osd|h_osd_start*}
set_false_path -from {*_osd|v_osd_start*}
set_false_path -from {*_osd|v_info_start*}
set_false_path -from {*_osd|h_osd_start*}
set_false_path -from {*_osd|rot*}
set_false_path -from {*_osd|dsp_width*}

62
sys/sys_top.v
View File

@ -235,7 +235,6 @@ wire io_clk = gp_outr[17];
wire io_ss0 = gp_outr[18];
wire io_ss1 = gp_outr[19];
wire io_ss2 = gp_outr[20];
//wire io_sdd = gp_outr[21]; // used only in ST core
wire io_osd_hdmi = io_ss1 & ~io_ss0;
wire io_fpga = ~io_ss1 & io_ss0;
@ -303,13 +302,16 @@ reg [8:0] coef_data;
reg coef_wr = 0;
wire [7:0] ARX, ARY;
reg [11:0] VSET = 0;
reg [11:0] VSET = 0, HSET = 0;
reg FREESCALE = 0;
reg [2:0] scaler_flt;
reg lowlat = 0;
reg cfg_dis = 0;
reg vs_wait = 0;
reg [11:0] vs_line = 0;
reg scaler_out = 0;
always@(posedge clk_sys) begin
reg [7:0] cmd;
reg has_cmd;
@ -336,6 +338,7 @@ always@(posedge clk_sys) begin
if(cmd == 1) begin
cfg <= io_din;
cfg_set <= 1;
scaler_out <= 1;
end
if(cmd == 'h20) begin
cfg_set <= 0;
@ -387,6 +390,8 @@ always@(posedge clk_sys) begin
if(cmd == 'h27) VSET <= io_din[11:0];
if(cmd == 'h2A) {coef_wr,coef_addr,coef_data} <= {1'b1,io_din};
if(cmd == 'h2B) scaler_flt <= io_din[2:0];
if(cmd == 'h37) {FREESCALE,HSET} <= {io_din[15],io_din[11:0]};
if(cmd == 'h38) vs_line <= io_din[11:0];
end
end
@ -434,7 +439,7 @@ cyclonev_hps_interface_peripheral_spi_master spi
.ss_in_n(1)
);
wire [63:0] f2h_irq = {HDMI_TX_VS};
wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS};
cyclonev_hps_interface_interrupts interrupts
(
.irq(f2h_irq)
@ -599,7 +604,7 @@ ascal
.vimax (0),
.o_clk (clk_hdmi),
.o_ce (1),
.o_ce (scaler_out),
.o_r (hdmi_data[23:16]),
.o_g (hdmi_data[15:8]),
.o_b (hdmi_data[7:0]),
@ -671,6 +676,11 @@ always @(posedge clk_vid) begin
reg [2:0] state;
reg [11:0] videow;
reg [11:0] videoh;
reg [11:0] height;
reg [11:0] width;
height <= (VSET && (VSET < HEIGHT)) ? VSET : HEIGHT;
width <= (HSET && (HSET < WIDTH)) ? HSET : WIDTH;
state <= state + 1'd1;
case(state)
@ -681,22 +691,17 @@ always @(posedge clk_vid) begin
vmax <= FB_VMAX;
state<= 0;
end
else if(ARX && ARY) begin
wcalc <= VSET ? (VSET*ARX)/ARY : (HEIGHT*ARX)/ARY;
hcalc <= (WIDTH*ARY)/ARX;
else if(ARX && ARY && !FREESCALE) begin
wcalc <= (height*ARX)/ARY;
hcalc <= (width*ARY)/ARX;
end
else begin
hmin <= 0;
hmax <= WIDTH - 1'd1;
vmin <= 0;
vmax <= HEIGHT - 1'd1;
wcalc<= WIDTH;
hcalc<= HEIGHT;
state<= 0;
wcalc <= width;
hcalc <= height;
end
6: begin
videow <= (!VSET && (wcalc > WIDTH)) ? WIDTH : wcalc[11:0];
videoh <= VSET ? VSET : (hcalc > HEIGHT) ? HEIGHT : hcalc[11:0];
videow <= (wcalc > width) ? width : wcalc[11:0];
videoh <= (hcalc > height) ? height : hcalc[11:0];
end
7: begin
hmin <= ((WIDTH - videow)>>1);
@ -1047,6 +1052,31 @@ csync csync_vga(clk_vid, vga_hs_osd, vga_vs_osd, vga_cs_osd);
assign VGA_B = (VGA_EN | SW[3]) ? 6'bZZZZZZ : vga_o[7:2];
`endif
reg video_sync = 0;
always @(posedge clk_vid) begin
reg [11:0] line_cnt = 0;
reg [11:0] sync_line = 0;
reg [1:0] hs_cnt = 0;
reg old_hs;
old_hs <= hs_fix;
if(~old_hs & hs_fix) begin
video_sync <= (sync_line == line_cnt);
line_cnt <= line_cnt + 1'd1;
if(~hs_cnt[1]) begin
hs_cnt <= hs_cnt + 1'd1;
if(hs_cnt[0]) begin
sync_line <= (line_cnt - vs_line);
line_cnt <= 0;
end
end
end
if(de_emu) hs_cnt <= 0;
end
///////////////////////// Audio output ////////////////////////////////
assign SDCD_SPDIF =(SW[3] & ~spdif) ? 1'b0 : 1'bZ;

45
sys/video_mixer.sv
View File

@ -185,41 +185,54 @@ end
wire hde = scandoubler ? ~hb_sd : ~hb_g;
wire vde = scandoubler ? ~vb_sd : ~vb_g;
reg [7:0] v_r,v_g,v_b;
reg v_vs,v_hs,v_de;
always @(posedge clk_vid) begin
reg old_hde;
if(ce_pix_out) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
VGA_R <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
VGA_G <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
VGA_B <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
v_r <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
v_g <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
v_b <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
end
2: begin // reduce 50% = 1/2
VGA_R <= {1'b0, r[7:1]};
VGA_G <= {1'b0, g[7:1]};
VGA_B <= {1'b0, b[7:1]};
v_r <= {1'b0, r[7:1]};
v_g <= {1'b0, g[7:1]};
v_b <= {1'b0, b[7:1]};
end
3: begin // reduce 75% = 1/4
VGA_R <= {2'b00, r[7:2]};
VGA_G <= {2'b00, g[7:2]};
VGA_B <= {2'b00, b[7:2]};
v_r <= {2'b00, r[7:2]};
v_g <= {2'b00, g[7:2]};
v_b <= {2'b00, b[7:2]};
end
default: begin
VGA_R <= r;
VGA_G <= g;
VGA_B <= b;
v_r <= r;
v_g <= g;
v_b <= b;
end
endcase
VGA_VS <= vs;
VGA_HS <= hs;
v_vs <= vs;
v_hs <= hs;
old_hde <= hde;
if(~old_hde && hde) VGA_DE <= vde;
if(old_hde && ~hde) VGA_DE <= 0;
if(~old_hde && hde) v_de <= vde;
if(old_hde && ~hde) v_de <= 0;
end
end
always @(posedge clk_vid) if(ce_pix_out) begin
VGA_R <= v_r;
VGA_G <= v_g;
VGA_B <= v_b;
VGA_HS <= v_hs;
VGA_VS <= v_vs;
VGA_DE <= v_de;
end
endmodule