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43
README.md
43
README.md
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@ -4,17 +4,46 @@
|
|||
|
||||
This is a classic Macintosh DB15 video out to VGA adapter. It's uses the same dip switch settings as the Sony MacView and Unimac 82D.
|
||||
|
||||
[Dip Switch Settings](/docs/manuals)
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||||
[Dip Switch Settings](docs/manuals)
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||||
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||||
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||||
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||||
The newest versions of the adapter, v1.2, come in 3 flavors now.
|
||||
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||||
**TH** is all through-hole components like v1.0. \
|
||||
**MX** has SMD diodes. The rest are through-hole components. \
|
||||
**SM** has SMD diodes and DIP switches. The rest are through-hole components.
|
||||
|
||||
|
||||
|
||||
## Bill of Materials
|
||||
|
||||
| Quantity | Designators | Product Number | Datasheet |
|
||||
| :------- | ----------- | ---------------- | ---------------------------------------------------- |
|
||||
| 1 | J1 | ID15S33E4GX00LF | [pdf](/docs/datasheets/J1_c-dd-0031-1304190.pdf) |
|
||||
| 1 | J2 | HD15-SN-24 | [pdf](/docs/datasheets/J2_hd15-sn-24-data-sheet.pdf) |
|
||||
| 2 | SWA1, SWB1 | DS04-254-1L-08BK | [pdf](/docs/datasheets/SWA1_SWB1_ds04-254.pdf) |
|
||||
### v1.0 TH and v1.2 TH
|
||||
|
||||
| Quantity | Description | Designators | Product Number | Datasheet |
|
||||
| :------- | -------------------------- | ---------------------- | ---------------- | ------------------------------------------------------------ |
|
||||
| 1 | DB15 | J1 | A-DS 15 A/KG-T4S | [pdf](docs/datasheets/J1_ASS_4888_CO.pdf) |
|
||||
| 1 | HD15 | J2 | HD15-SN-25 | [pdf](docs/datasheets/J2_hdxx-sn-25-data-sheet.pdf) |
|
||||
| 2 | Dip switch SPST 8 position | SWA1, SWB1 | DS04-254-1L-08BK | [pdf](docs/datasheets/SWA1_SWB1_ds04-254.pdf) |
|
||||
| 6 | Diode 1N4148 DO-35 | D1, D2, D3, D4, D5, D6 | 1N4148 | [pdf](docs/datasheets/D1_D2_D3_D4_D5_D6_1N914_D-2309448.pdf) |
|
||||
|
||||
### v1.2 MX
|
||||
|
||||
| Quantity | Description | Designators | Product Number | Datasheet |
|
||||
| :------- | -------------------------- | ---------------------- | ---------------- | ---------------------------------------------------- |
|
||||
| 1 | DB15 | J1 | A-DS 15 A/KG-T4S | [pdf](docs/datasheets/J1_ASS_4888_CO.pdf) |
|
||||
| 1 | HD15 | J2 | HD15-SN-25 | [pdf](docs/datasheets/J2_hdxx-sn-25-data-sheet.pdf) |
|
||||
| 2 | Dip switch SPST 8 position | SWA1, SWB1 | DS04-254-1L-08BK | [pdf](docs/datasheets/SWA1_SWB1_ds04-254.pdf) |
|
||||
| 6 | Diode 1N4148 SOD-123 | D1, D2, D3, D4, D5, D6 | 1N4148W | [pdf](docs/datasheets/D1_D2_D3_D4_D5_D6_1N4148W.pdf) |
|
||||
|
||||
### v1.2 SM
|
||||
|
||||
| Quantity | Description | Designators | Product Number | Datasheet |
|
||||
| :------- | ------------------------------ | ---------------------- | ---------------- | ---------------------------------------------------- |
|
||||
| 1 | DB15 | J1 | A-DS 15 A/KG-T4S | [pdf](docs/datasheets/J1_ASS_4888_CO.pdf) |
|
||||
| 1 | HD15 | J2 | HD15-SN-25 | [pdf](docs/datasheets/J2_hdxx-sn-25-data-sheet.pdf) |
|
||||
| 2 | Dip switch SPST 8 position SMD | SWA1, SWB1 | 219-8MST | [pdf](docs/datasheets/SWA1_SWB1_219.pdf) |
|
||||
| 6 | Diode 1N4148 SOD-123 | D1, D2, D3, D4, D5, D6 | 1N4148W | [pdf](docs/datasheets/D1_D2_D3_D4_D5_D6_1N4148W.pdf) |
|
||||
|
||||
|
||||
|
||||
|
@ -52,5 +81,5 @@ Join us in #skunkworks on [Discord](https://discord.gg/GKcvtgU7P9) to help make
|
|||
|
||||
## Special Thanks
|
||||
|
||||
[Drake](https://tinkerdifferent.com/members/drake.14/), [fehervaria](https://tinkerdifferent.com/members/fehervaria.16/)
|
||||
[Drake](https://tinkerdifferent.com/members/drake.14/), [fehervaria](https://tinkerdifferent.com/members/fehervaria.16/), [Stephen](https://tinkerdifferent.com/members/stephen.12/)
|
||||
|
||||
|
|
BIN
case/vga-adapter-base.stl
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case/vga-adapter-base.stl
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case/vga-adapter-fusion360.f3d
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case/vga-adapter-fusion360.f3d
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case/vga-adapter-lid.stl
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case/vga-adapter-lid.stl
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docs/datasheets/D1_D2_D3_D4_D5_D6_1N4148W.pdf
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docs/datasheets/D1_D2_D3_D4_D5_D6_1N4148W.pdf
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docs/datasheets/D1_D2_D3_D4_D5_D6_1N914_D-2309448.pdf
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docs/datasheets/D1_D2_D3_D4_D5_D6_1N914_D-2309448.pdf
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docs/datasheets/J1_ASS_4888_CO.pdf
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docs/datasheets/J1_ASS_4888_CO.pdf
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docs/datasheets/J2_hdxx-sn-25-data-sheet.pdf
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docs/datasheets/J2_hdxx-sn-25-data-sheet.pdf
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docs/datasheets/SWA1_SWB1_219.pdf
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docs/datasheets/SWA1_SWB1_219.pdf
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Before Width: | Height: | Size: 24 KiB After Width: | Height: | Size: 18 KiB |
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gerbers/Mac DB15 to VGA MX v1.2.zip
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gerbers/Mac DB15 to VGA MX v1.2.zip
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gerbers/Mac DB15 to VGA SM v1.2.zip
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gerbers/Mac DB15 to VGA SM v1.2.zip
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gerbers/Mac DB15 to VGA TH v1.2.zip
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gerbers/Mac DB15 to VGA TH v1.2.zip
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20203
kicad/Mac DB15 to VGA MX v1.2.kicad_pcb
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20203
kicad/Mac DB15 to VGA MX v1.2.kicad_pcb
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File diff suppressed because it is too large
Load Diff
77
kicad/Mac DB15 to VGA MX v1.2.kicad_prl
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77
kicad/Mac DB15 to VGA MX v1.2.kicad_prl
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@ -0,0 +1,77 @@
|
|||
{
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|
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"opacity": {
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|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
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|
||||
"ratsnest_display_mode": 0,
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
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|
||||
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||||
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|
||||
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|
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|
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|
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|
433
kicad/Mac DB15 to VGA MX v1.2.kicad_pro
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kicad/Mac DB15 to VGA MX v1.2.kicad_pro
Normal file
|
@ -0,0 +1,433 @@
|
|||
{
|
||||
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|
||||
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|
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|
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|
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA MX v1.2.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.127,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "Mac DB-15 to VGA TH v1.0.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"4de664de-51a8-454d-82b8-139124435893",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
1705
kicad/Mac DB15 to VGA MX v1.2.kicad_sch
Normal file
1705
kicad/Mac DB15 to VGA MX v1.2.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
18055
kicad/Mac DB15 to VGA SM v1.2.kicad_pcb
Normal file
18055
kicad/Mac DB15 to VGA SM v1.2.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
77
kicad/Mac DB15 to VGA SM v1.2.kicad_prl
Normal file
77
kicad/Mac DB15 to VGA SM v1.2.kicad_prl
Normal file
|
@ -0,0 +1,77 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"ratsnest_display_mode": 0,
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36
|
||||
],
|
||||
"visible_layers": "fffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA SM v1.2.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
433
kicad/Mac DB15 to VGA SM v1.2.kicad_pro
Normal file
433
kicad/Mac DB15 to VGA SM v1.2.kicad_pro
Normal file
|
@ -0,0 +1,433 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.127
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rule_severitieslegacy_courtyards_overlap": false,
|
||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.127,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.6,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.5
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
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|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
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|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
[
|
||||
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|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
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|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0,
|
||||
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|
||||
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|
||||
2
|
||||
],
|
||||
[
|
||||
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|
||||
2,
|
||||
1,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
0,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
[
|
||||
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|
||||
2,
|
||||
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|
||||
1,
|
||||
0,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
[
|
||||
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|
||||
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|
||||
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|
||||
1,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
[
|
||||
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|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA SM v1.2.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.127,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "Mac DB-15 to VGA TH v1.0.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"0ef8ba32-d4e8-4d2b-b6dd-ffa014de9e85",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
1705
kicad/Mac DB15 to VGA SM v1.2.kicad_sch
Normal file
1705
kicad/Mac DB15 to VGA SM v1.2.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -1,220 +0,0 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# Diode_1N4148
|
||||
#
|
||||
DEF Diode_1N4148 D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "Diode_1N4148" 0 -100 50 H V C CNN
|
||||
F2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" 0 -175 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS 1N4448 1N4149 1N4151 1N914 BA243 BA244 BA282 BA283 BAV17 BAV18 BAV19 BAV20 BAV21 BAW75 BAW76 BAY93
|
||||
$FPLIST
|
||||
D*DO?35*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 10 -50 50 -50 -50 N
|
||||
P 2 0 1 0 50 0 -50 0 N
|
||||
P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
|
||||
X K 1 -150 0 100 R 50 50 1 1 P
|
||||
X A 2 150 0 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Switch_SW_DIP_x08
|
||||
#
|
||||
DEF Switch_SW_DIP_x08 SW 0 0 Y N 1 F N
|
||||
F0 "SW" 0 550 50 H V C CNN
|
||||
F1 "Switch_SW_DIP_x08" 0 -450 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
SW?DIP?x8*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C -80 -300 20 0 0 0 N
|
||||
C -80 -200 20 0 0 0 N
|
||||
C -80 -100 20 0 0 0 N
|
||||
C -80 0 20 0 0 0 N
|
||||
C -80 100 20 0 0 0 N
|
||||
C -80 200 20 0 0 0 N
|
||||
C -80 300 20 0 0 0 N
|
||||
C -80 400 20 0 0 0 N
|
||||
C 80 -300 20 0 0 0 N
|
||||
C 80 -200 20 0 0 0 N
|
||||
C 80 -100 20 0 0 0 N
|
||||
C 80 0 20 0 0 0 N
|
||||
C 80 100 20 0 0 0 N
|
||||
C 80 200 20 0 0 0 N
|
||||
C 80 300 20 0 0 0 N
|
||||
C 80 400 20 0 0 0 N
|
||||
S -150 500 150 -400 0 1 10 f
|
||||
P 2 0 0 0 -60 -294 93 -253 N
|
||||
P 2 0 0 0 -60 -194 93 -153 N
|
||||
P 2 0 0 0 -60 -94 93 -53 N
|
||||
P 2 0 0 0 -60 5 93 46 N
|
||||
P 2 0 0 0 -60 105 93 146 N
|
||||
P 2 0 0 0 -60 205 93 246 N
|
||||
P 2 0 0 0 -60 305 93 346 N
|
||||
P 2 0 0 0 -60 405 93 446 N
|
||||
X ~ 1 -300 400 200 R 50 50 1 1 P
|
||||
X ~ 10 300 -200 200 L 50 50 1 1 P
|
||||
X ~ 11 300 -100 200 L 50 50 1 1 P
|
||||
X ~ 12 300 0 200 L 50 50 1 1 P
|
||||
X ~ 13 300 100 200 L 50 50 1 1 P
|
||||
X ~ 14 300 200 200 L 50 50 1 1 P
|
||||
X ~ 15 300 300 200 L 50 50 1 1 P
|
||||
X ~ 16 300 400 200 L 50 50 1 1 P
|
||||
X ~ 2 -300 300 200 R 50 50 1 1 P
|
||||
X ~ 3 -300 200 200 R 50 50 1 1 P
|
||||
X ~ 4 -300 100 200 R 50 50 1 1 P
|
||||
X ~ 5 -300 0 200 R 50 50 1 1 P
|
||||
X ~ 6 -300 -100 200 R 50 50 1 1 P
|
||||
X ~ 7 -300 -200 200 R 50 50 1 1 P
|
||||
X ~ 8 -300 -300 200 R 50 50 1 1 P
|
||||
X ~ 9 300 -300 200 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# project_Mac_DB15_Male_MountingHoles
|
||||
#
|
||||
DEF project_Mac_DB15_Male_MountingHoles J 0 40 Y N 1 F N
|
||||
F0 "J" 100 950 50 H V C CNN
|
||||
F1 "project_Mac_DB15_Male_MountingHoles" 100 1025 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
DSUB*Male*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C -50 -600 30 0 1 0 F
|
||||
C -50 -400 30 0 1 0 F
|
||||
C -50 -200 30 0 1 0 F
|
||||
C -50 0 30 0 1 0 F
|
||||
C -50 200 30 0 1 0 F
|
||||
C -50 400 30 0 1 0 F
|
||||
C -50 600 30 0 1 0 F
|
||||
C 70 -700 30 0 1 0 F
|
||||
C 70 -500 30 0 1 0 F
|
||||
C 70 -300 30 0 1 0 F
|
||||
C 70 -100 30 0 1 0 F
|
||||
C 70 100 30 0 1 0 F
|
||||
C 70 300 30 0 1 0 F
|
||||
C 70 500 30 0 1 0 F
|
||||
C 70 700 30 0 1 0 F
|
||||
T 0 -50 660 20 0 0 0 B Normal 0 C T
|
||||
T 0 -50 -140 20 0 0 0 B.G Normal 0 C T
|
||||
T 0 -50 260 20 0 0 0 C/V.G Normal 0 C T
|
||||
T 0 70 360 20 0 0 0 CS Normal 0 C T
|
||||
T 0 70 -40 20 0 0 0 G Normal 0 C T
|
||||
T 0 70 -240 20 0 0 0 G.G Normal 0 C T
|
||||
T 0 -50 -540 20 0 0 0 HS Normal 0 C T
|
||||
T 0 -50 -340 20 0 0 0 HS.G Normal 0 C T
|
||||
T 0 70 560 20 0 0 0 R Normal 0 C T
|
||||
T 0 70 760 20 0 0 0 R.G Normal 0 C T
|
||||
T 0 70 160 20 0 0 0 S0 Normal 0 C T
|
||||
T 0 65 -440 20 0 0 0 S1 Normal 0 C T
|
||||
T 0 -50 460 20 0 0 0 S2 Normal 0 C T
|
||||
T 0 -50 60 20 0 0 0 VS Normal 0 C T
|
||||
P 2 0 1 0 150 -700 100 -700 N
|
||||
P 2 0 1 0 150 -600 -20 -600 N
|
||||
P 2 0 1 0 150 -500 100 -500 N
|
||||
P 2 0 1 0 150 -400 -20 -400 N
|
||||
P 2 0 1 0 150 -300 100 -300 N
|
||||
P 2 0 1 0 150 -200 -20 -200 N
|
||||
P 2 0 1 0 150 -100 100 -100 N
|
||||
P 2 0 1 0 150 0 -20 0 N
|
||||
P 2 0 1 0 150 100 100 100 N
|
||||
P 2 0 1 0 150 200 -20 200 N
|
||||
P 2 0 1 0 150 300 100 300 N
|
||||
P 2 0 1 0 150 400 -20 400 N
|
||||
P 2 0 1 0 150 500 100 500 N
|
||||
P 2 0 1 0 150 600 -20 600 N
|
||||
P 2 0 1 0 150 700 100 700 N
|
||||
P 5 0 1 10 150 825 -125 675 -125 -675 150 -825 150 825 f
|
||||
X SGND 0 0 -900 150 U 50 50 1 1 P
|
||||
X RED.GND 1 300 700 150 L 50 50 1 1 P
|
||||
X SENSE2 10 300 400 150 L 50 50 1 1 O
|
||||
X CSYNC/VSYNC.GND 11 300 200 150 L 50 50 1 1 P
|
||||
X /VSYNC 12 300 0 150 L 50 50 1 1 I
|
||||
X BLU.GND 13 300 -200 150 L 50 50 1 1 P
|
||||
X HSYNC.GND 14 300 -400 150 L 50 50 1 1 P
|
||||
X /HSYNC 15 300 -600 150 L 50 50 1 1 I
|
||||
X RED.VID 2 300 500 150 L 50 50 1 1 I
|
||||
X /CSYNC 3 300 300 150 L 50 50 1 1 I
|
||||
X SENSE0 4 300 100 150 L 50 50 1 1 O
|
||||
X GRN.VID 5 300 -100 150 L 50 50 1 1 I
|
||||
X GRN.GND 6 300 -300 150 L 50 50 1 1 P
|
||||
X SENSE1 7 300 -500 150 L 50 50 1 1 O
|
||||
X 8 8 300 -700 150 L 50 50 1 1 N N
|
||||
X BLU.VID 9 300 600 150 L 50 50 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# project_VGA_DB15_Female_HighDensity_MountingHoles
|
||||
#
|
||||
DEF project_VGA_DB15_Female_HighDensity_MountingHoles J 0 40 Y N 1 F N
|
||||
F0 "J" 0 850 50 H V C CNN
|
||||
F1 "project_VGA_DB15_Female_HighDensity_MountingHoles" 0 750 50 H V C CNN
|
||||
F2 "" -950 400 50 H I C CNN
|
||||
F3 "" -950 400 50 H I C CNN
|
||||
$FPLIST
|
||||
DSUB*Female*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C -75 -400 25 0 1 0 N
|
||||
C -75 -200 25 0 1 0 N
|
||||
C -75 0 25 0 1 0 N
|
||||
C -75 200 25 0 1 0 N
|
||||
C -75 400 25 0 1 0 N
|
||||
C 0 -300 25 0 1 0 N
|
||||
C 0 -100 25 0 1 0 N
|
||||
C 0 100 25 0 1 0 N
|
||||
C 0 300 25 0 1 0 N
|
||||
C 0 500 25 0 1 0 N
|
||||
C 75 -400 25 0 1 0 N
|
||||
C 75 -200 25 0 1 0 N
|
||||
C 75 0 25 0 1 0 N
|
||||
C 75 200 25 0 1 0 N
|
||||
C 75 400 25 0 1 0 N
|
||||
T 0 -75 -50 20 0 0 0 B Normal 0 C B
|
||||
T 0 0 50 20 0 0 0 B.G Normal 0 C B
|
||||
T 0 -75 150 20 0 0 0 G Normal 0 C B
|
||||
T 0 0 250 20 0 0 0 G.G Normal 0 C B
|
||||
T 0 -75 -450 20 0 0 0 GND Normal 0 C C
|
||||
T 0 75 -50 20 0 0 0 HS Normal 0 C B
|
||||
T 0 75 350 20 0 0 0 ID0 Normal 0 C B
|
||||
T 0 75 150 20 0 0 0 ID1 Normal 0 C B
|
||||
T 0 -75 -250 20 0 0 0 ID2 Normal 0 C B
|
||||
T 0 75 -450 20 0 0 0 ID3 Normal 0 C C
|
||||
T 0 0 -150 20 0 0 0 KEY Normal 0 C B
|
||||
T 0 -75 350 20 0 0 0 R Normal 0 C B
|
||||
T 0 0 450 20 0 0 0 R.G Normal 0 C B
|
||||
T 0 0 -350 20 0 0 0 S.G Normal 0 C B
|
||||
T 0 75 -250 20 0 0 0 VS Normal 0 C B
|
||||
P 2 0 1 0 -125 300 -25 300 N
|
||||
P 2 0 1 0 -25 -300 -125 -300 N
|
||||
P 2 0 1 0 -25 -100 -125 -100 N
|
||||
P 2 0 1 0 -25 100 -125 100 N
|
||||
P 2 0 1 0 -25 500 -125 500 N
|
||||
P 5 0 1 10 -150 700 -150 -600 150 -500 150 600 -150 700 f
|
||||
X SGND 0 0 -700 150 U 50 50 1 1 P
|
||||
X RED.VID 1 -300 400 200 R 50 50 1 1 O
|
||||
X SYNC.GND 10 -300 -300 200 R 50 50 1 1 P
|
||||
X ID0 11 300 400 200 L 50 50 1 1 I
|
||||
X ID1 12 300 200 200 L 50 50 1 1 I
|
||||
X /HSYNC 13 300 0 200 L 50 50 1 1 O
|
||||
X /VSYNC 14 300 -200 200 L 50 50 1 1 O
|
||||
X ID3 15 300 -400 200 L 50 50 1 1 I
|
||||
X GRN.VID 2 -300 200 200 R 50 50 1 1 O
|
||||
X BLU.VID 3 -300 0 200 R 50 50 1 1 O
|
||||
X ID2/RES 4 -300 -200 200 R 50 50 1 1 I
|
||||
X GND 5 -300 -400 200 R 50 50 1 1 P
|
||||
X RED.GND 6 -300 500 200 R 50 50 1 1 P
|
||||
X GRN.GND 7 -300 300 200 R 50 50 1 1 P
|
||||
X BLU.GND 8 -300 100 200 R 50 50 1 1 P
|
||||
X KEY 9 -300 -100 200 R 50 50 1 1 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
|
@ -1,15 +0,0 @@
|
|||
EESchema-DOCLIB Version 2.0
|
||||
#
|
||||
$CMP Mac_DB15_Male_MountingHoles
|
||||
D 15-pin male D-SUB connector (low-density/2 columns), Mounting Hole
|
||||
K male D-SUB connector
|
||||
F ~
|
||||
$ENDCMP
|
||||
#
|
||||
$CMP VGA_DB15_Female_HighDensity_MountingHoles
|
||||
D 15-pin female D-SUB connector, High density (3 columns), Triple Row, Generic, VGA-connector, Mounting Hole
|
||||
K connector db15 female D-SUB VGA
|
||||
F ~
|
||||
$ENDCMP
|
||||
#
|
||||
#End Doc Library
|
File diff suppressed because it is too large
Load Diff
77
kicad/Mac DB15 to VGA TH v1.0.kicad_prl
Normal file
77
kicad/Mac DB15 to VGA TH v1.0.kicad_prl
Normal file
|
@ -0,0 +1,77 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"ratsnest_display_mode": 0,
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36
|
||||
],
|
||||
"visible_layers": "fffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA TH v1.0.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
440
kicad/Mac DB15 to VGA TH v1.0.kicad_pro
Normal file
440
kicad/Mac DB15 to VGA TH v1.0.kicad_pro
Normal file
|
@ -0,0 +1,440 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.254
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [
|
||||
"courtyards_overlap|115590001|106392001|00000000-0000-0000-0000-0000619533b2|00000000-0000-0000-0000-000061953672",
|
||||
"courtyards_overlap|118785949|106392001|00000000-0000-0000-0000-0000619533b2|00000000-0000-0000-0000-000061953618",
|
||||
"courtyards_overlap|127782001|106392001|00000000-0000-0000-0000-00006195532d|00000000-0000-0000-0000-000061955086",
|
||||
"courtyards_overlap|127782001|93692001|00000000-0000-0000-0000-00006195532d|00000000-0000-0000-0000-0000619550c4",
|
||||
"courtyards_overlap|130322001|93692001|00000000-0000-0000-0000-00006195532d|00000000-0000-0000-0000-0000619550e3",
|
||||
"courtyards_overlap|130977949|106392001|00000000-0000-0000-0000-00006195532d|00000000-0000-0000-0000-0000619550a5"
|
||||
],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rule_severitieslegacy_courtyards_overlap": true,
|
||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.19999999999999998,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.39999999999999997,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.5
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA TH v1.0.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.2,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.25,
|
||||
"via_diameter": 0.8,
|
||||
"via_drill": 0.4,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "Mac DB-15 to VGA TH v1.0.net",
|
||||
"specctra_dsn": "",
|
||||
"step": "",
|
||||
"vrml": ""
|
||||
},
|
||||
"page_layout_descr_file": ""
|
||||
},
|
||||
"schematic": {
|
||||
"annotate_start_num": 0,
|
||||
"drawing": {
|
||||
"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
|
||||
"field_names": [],
|
||||
"intersheets_ref_own_page": false,
|
||||
"intersheets_ref_prefix": "",
|
||||
"intersheets_ref_short": false,
|
||||
"intersheets_ref_show": false,
|
||||
"intersheets_ref_suffix": "",
|
||||
"junction_size_choice": 3,
|
||||
"label_size_ratio": 0.25,
|
||||
"pin_symbol_size": 0.0,
|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"7f353085-cee5-40c7-a500-d14ad2361ace",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
1719
kicad/Mac DB15 to VGA TH v1.0.kicad_sch
Normal file
1719
kicad/Mac DB15 to VGA TH v1.0.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -1,251 +0,0 @@
|
|||
update=11/17/2021 10:32:34 PM
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=Mac DB-15 to VGA TH v1.0.net
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.5
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
ViaDiameter2=0.6
|
||||
ViaDrill2=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.05
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
|
@ -1,433 +0,0 @@
|
|||
EESchema Schematic File Version 4
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
Sheet 1 1
|
||||
Title ""
|
||||
Date ""
|
||||
Rev ""
|
||||
Comp ""
|
||||
Comment1 ""
|
||||
Comment2 ""
|
||||
Comment3 ""
|
||||
Comment4 ""
|
||||
$EndDescr
|
||||
$Comp
|
||||
L Diode:1N4148 D2
|
||||
U 1 1 61588880
|
||||
P 4750 4800
|
||||
F 0 "D2" H 4750 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4926 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 4750 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4800 50 0001 C CNN
|
||||
1 4750 4800
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
3750 4350 4050 4350
|
||||
Wire Wire Line
|
||||
4900 4450 5200 4450
|
||||
Wire Wire Line
|
||||
4900 4800 5200 4800
|
||||
Text Label 4950 4450 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 4950 4800 0 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
4600 4800 4300 4800
|
||||
Wire Wire Line
|
||||
4600 4450 4300 4450
|
||||
Text Label 5650 4050 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
5550 4250 5550 4150
|
||||
Text Label 5650 4250 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 9100 5050 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
9350 4400 9050 4400
|
||||
Wire Wire Line
|
||||
8900 3400 8900 3600
|
||||
Wire Wire Line
|
||||
9950 3700 10250 3700
|
||||
Connection ~ 8900 4500
|
||||
Wire Wire Line
|
||||
8900 5050 8900 4500
|
||||
Wire Wire Line
|
||||
8900 4500 8900 4300
|
||||
Wire Wire Line
|
||||
9350 4500 8900 4500
|
||||
Connection ~ 8900 4300
|
||||
Connection ~ 8900 3600
|
||||
Connection ~ 8900 4000
|
||||
Wire Wire Line
|
||||
8900 4300 8900 4000
|
||||
Wire Wire Line
|
||||
8900 5050 9650 5050
|
||||
Wire Wire Line
|
||||
8900 4300 9350 4300
|
||||
Wire Wire Line
|
||||
9650 4800 9650 5050
|
||||
Wire Wire Line
|
||||
9350 3600 8900 3600
|
||||
Wire Wire Line
|
||||
9050 3700 9350 3700
|
||||
Wire Wire Line
|
||||
8900 3800 9350 3800
|
||||
Wire Wire Line
|
||||
8900 4000 9350 4000
|
||||
Wire Wire Line
|
||||
8900 3800 8900 4000
|
||||
Connection ~ 8900 3800
|
||||
Wire Wire Line
|
||||
8900 3600 8900 3800
|
||||
NoConn ~ 9350 4200
|
||||
NoConn ~ 9950 4500
|
||||
NoConn ~ 9950 3900
|
||||
Text Label 2150 3700 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 2150 4600 0 50 ~ 0
|
||||
S1-1
|
||||
Text Label 2150 4000 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 2150 3800 0 50 ~ 0
|
||||
CS
|
||||
Text Label 2150 3600 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
7550 4450 7200 4450
|
||||
Wire Wire Line
|
||||
7550 4800 7200 4800
|
||||
Text Label 7950 4800 0 50 ~ 0
|
||||
S2-1
|
||||
Text Label 7950 4450 0 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
7850 4800 8200 4800
|
||||
Wire Wire Line
|
||||
7850 4450 8200 4450
|
||||
$Comp
|
||||
L Diode:1N4148 D3
|
||||
U 1 1 615851AF
|
||||
P 7700 4450
|
||||
F 0 "D3" H 7700 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4576 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4450 50 0001 C CNN
|
||||
1 7700 4450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2100 4600 2400 4600
|
||||
Wire Wire Line
|
||||
2100 4000 2400 4000
|
||||
Wire Wire Line
|
||||
2100 3800 2400 3800
|
||||
Wire Wire Line
|
||||
2100 3600 2400 3600
|
||||
Wire Wire Line
|
||||
2100 4700 2400 4700
|
||||
Wire Wire Line
|
||||
2100 4500 2400 4500
|
||||
Wire Wire Line
|
||||
2100 3900 2400 3900
|
||||
Wire Wire Line
|
||||
2100 3700 2400 3700
|
||||
Wire Wire Line
|
||||
1800 5050 1800 5000
|
||||
Connection ~ 8900 5050
|
||||
Wire Wire Line
|
||||
8900 5050 1800 5050
|
||||
Text Label 7950 4050 0 50 ~ 0
|
||||
S0-1
|
||||
Text Label 7950 3700 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
7850 4050 8200 4050
|
||||
Wire Wire Line
|
||||
7850 3700 8200 3700
|
||||
$Comp
|
||||
L Diode:1N4148 D5
|
||||
U 1 1 61587AEA
|
||||
P 7700 3700
|
||||
F 0 "D5" H 7700 3917 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 3826 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 3525 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 3700 50 0001 C CNN
|
||||
1 7700 3700
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D6
|
||||
U 1 1 615862A9
|
||||
P 7700 4050
|
||||
F 0 "D6" H 7700 4267 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4176 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 3875 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4050 50 0001 C CNN
|
||||
1 7700 4050
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L Diode:1N4148 D4
|
||||
U 1 1 6158496F
|
||||
P 7700 4800
|
||||
F 0 "D4" H 7700 5017 50 0000 C CNN
|
||||
F 1 "1N4148" H 7700 4926 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 7700 4625 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 7700 4800 50 0001 C CNN
|
||||
1 7700 4800
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
2800 4350 3150 4350
|
||||
Text Label 3100 4350 2 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
2800 4450 3150 4450
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4450
|
||||
Wire Wire Line
|
||||
4050 4450 3750 4450
|
||||
Connection ~ 4050 4350
|
||||
Wire Wire Line
|
||||
4050 4350 4050 4250
|
||||
Connection ~ 4050 4250
|
||||
Wire Wire Line
|
||||
4050 4250 3750 4250
|
||||
Wire Wire Line
|
||||
4050 4250 4050 4150
|
||||
Wire Wire Line
|
||||
4050 4150 3750 4150
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWA1
|
||||
U 1 1 61528095
|
||||
P 3450 4050
|
||||
F 0 "SWA1" H 3450 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 3450 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 3450 4050 50 0001 C CNN
|
||||
F 3 "~" H 3450 4050 50 0001 C CNN
|
||||
1 3450 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Text Label 9100 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4300 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3600 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 3800 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4000 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 4300 2400 4300
|
||||
Text Label 2150 3400 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:Mac_DB15_Male_MountingHoles J1
|
||||
U 1 1 6154A803
|
||||
P 1800 4100
|
||||
F 0 "J1" H 1894 5092 50 0000 C CNN
|
||||
F 1 "Mac_DB15_Male_MountingHoles" H 1894 5001 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15_Male_Horizontal_P2.77x2.84mm_EdgePinOffset7.70mm_Housed_MountingHolesOffset9.12mm" H 1800 4100 50 0001 C CNN
|
||||
F 3 " ~" H 1800 4100 50 0001 C CNN
|
||||
1 1800 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 2150 4300 0 50 ~ 0
|
||||
GND
|
||||
$Comp
|
||||
L project:VGA_DB15_Female_HighDensity_MountingHoles J2
|
||||
U 1 1 6151FC86
|
||||
P 9650 4100
|
||||
F 0 "J2" H 9650 4967 50 0000 C CNN
|
||||
F 1 "VGA_DB15_Female_HighDensity_MountingHoles" H 9650 4876 50 0000 C CNN
|
||||
F 2 "Connector_Dsub:DSUB-15-HD_Female_Horizontal_P2.29x1.98mm_EdgePinOffset3.03mm_Housed_MountingHolesOffset4.94mm" H 8700 4500 50 0001 C CNN
|
||||
F 3 " ~" H 8700 4500 50 0001 C CNN
|
||||
1 9650 4100
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 9100 3700 0 50 ~ 0
|
||||
R
|
||||
Wire Wire Line
|
||||
5900 4050 5550 4050
|
||||
Text Label 10000 3700 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 3900 0 50 ~ 0
|
||||
GND
|
||||
Text Label 9100 4400 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4500 0 50 ~ 0
|
||||
GND
|
||||
Text Label 2150 4200 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
9350 3900 9050 3900
|
||||
Text Label 9100 3900 0 50 ~ 0
|
||||
G
|
||||
Wire Wire Line
|
||||
2100 4400 2400 4400
|
||||
Text Label 2150 4400 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3500 2400 3500
|
||||
Text Label 2150 3500 0 50 ~ 0
|
||||
B
|
||||
Wire Wire Line
|
||||
9350 4100 9050 4100
|
||||
Text Label 9100 4100 0 50 ~ 0
|
||||
B
|
||||
$Comp
|
||||
L Diode:1N4148 D1
|
||||
U 1 1 61582C6F
|
||||
P 4750 4450
|
||||
F 0 "D1" H 4750 4667 50 0000 C CNN
|
||||
F 1 "1N4148" H 4750 4576 50 0000 C CNN
|
||||
F 2 "Diode_THT:D_DO-35_SOD27_P7.62mm_Horizontal" H 4750 4275 50 0001 C CNN
|
||||
F 3 "https://assets.nexperia.com/documents/data-sheet/1N4148_1N4448.pdf" H 4750 4450 50 0001 C CNN
|
||||
1 4750 4450
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text Label 3100 4150 2 50 ~ 0
|
||||
S2-1
|
||||
Wire Wire Line
|
||||
2800 4150 3150 4150
|
||||
Text Label 3100 4250 2 50 ~ 0
|
||||
S1-1
|
||||
Wire Wire Line
|
||||
2800 4250 3150 4250
|
||||
Wire Wire Line
|
||||
2800 4050 3150 4050
|
||||
Wire Wire Line
|
||||
5900 3950 5550 3950
|
||||
Wire Wire Line
|
||||
5550 3950 5550 4050
|
||||
Wire Wire Line
|
||||
2100 4100 2400 4100
|
||||
Text Label 2150 4100 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4050 0 50 ~ 0
|
||||
VS
|
||||
Text Label 2900 4450 0 50 ~ 0
|
||||
GND
|
||||
Wire Wire Line
|
||||
2100 3400 8900 3400
|
||||
Wire Wire Line
|
||||
5550 3850 5900 3850
|
||||
Text Label 5650 3850 0 50 ~ 0
|
||||
CS
|
||||
Text Label 5650 4450 0 50 ~ 0
|
||||
S0-1
|
||||
Wire Wire Line
|
||||
5550 4450 5900 4450
|
||||
Wire Wire Line
|
||||
5550 4350 5900 4350
|
||||
Wire Wire Line
|
||||
5550 4350 5550 4450
|
||||
Wire Wire Line
|
||||
8200 3700 8200 4050
|
||||
Wire Wire Line
|
||||
8200 4450 8200 4800
|
||||
Wire Wire Line
|
||||
2100 4200 2400 4200
|
||||
Wire Wire Line
|
||||
5200 4450 5200 4800
|
||||
Wire Wire Line
|
||||
5900 4250 5550 4250
|
||||
Wire Wire Line
|
||||
5550 4150 5900 4150
|
||||
Text Label 2150 4700 0 50 ~ 0
|
||||
HS
|
||||
$Comp
|
||||
L Switch:SW_DIP_x08 SWB1
|
||||
U 1 1 6152990A
|
||||
P 6200 4050
|
||||
F 0 "SWB1" H 6200 4717 50 0000 C CNN
|
||||
F 1 "SW_DIP_x08" H 6200 4626 50 0000 C CNN
|
||||
F 2 "project:SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" H 6200 4050 50 0001 C CNN
|
||||
F 3 "~" H 6200 4050 50 0001 C CNN
|
||||
1 6200 4050
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Wire Wire Line
|
||||
5900 3750 5550 3750
|
||||
Text Label 5650 3750 0 50 ~ 0
|
||||
HS
|
||||
NoConn ~ 3750 3950
|
||||
NoConn ~ 3750 3850
|
||||
NoConn ~ 3750 3750
|
||||
NoConn ~ 3150 3750
|
||||
NoConn ~ 3150 3850
|
||||
NoConn ~ 3150 3950
|
||||
Wire Wire Line
|
||||
6500 3750 6900 3750
|
||||
Wire Wire Line
|
||||
9950 4100 10250 4100
|
||||
Text Label 10000 4100 0 50 ~ 0
|
||||
HS-CS
|
||||
Wire Wire Line
|
||||
3750 4050 4050 4050
|
||||
Text Label 3800 4050 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
9950 4300 10250 4300
|
||||
Text Label 10000 4300 0 50 ~ 0
|
||||
VS-2
|
||||
Wire Wire Line
|
||||
6500 4450 6900 4450
|
||||
Wire Wire Line
|
||||
6500 4350 6900 4350
|
||||
Text Label 4450 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 4450 4800 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4350 0 50 ~ 0
|
||||
D2
|
||||
Text Label 6600 4450 0 50 ~ 0
|
||||
D1
|
||||
Text Label 7350 4800 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
6500 4250 6900 4250
|
||||
Text Label 6600 4250 0 50 ~ 0
|
||||
D4
|
||||
Wire Wire Line
|
||||
7550 3700 7200 3700
|
||||
Wire Wire Line
|
||||
7550 4050 7200 4050
|
||||
Wire Wire Line
|
||||
6500 4150 6900 4150
|
||||
Text Label 6600 4150 0 50 ~ 0
|
||||
D3
|
||||
Text Label 7350 4450 0 50 ~ 0
|
||||
D3
|
||||
Wire Wire Line
|
||||
6500 4050 6900 4050
|
||||
Wire Wire Line
|
||||
6500 3950 6900 3950
|
||||
Text Label 6600 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 4050 0 50 ~ 0
|
||||
D6
|
||||
Text Label 7350 3700 0 50 ~ 0
|
||||
D5
|
||||
Wire Wire Line
|
||||
6500 3850 6900 3850
|
||||
Wire Wire Line
|
||||
6900 3850 6900 3750
|
||||
Text Label 6600 3950 0 50 ~ 0
|
||||
D5
|
||||
Text Label 6600 3850 0 50 ~ 0
|
||||
HS-CS
|
||||
Text Notes 7050 6700 0 50 ~ 0
|
||||
Sony MacView / Unimac 82D Schematics
|
||||
Text Notes 7050 6800 0 50 ~ 0
|
||||
CC BY-NC-SA 4.0
|
||||
Text Notes 7400 7500 0 50 ~ 0
|
||||
DB-15 to VGA TH v1.0
|
||||
Text Notes 8150 7650 0 50 ~ 0
|
||||
November 18, 2021
|
||||
$EndSCHEMATC
|
11009
kicad/Mac DB15 to VGA TH v1.1.kicad_pcb
Normal file
11009
kicad/Mac DB15 to VGA TH v1.1.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
77
kicad/Mac DB15 to VGA TH v1.1.kicad_prl
Normal file
77
kicad/Mac DB15 to VGA TH v1.1.kicad_prl
Normal file
|
@ -0,0 +1,77 @@
|
|||
{
|
||||
"board": {
|
||||
"active_layer": 0,
|
||||
"active_layer_preset": "",
|
||||
"auto_track_width": true,
|
||||
"hidden_nets": [],
|
||||
"high_contrast_mode": 0,
|
||||
"net_color_mode": 1,
|
||||
"opacity": {
|
||||
"pads": 1.0,
|
||||
"tracks": 1.0,
|
||||
"vias": 1.0,
|
||||
"zones": 0.6
|
||||
},
|
||||
"ratsnest_display_mode": 0,
|
||||
"selection_filter": {
|
||||
"dimensions": true,
|
||||
"footprints": true,
|
||||
"graphics": true,
|
||||
"keepouts": true,
|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
"pads": true,
|
||||
"text": true,
|
||||
"tracks": true,
|
||||
"vias": true,
|
||||
"zones": true
|
||||
},
|
||||
"visible_items": [
|
||||
0,
|
||||
1,
|
||||
2,
|
||||
3,
|
||||
4,
|
||||
5,
|
||||
6,
|
||||
7,
|
||||
8,
|
||||
9,
|
||||
10,
|
||||
11,
|
||||
12,
|
||||
13,
|
||||
14,
|
||||
15,
|
||||
16,
|
||||
17,
|
||||
18,
|
||||
19,
|
||||
20,
|
||||
21,
|
||||
22,
|
||||
23,
|
||||
24,
|
||||
25,
|
||||
26,
|
||||
27,
|
||||
28,
|
||||
29,
|
||||
30,
|
||||
32,
|
||||
33,
|
||||
34,
|
||||
35,
|
||||
36
|
||||
],
|
||||
"visible_layers": "fffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA TH v1.1.kicad_prl",
|
||||
"version": 3
|
||||
},
|
||||
"project": {
|
||||
"files": []
|
||||
}
|
||||
}
|
433
kicad/Mac DB15 to VGA TH v1.1.kicad_pro
Normal file
433
kicad/Mac DB15 to VGA TH v1.1.kicad_pro
Normal file
|
@ -0,0 +1,433 @@
|
|||
{
|
||||
"board": {
|
||||
"design_settings": {
|
||||
"defaults": {
|
||||
"board_outline_line_width": 0.049999999999999996,
|
||||
"copper_line_width": 0.19999999999999998,
|
||||
"copper_text_italic": false,
|
||||
"copper_text_size_h": 1.5,
|
||||
"copper_text_size_v": 1.5,
|
||||
"copper_text_thickness": 0.3,
|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
"arrow_length": 1270000,
|
||||
"extension_offset": 500000,
|
||||
"keep_text_aligned": true,
|
||||
"suppress_zeroes": false,
|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
"fab_text_italic": false,
|
||||
"fab_text_size_h": 1.0,
|
||||
"fab_text_size_v": 1.0,
|
||||
"fab_text_thickness": 0.15,
|
||||
"fab_text_upright": false,
|
||||
"other_line_width": 0.09999999999999999,
|
||||
"other_text_italic": false,
|
||||
"other_text_size_h": 1.0,
|
||||
"other_text_size_v": 1.0,
|
||||
"other_text_thickness": 0.15,
|
||||
"other_text_upright": false,
|
||||
"pads": {
|
||||
"drill": 0.762,
|
||||
"height": 1.524,
|
||||
"width": 1.524
|
||||
},
|
||||
"silk_line_width": 0.12,
|
||||
"silk_text_italic": false,
|
||||
"silk_text_size_h": 1.0,
|
||||
"silk_text_size_v": 1.0,
|
||||
"silk_text_thickness": 0.15,
|
||||
"silk_text_upright": false,
|
||||
"zones": {
|
||||
"45_degree_only": false,
|
||||
"min_clearance": 0.127
|
||||
}
|
||||
},
|
||||
"diff_pair_dimensions": [],
|
||||
"drc_exclusions": [],
|
||||
"meta": {
|
||||
"filename": "board_design_settings.json",
|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
"annular_width": "error",
|
||||
"clearance": "error",
|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
"diff_pair_uncoupled_length_too_long": "error",
|
||||
"drill_out_of_range": "error",
|
||||
"duplicate_footprints": "warning",
|
||||
"extra_footprint": "warning",
|
||||
"footprint_type_mismatch": "error",
|
||||
"hole_clearance": "error",
|
||||
"hole_near_hole": "error",
|
||||
"invalid_outline": "error",
|
||||
"item_on_disabled_layer": "error",
|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
"malformed_courtyard": "error",
|
||||
"microvia_drill_out_of_range": "error",
|
||||
"missing_courtyard": "ignore",
|
||||
"missing_footprint": "warning",
|
||||
"net_conflict": "warning",
|
||||
"npth_inside_courtyard": "ignore",
|
||||
"padstack": "error",
|
||||
"pth_inside_courtyard": "ignore",
|
||||
"shorting_items": "error",
|
||||
"silk_over_copper": "warning",
|
||||
"silk_overlap": "warning",
|
||||
"skew_out_of_range": "error",
|
||||
"through_hole_pad_without_hole": "error",
|
||||
"too_many_vias": "error",
|
||||
"track_dangling": "warning",
|
||||
"track_width": "error",
|
||||
"tracks_crossing": "error",
|
||||
"unconnected_items": "error",
|
||||
"unresolved_variable": "error",
|
||||
"via_dangling": "warning",
|
||||
"zone_has_empty_net": "error",
|
||||
"zones_intersect": "error"
|
||||
},
|
||||
"rule_severitieslegacy_courtyards_overlap": false,
|
||||
"rule_severitieslegacy_no_courtyard_defined": false,
|
||||
"rules": {
|
||||
"allow_blind_buried_vias": false,
|
||||
"allow_microvias": false,
|
||||
"max_error": 0.005,
|
||||
"min_clearance": 0.0,
|
||||
"min_copper_edge_clearance": 0.024999999999999998,
|
||||
"min_hole_clearance": 0.25,
|
||||
"min_hole_to_hole": 0.25,
|
||||
"min_microvia_diameter": 0.19999999999999998,
|
||||
"min_microvia_drill": 0.09999999999999999,
|
||||
"min_silk_clearance": 0.0,
|
||||
"min_through_hole_diameter": 0.3,
|
||||
"min_track_width": 0.127,
|
||||
"min_via_annular_width": 0.049999999999999996,
|
||||
"min_via_diameter": 0.6,
|
||||
"use_height_for_length_calcs": true
|
||||
},
|
||||
"track_widths": [
|
||||
0.0,
|
||||
0.5
|
||||
],
|
||||
"via_dimensions": [
|
||||
{
|
||||
"diameter": 0.0,
|
||||
"drill": 0.0
|
||||
},
|
||||
{
|
||||
"diameter": 0.6,
|
||||
"drill": 0.3
|
||||
}
|
||||
],
|
||||
"zones_allow_external_fillets": false,
|
||||
"zones_use_no_outline": true
|
||||
},
|
||||
"layer_presets": []
|
||||
},
|
||||
"boards": [],
|
||||
"cvpcb": {
|
||||
"equivalence_files": []
|
||||
},
|
||||
"erc": {
|
||||
"erc_exclusions": [],
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"pin_map": [
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
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|
||||
0,
|
||||
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|
||||
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|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
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||||
[
|
||||
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|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
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||||
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||||
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||||
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||||
[
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||||
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|
||||
1,
|
||||
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|
||||
1,
|
||||
1,
|
||||
0,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
1,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
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|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
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|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
],
|
||||
[
|
||||
0,
|
||||
2,
|
||||
1,
|
||||
1,
|
||||
0,
|
||||
0,
|
||||
1,
|
||||
0,
|
||||
2,
|
||||
0,
|
||||
0,
|
||||
2
|
||||
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|
||||
[
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2,
|
||||
2
|
||||
]
|
||||
],
|
||||
"rule_severities": {
|
||||
"bus_definition_conflict": "error",
|
||||
"bus_entry_needed": "error",
|
||||
"bus_label_syntax": "error",
|
||||
"bus_to_bus_conflict": "error",
|
||||
"bus_to_net_conflict": "error",
|
||||
"different_unit_footprint": "error",
|
||||
"different_unit_net": "error",
|
||||
"duplicate_reference": "error",
|
||||
"duplicate_sheet_names": "error",
|
||||
"extra_units": "error",
|
||||
"global_label_dangling": "warning",
|
||||
"hier_label_mismatch": "error",
|
||||
"label_dangling": "error",
|
||||
"lib_symbol_issues": "warning",
|
||||
"multiple_net_names": "warning",
|
||||
"net_not_bus_member": "warning",
|
||||
"no_connect_connected": "warning",
|
||||
"no_connect_dangling": "warning",
|
||||
"pin_not_connected": "error",
|
||||
"pin_not_driven": "error",
|
||||
"pin_to_pin": "warning",
|
||||
"power_pin_not_driven": "error",
|
||||
"similar_labels": "warning",
|
||||
"unannotated": "error",
|
||||
"unit_value_mismatch": "error",
|
||||
"unresolved_variable": "error",
|
||||
"wire_dangling": "error"
|
||||
}
|
||||
},
|
||||
"libraries": {
|
||||
"pinned_footprint_libs": [],
|
||||
"pinned_symbol_libs": []
|
||||
},
|
||||
"meta": {
|
||||
"filename": "Mac DB15 to VGA TH v1.1.kicad_pro",
|
||||
"version": 1
|
||||
},
|
||||
"net_settings": {
|
||||
"classes": [
|
||||
{
|
||||
"bus_width": 12.0,
|
||||
"clearance": 0.127,
|
||||
"diff_pair_gap": 0.25,
|
||||
"diff_pair_via_gap": 0.25,
|
||||
"diff_pair_width": 0.2,
|
||||
"line_style": 0,
|
||||
"microvia_diameter": 0.3,
|
||||
"microvia_drill": 0.1,
|
||||
"name": "Default",
|
||||
"pcb_color": "rgba(0, 0, 0, 0.000)",
|
||||
"schematic_color": "rgba(0, 0, 0, 0.000)",
|
||||
"track_width": 0.127,
|
||||
"via_diameter": 0.6,
|
||||
"via_drill": 0.3,
|
||||
"wire_width": 6.0
|
||||
}
|
||||
],
|
||||
"meta": {
|
||||
"version": 2
|
||||
},
|
||||
"net_colors": null
|
||||
},
|
||||
"pcbnew": {
|
||||
"last_paths": {
|
||||
"gencad": "",
|
||||
"idf": "",
|
||||
"netlist": "Mac DB-15 to VGA TH v1.0.net",
|
||||
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|
||||
"step": "",
|
||||
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|
||||
},
|
||||
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|
||||
},
|
||||
"schematic": {
|
||||
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|
||||
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|
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"default_line_thickness": 6.0,
|
||||
"default_text_size": 50.0,
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|
||||
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|
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|
||||
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|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
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||||
"fix_include_paths": true,
|
||||
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|
||||
"meta": {
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|
||||
"spice_adjust_passive_values": false,
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||||
"spice_external_command": "spice \"%I\"",
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"subpart_first_id": 65,
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"sheets": [
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|
1705
kicad/Mac DB15 to VGA TH v1.1.kicad_sch
Normal file
1705
kicad/Mac DB15 to VGA TH v1.1.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
20569
kicad/Mac DB15 to VGA TH v1.2.kicad_pcb
Normal file
20569
kicad/Mac DB15 to VGA TH v1.2.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
77
kicad/Mac DB15 to VGA TH v1.2.kicad_prl
Normal file
77
kicad/Mac DB15 to VGA TH v1.2.kicad_prl
Normal file
|
@ -0,0 +1,77 @@
|
|||
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|
||||
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|
||||
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"vias": 1.0,
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||||
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||||
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|
||||
"lockedItems": true,
|
||||
"otherItems": true,
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
"visible_layers": "fffffff_ffffffff",
|
||||
"zone_display_mode": 0
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
}
|
||||
}
|
435
kicad/Mac DB15 to VGA TH v1.2.kicad_pro
Normal file
435
kicad/Mac DB15 to VGA TH v1.2.kicad_pro
Normal file
|
@ -0,0 +1,435 @@
|
|||
{
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"copper_text_size_h": 1.5,
|
||||
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|
||||
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|
||||
"copper_text_upright": false,
|
||||
"courtyard_line_width": 0.049999999999999996,
|
||||
"dimension_precision": 4,
|
||||
"dimension_units": 3,
|
||||
"dimensions": {
|
||||
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|
||||
"extension_offset": 500000,
|
||||
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|
||||
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|
||||
"text_position": 0,
|
||||
"units_format": 1
|
||||
},
|
||||
"fab_line_width": 0.09999999999999999,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
}
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
],
|
||||
"meta": {
|
||||
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|
||||
"version": 2
|
||||
},
|
||||
"rule_severities": {
|
||||
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|
||||
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|
||||
"copper_edge_clearance": "error",
|
||||
"courtyards_overlap": "error",
|
||||
"diff_pair_gap_out_of_range": "error",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"items_not_allowed": "error",
|
||||
"length_out_of_range": "error",
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"text_offset_ratio": 0.08
|
||||
},
|
||||
"legacy_lib_dir": "",
|
||||
"legacy_lib_list": [],
|
||||
"meta": {
|
||||
"version": 1
|
||||
},
|
||||
"net_format_name": "Pcbnew",
|
||||
"ngspice": {
|
||||
"fix_include_paths": true,
|
||||
"fix_passive_vals": false,
|
||||
"meta": {
|
||||
"version": 0
|
||||
},
|
||||
"model_mode": 0,
|
||||
"workbook_filename": ""
|
||||
},
|
||||
"page_layout_descr_file": "",
|
||||
"plot_directory": "",
|
||||
"spice_adjust_passive_values": false,
|
||||
"spice_external_command": "spice \"%I\"",
|
||||
"subpart_first_id": 65,
|
||||
"subpart_id_separator": 0
|
||||
},
|
||||
"sheets": [
|
||||
[
|
||||
"ddf22df6-5864-443b-8c42-4910cb155b55",
|
||||
""
|
||||
]
|
||||
],
|
||||
"text_variables": {}
|
||||
}
|
1705
kicad/Mac DB15 to VGA TH v1.2.kicad_sch
Normal file
1705
kicad/Mac DB15 to VGA TH v1.2.kicad_sch
Normal file
File diff suppressed because it is too large
Load Diff
|
@ -1,4 +1,3 @@
|
|||
(fp_lib_table
|
||||
(lib (name project)(type KiCad)(uri ${KIPRJMOD}/project.pretty)(options "")(descr ""))
|
||||
(lib (name snapeda)(type KiCad)(uri ${KIPRJMOD}/snapeda.pretty)(options "")(descr ""))
|
||||
(lib (name "project")(type "KiCad")(uri "${KIPRJMOD}/project.pretty")(options "")(descr ""))
|
||||
)
|
||||
|
|
|
@ -1,173 +0,0 @@
|
|||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# Mac_DB15_Male_MountingHoles
|
||||
#
|
||||
DEF Mac_DB15_Male_MountingHoles J 0 40 Y N 1 F N
|
||||
F0 "J" 100 950 50 H V C CNN
|
||||
F1 "Mac_DB15_Male_MountingHoles" 100 1025 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
DSUB*Male*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C -50 -600 30 0 1 0 F
|
||||
C -50 -400 30 0 1 0 F
|
||||
C -50 -200 30 0 1 0 F
|
||||
C -50 0 30 0 1 0 F
|
||||
C -50 200 30 0 1 0 F
|
||||
C -50 400 30 0 1 0 F
|
||||
C -50 600 30 0 1 0 F
|
||||
C 70 -700 30 0 1 0 F
|
||||
C 70 -500 30 0 1 0 F
|
||||
C 70 -300 30 0 1 0 F
|
||||
C 70 -100 30 0 1 0 F
|
||||
C 70 100 30 0 1 0 F
|
||||
C 70 300 30 0 1 0 F
|
||||
C 70 500 30 0 1 0 F
|
||||
C 70 700 30 0 1 0 F
|
||||
T 0 -50 660 20 0 0 0 B Normal 0 C T
|
||||
T 0 -50 -140 20 0 0 0 B.G Normal 0 C T
|
||||
T 0 -50 260 20 0 0 0 C/V.G Normal 0 C T
|
||||
T 0 70 360 20 0 0 0 CS Normal 0 C T
|
||||
T 0 70 -40 20 0 0 0 G Normal 0 C T
|
||||
T 0 70 -240 20 0 0 0 G.G Normal 0 C T
|
||||
T 0 -50 -540 20 0 0 0 HS Normal 0 C T
|
||||
T 0 -50 -340 20 0 0 0 HS.G Normal 0 C T
|
||||
T 0 70 560 20 0 0 0 R Normal 0 C T
|
||||
T 0 70 760 20 0 0 0 R.G Normal 0 C T
|
||||
T 0 70 160 20 0 0 0 S0 Normal 0 C T
|
||||
T 0 65 -440 20 0 0 0 S1 Normal 0 C T
|
||||
T 0 -50 460 20 0 0 0 S2 Normal 0 C T
|
||||
T 0 -50 60 20 0 0 0 VS Normal 0 C T
|
||||
P 2 0 1 0 150 -700 100 -700 N
|
||||
P 2 0 1 0 150 -600 -20 -600 N
|
||||
P 2 0 1 0 150 -500 100 -500 N
|
||||
P 2 0 1 0 150 -400 -20 -400 N
|
||||
P 2 0 1 0 150 -300 100 -300 N
|
||||
P 2 0 1 0 150 -200 -20 -200 N
|
||||
P 2 0 1 0 150 -100 100 -100 N
|
||||
P 2 0 1 0 150 0 -20 0 N
|
||||
P 2 0 1 0 150 100 100 100 N
|
||||
P 2 0 1 0 150 200 -20 200 N
|
||||
P 2 0 1 0 150 300 100 300 N
|
||||
P 2 0 1 0 150 400 -20 400 N
|
||||
P 2 0 1 0 150 500 100 500 N
|
||||
P 2 0 1 0 150 600 -20 600 N
|
||||
P 2 0 1 0 150 700 100 700 N
|
||||
P 5 0 1 10 150 825 -125 675 -125 -675 150 -825 150 825 f
|
||||
X SGND 0 0 -900 150 U 50 50 1 1 P
|
||||
X RED.GND 1 300 700 150 L 50 50 1 1 P
|
||||
X SENSE2 10 300 400 150 L 50 50 1 1 O
|
||||
X CSYNC/VSYNC.GND 11 300 200 150 L 50 50 1 1 P
|
||||
X /VSYNC 12 300 0 150 L 50 50 1 1 I
|
||||
X BLU.GND 13 300 -200 150 L 50 50 1 1 P
|
||||
X HSYNC.GND 14 300 -400 150 L 50 50 1 1 P
|
||||
X /HSYNC 15 300 -600 150 L 50 50 1 1 I
|
||||
X RED.VID 2 300 500 150 L 50 50 1 1 I
|
||||
X /CSYNC 3 300 300 150 L 50 50 1 1 I
|
||||
X SENSE0 4 300 100 150 L 50 50 1 1 O
|
||||
X GRN.VID 5 300 -100 150 L 50 50 1 1 I
|
||||
X GRN.GND 6 300 -300 150 L 50 50 1 1 P
|
||||
X SENSE1 7 300 -500 150 L 50 50 1 1 O
|
||||
X 8 8 300 -700 150 L 50 50 1 1 N N
|
||||
X BLU.VID 9 300 600 150 L 50 50 1 1 O
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# VGA_DB15_Female_HighDensity_MountingHoles
|
||||
#
|
||||
DEF VGA_DB15_Female_HighDensity_MountingHoles J 0 40 Y N 1 F N
|
||||
F0 "J" 0 850 50 H V C CNN
|
||||
F1 "VGA_DB15_Female_HighDensity_MountingHoles" 0 750 50 H V C CNN
|
||||
F2 "" -950 400 50 H I C CNN
|
||||
F3 "" -950 400 50 H I C CNN
|
||||
$FPLIST
|
||||
DSUB*Female*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C -75 -400 25 0 1 0 N
|
||||
C -75 -200 25 0 1 0 N
|
||||
C -75 0 25 0 1 0 N
|
||||
C -75 200 25 0 1 0 N
|
||||
C -75 400 25 0 1 0 N
|
||||
C 0 -300 25 0 1 0 N
|
||||
C 0 -100 25 0 1 0 N
|
||||
C 0 100 25 0 1 0 N
|
||||
C 0 300 25 0 1 0 N
|
||||
C 0 500 25 0 1 0 N
|
||||
C 75 -400 25 0 1 0 N
|
||||
C 75 -200 25 0 1 0 N
|
||||
C 75 0 25 0 1 0 N
|
||||
C 75 200 25 0 1 0 N
|
||||
C 75 400 25 0 1 0 N
|
||||
T 0 -75 -50 20 0 0 0 B Normal 0 C B
|
||||
T 0 0 50 20 0 0 0 B.G Normal 0 C B
|
||||
T 0 -75 150 20 0 0 0 G Normal 0 C B
|
||||
T 0 0 250 20 0 0 0 G.G Normal 0 C B
|
||||
T 0 -75 -450 20 0 0 0 GND Normal 0 C C
|
||||
T 0 75 -50 20 0 0 0 HS Normal 0 C B
|
||||
T 0 75 350 20 0 0 0 ID0 Normal 0 C B
|
||||
T 0 75 150 20 0 0 0 ID1 Normal 0 C B
|
||||
T 0 -75 -250 20 0 0 0 ID2 Normal 0 C B
|
||||
T 0 75 -450 20 0 0 0 ID3 Normal 0 C C
|
||||
T 0 0 -150 20 0 0 0 KEY Normal 0 C B
|
||||
T 0 -75 350 20 0 0 0 R Normal 0 C B
|
||||
T 0 0 450 20 0 0 0 R.G Normal 0 C B
|
||||
T 0 0 -350 20 0 0 0 S.G Normal 0 C B
|
||||
T 0 75 -250 20 0 0 0 VS Normal 0 C B
|
||||
P 2 0 1 0 -125 300 -25 300 N
|
||||
P 2 0 1 0 -25 -300 -125 -300 N
|
||||
P 2 0 1 0 -25 -100 -125 -100 N
|
||||
P 2 0 1 0 -25 100 -125 100 N
|
||||
P 2 0 1 0 -25 500 -125 500 N
|
||||
P 5 0 1 10 -150 700 -150 -600 150 -500 150 600 -150 700 f
|
||||
X SGND 0 0 -700 150 U 50 50 1 1 P
|
||||
X RED.VID 1 -300 400 200 R 50 50 1 1 O
|
||||
X SYNC.GND 10 -300 -300 200 R 50 50 1 1 P
|
||||
X ID0 11 300 400 200 L 50 50 1 1 I
|
||||
X ID1 12 300 200 200 L 50 50 1 1 I
|
||||
X /HSYNC 13 300 0 200 L 50 50 1 1 O
|
||||
X /VSYNC 14 300 -200 200 L 50 50 1 1 O
|
||||
X ID3 15 300 -400 200 L 50 50 1 1 I
|
||||
X GRN.VID 2 -300 200 200 R 50 50 1 1 O
|
||||
X BLU.VID 3 -300 0 200 R 50 50 1 1 O
|
||||
X ID2/RES 4 -300 -200 200 R 50 50 1 1 I
|
||||
X GND 5 -300 -400 200 R 50 50 1 1 P
|
||||
X RED.GND 6 -300 500 200 R 50 50 1 1 P
|
||||
X GRN.GND 7 -300 300 200 R 50 50 1 1 P
|
||||
X BLU.GND 8 -300 100 200 R 50 50 1 1 P
|
||||
X KEY 9 -300 -100 200 R 50 50 1 1 w
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GND
|
||||
#
|
||||
DEF power_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GND" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# pspice_DIODE
|
||||
#
|
||||
DEF pspice_DIODE D 0 40 Y N 1 F N
|
||||
F0 "D" 0 150 50 H V C CNN
|
||||
F1 "pspice_DIODE" 0 -175 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 75 100 75 -100 N
|
||||
P 3 0 1 0 -75 100 -75 -100 75 0 F
|
||||
X K 1 -200 0 150 R 50 50 1 1 I
|
||||
X A 2 200 0 150 L 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
|
@ -1,51 +1,58 @@
|
|||
(module SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm (layer F.Cu) (tedit 6195ED7C)
|
||||
(footprint "SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" (version 20211014) (generator pcbnew)
|
||||
(layer "F.Cu")
|
||||
(tedit 6195ED7C)
|
||||
(descr "8x-dip-switch SPST , Slide, row spacing 7.62 mm (300 mils), body size 9.78x22.5mm (see e.g. https://www.ctscorp.com/wp-content/uploads/206-208.pdf)")
|
||||
(tags "DIP Switch SPST Slide 7.62mm 300mil")
|
||||
(fp_text reference REF** (at 3.81 -3.42) (layer F.SilkS)
|
||||
(attr through_hole)
|
||||
(fp_text reference "REF**" (at 3.81 -3.42) (layer "F.SilkS")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp 58e9df79-4299-4e52-9d27-2aa7c9a712a7)
|
||||
)
|
||||
(fp_text value SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm (at 3.81 21.2) (layer F.Fab)
|
||||
(fp_text value "SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm" (at 3.81 21.2) (layer "F.Fab")
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
(tstamp eca2cc80-8396-4807-8d81-b6ae643b650e)
|
||||
)
|
||||
(fp_line (start 8.95 -2.7) (end -1.35 -2.7) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 8.95 20.5) (end 8.95 -2.7) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.35 20.5) (end 8.95 20.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.35 -2.7) (end -1.35 20.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.38 -2.66) (end -1.38 -1.277) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.38 -2.66) (end 0.004 -2.66) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start 8.76 -2.42) (end 8.76 20.201) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.14 -2.42) (end -1.14 20.201) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.14 20.201) (end 8.76 20.201) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.14 -2.42) (end 8.76 -2.42) (layer F.SilkS) (width 0.12))
|
||||
(fp_line (start -1.08 -1.36) (end -0.08 -2.36) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -1.08 20.14) (end -1.08 -1.36) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 8.7 20.14) (end -1.08 20.14) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start 8.7 -2.36) (end 8.7 20.14) (layer F.Fab) (width 0.1))
|
||||
(fp_line (start -0.08 -2.36) (end 8.7 -2.36) (layer F.Fab) (width 0.1))
|
||||
(fp_text user on (at 5.365 -1.4975) (layer F.Fab)
|
||||
(fp_text user "on" (at 5.365 -1.4975) (layer "F.Fab")
|
||||
(effects (font (size 0.8 0.8) (thickness 0.12)))
|
||||
(tstamp 84a85ab7-e3c3-4814-b0fb-aa7605c88627)
|
||||
)
|
||||
(fp_text user %R (at 7.27 8.89 90) (layer F.Fab)
|
||||
(fp_text user "${REFERENCE}" (at 7.27 8.89 90) (layer "F.Fab")
|
||||
(effects (font (size 0.8 0.8) (thickness 0.12)))
|
||||
(tstamp 8ca9c100-2905-4ba6-9f19-b2b0d84ab3c7)
|
||||
)
|
||||
(pad 16 thru_hole oval (at 7.62 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 8 thru_hole oval (at 0 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 15 thru_hole oval (at 7.62 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 7 thru_hole oval (at 0 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 14 thru_hole oval (at 7.62 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 6 thru_hole oval (at 0 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 13 thru_hole oval (at 7.62 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 5 thru_hole oval (at 0 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 12 thru_hole oval (at 7.62 10.16) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 4 thru_hole oval (at 0 7.62) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 11 thru_hole oval (at 7.62 12.7) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 3 thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 10 thru_hole oval (at 7.62 15.24) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 2 thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 9 thru_hole oval (at 7.62 17.78) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
|
||||
(model ${KISYS3DMOD}/Button_Switch_THT.3dshapes/SW_DIP_SPSTx08_Slide_9.78x22.5mm_W7.62mm_P2.54mm.wrl
|
||||
(at (xyz 0 0 0))
|
||||
(fp_line (start -1.14 20.201) (end 8.76 20.201) (layer "F.SilkS") (width 0.12) (tstamp 601f70bc-038d-4872-8017-e6c5bc773214))
|
||||
(fp_line (start -1.38 -2.66) (end -1.38 -1.277) (layer "F.SilkS") (width 0.12) (tstamp 659873c6-1d93-4121-a4f0-99767f157e75))
|
||||
(fp_line (start -1.38 -2.66) (end 0.004 -2.66) (layer "F.SilkS") (width 0.12) (tstamp 88facf73-eded-468b-8827-0399dd56412d))
|
||||
(fp_line (start -1.14 -2.42) (end 8.76 -2.42) (layer "F.SilkS") (width 0.12) (tstamp 985ad872-b9f3-4c0b-be89-750adb4eb4a3))
|
||||
(fp_line (start 8.76 -2.42) (end 8.76 20.201) (layer "F.SilkS") (width 0.12) (tstamp b08f7f04-5160-400e-973a-0c421f7ce2c2))
|
||||
(fp_line (start -1.14 -2.42) (end -1.14 20.201) (layer "F.SilkS") (width 0.12) (tstamp c7ccb1cf-5393-4907-8d03-a37a89b15ced))
|
||||
(fp_line (start -1.35 20.5) (end 8.95 20.5) (layer "F.CrtYd") (width 0.05) (tstamp 23b4ff1a-bac9-4a4b-9fdc-42302e9dc289))
|
||||
(fp_line (start 8.95 -2.7) (end -1.35 -2.7) (layer "F.CrtYd") (width 0.05) (tstamp 24123fe7-fe58-4c97-b7ff-111810eb2f46))
|
||||
(fp_line (start -1.35 -2.7) (end -1.35 20.5) (layer "F.CrtYd") (width 0.05) (tstamp aca643ef-1a16-46e3-87f3-4e268021bd5e))
|
||||
(fp_line (start 8.95 20.5) (end 8.95 -2.7) (layer "F.CrtYd") (width 0.05) (tstamp d5f4e1c8-7cf4-444b-9ca9-8b515f279896))
|
||||
(fp_line (start 8.7 20.14) (end -1.08 20.14) (layer "F.Fab") (width 0.1) (tstamp 0848f396-717b-45b9-b19f-7872624ffa12))
|
||||
(fp_line (start -0.08 -2.36) (end 8.7 -2.36) (layer "F.Fab") (width 0.1) (tstamp 13e9ad94-8ffa-44c4-910c-524167604492))
|
||||
(fp_line (start 8.7 -2.36) (end 8.7 20.14) (layer "F.Fab") (width 0.1) (tstamp 3df77bca-b5a5-44d4-addc-a4d34b03657e))
|
||||
(fp_line (start -1.08 -1.36) (end -0.08 -2.36) (layer "F.Fab") (width 0.1) (tstamp 50e191e2-5c1a-4003-a449-e05e5906bd0c))
|
||||
(fp_line (start -1.08 20.14) (end -1.08 -1.36) (layer "F.Fab") (width 0.1) (tstamp b78e03cf-9798-4e44-b7de-80158437790a))
|
||||
(pad "1" thru_hole rect (at 0 0) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 167641cc-1b40-4d18-a1c9-ede63a6806ca))
|
||||
(pad "2" thru_hole oval (at 0 2.54) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 51c071ca-bc78-403f-8e26-f8da98236823))
|
||||
(pad "3" thru_hole oval (at 0 5.08) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask) (tstamp 24465d70-87b0-47c2-87be-11913bc4e949))
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||||
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(fp_poly (pts (xy -1.283188 -0.180946) (xy -1.275772 -0.180348) (xy -1.216848 -0.170172) (xy -1.192269 -0.148116) (xy -1.189181 -0.127000) (xy -1.199119 -0.094751) (xy -1.236659 -0.078535) (xy -1.275772 -0.073651)
|
||||
(xy -1.332470 -0.071989) (xy -1.356864 -0.085295) (xy -1.362341 -0.121819) (xy -1.362363 -0.127000) (xy -1.358028 -0.166265) (xy -1.336099 -0.181498) (xy -1.283188 -0.180946) )(layer F.SilkS) (width 0.010000)
|
||||
)
|
||||
(fp_poly (pts (xy 2.922071 -0.095757) (xy 2.945606 -0.045667) (xy 2.958730 -0.011545) (xy 2.996095 0.092364) (xy 2.819894 0.092364) (xy 2.855300 -0.011545) (xy 2.878947 -0.072375) (xy 2.899116 -0.109781)
|
||||
(xy 2.906035 -0.115454) (xy 2.922071 -0.095757) )(layer F.SilkS) (width 0.010000)
|
||||
)
|
||||
)
|
|
@ -1,4 +1,3 @@
|
|||
(sym_lib_table
|
||||
(lib (name snapeda)(type Legacy)(uri ${KIPRJMOD}/snapeda.pretty/snapeda.lib)(options "")(descr ""))
|
||||
(lib (name project)(type Legacy)(uri ${KIPRJMOD}/project.lib)(options "")(descr ""))
|
||||
(lib (name "project")(type "KiCad")(uri "${KIPRJMOD}/project.kicad_sym")(options "")(descr ""))
|
||||
)
|
||||
|
|
Loading…
Reference in New Issue
Block a user