2022-02-05 14:32:44 +00:00
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#include "NuBusFPGADrvr.h"
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OSErr cNuBusFPGAOpen(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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{
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OSErr ret = noErr;
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2022-04-17 09:25:48 +00:00
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/* write_reg(dce, GOBOFB_DEBUG, 0xBEEF0000); */
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/* write_reg(dce, GOBOFB_DEBUG, (unsigned long)dce->dCtlDevBase); */
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2022-02-05 14:32:44 +00:00
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if (dce->dCtlStorage == nil)
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{
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int i;
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/* set up flags in the device control entry */
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/* dce->dCtlFlags |= (dCtlEnableMask | dStatEnableMask | dWritEnableMask |
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dReadEnableMask | dNeedLockMask | dRAMBasedMask ); */
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/* initialize dCtlStorage */
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ReserveMemSys(sizeof(NuBusFPGADriverGlobals));
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dce->dCtlStorage = NewHandleSysClear(sizeof(NuBusFPGADriverGlobals));
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if (dce->dCtlStorage == nil)
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return(openErr);
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HLock(dce->dCtlStorage);
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NuBusFPGADriverGlobalsHdl dStoreHdl = (NuBusFPGADriverGlobalsHdl)dce->dCtlStorage;
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/* (*dStore)->dce = dce; */
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/* for (i = 0 ; i < 256 ; i++) { */
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/* (*dStoreHdl)->shadowClut[i*3+0] = i; */
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/* (*dStoreHdl)->shadowClut[i*3+1] = i; */
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/* (*dStoreHdl)->shadowClut[i*3+2] = i; */
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/* } */
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(*dStoreHdl)->gray = 0;
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(*dStoreHdl)->irqen = 0;
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2022-09-17 12:44:26 +00:00
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(*dStoreHdl)->slot = dce->dCtlSlot;
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2022-09-17 15:06:15 +00:00
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/* Get the HW setting for native resolution */
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(*dStoreHdl)->hres = __builtin_bswap32((unsigned int)read_reg(dce, GOBOFB_HRES)); // fixme: endianness
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(*dStoreHdl)->vres = __builtin_bswap32((unsigned int)read_reg(dce, GOBOFB_VRES)); // fixme: endianness
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2022-02-05 14:32:44 +00:00
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SlotIntQElement *siqel = (SlotIntQElement *)NewPtrSysClear(sizeof(SlotIntQElement));
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if (siqel == NULL) {
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return openErr;
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}
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siqel->sqType = sIQType;
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siqel->sqPrio = 8;
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//siqel->sqAddr = interruptRoutine;
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/* not sure how to get the proper result in C... */
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SlotIntServiceProcPtr sqAddr;
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asm("lea %%pc@(interruptRoutine),%0\n" : "=a"(sqAddr));
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siqel->sqAddr = sqAddr;
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siqel->sqParm = (long)dce->dCtlDevBase;
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(*dStoreHdl)->siqel = siqel;
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2022-09-17 12:44:26 +00:00
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(*dStoreHdl)->curMode = firstVidMode;
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(*dStoreHdl)->curDepth = kDepthMode1;
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2022-02-05 14:32:44 +00:00
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linearGamma(*dStoreHdl);
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2022-04-17 09:25:48 +00:00
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write_reg(dce, GOBOFB_MODE, GOBOFB_MODE_8BIT);
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write_reg(dce, GOBOFB_VIDEOCTRL, 1);
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2022-02-05 14:32:44 +00:00
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ret = changeIRQ(dce, 1, openErr);
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}
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return noErr;
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}
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OSErr cNuBusFPGAClose(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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{
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OSErr ret = noErr;
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/* write_reg(dce, GOBOFB_DEBUG, 0xBEEF0003); */
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/* write_reg(dce, GOBOFB_DEBUG, 0x0000DEAD); */
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asm(".word 0xfe16\n");
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if (dce->dCtlStorage != nil)
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{
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ret = changeIRQ(dce, 0, openErr);
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2022-04-17 09:25:48 +00:00
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write_reg(dce, GOBOFB_VIDEOCTRL, 0);
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DisposePtr((Ptr)(*(NuBusFPGADriverGlobalsHdl)dce->dCtlStorage)->siqel);
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2022-02-05 14:32:44 +00:00
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DisposeHandle(dce->dCtlStorage);
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dce->dCtlStorage = nil;
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}
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return ret;
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}
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