some missing stuff, minor HW update, SW
This commit is contained in:
Romain Dolbeau
parent
68e63497af
commit
de1aaf8161
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@ -1,14 +1,19 @@
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NuBusFPGAID = 0xBEEF
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.include "res.inc"
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NuBusFPGAID = 0xC0
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defMinorBase = 0 /* beginning */
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defMinorLength = 0xC0000 /* 768 KiB */
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defMinorLength = 0x200000 /* 2048 KiB */
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Pages8s = 1 /* no idea */
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defmBounds_Ts = 0
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defmBounds_Ls = 0
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defmBounds_Bs = 480
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defmBounds_Rs = 640
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defmBounds_Ts = 0
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defmBounds_Rs = HRES
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defmBounds_Bs = VRES
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defScrnRow = HRES
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RB8s = HRES
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DrHwNuBusFPGA = 0xBEEF /* placeholder */
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@ -25,8 +30,6 @@ defmPlaneBytes = 0 /* Offset from one plane to the next. */
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SGammaResID = 0
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RB8s = 640
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ChunkyIndexed = 0
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@ -1,4 +1,5 @@
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AS=/home/dolbeau/Retro68/build/toolchain/bin/m68k-apple-macos-as
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CC=/home/dolbeau/Retro68/build/toolchain/bin/m68k-apple-macos-gcc
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OBJCOPY=/home/dolbeau/Retro68/build/toolchain/bin/m68k-apple-macos-objcopy
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NS816DECLROMDIR=/home/dolbeau/ns816-declrom
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@ -7,16 +8,43 @@ PROCESS_ROM=${NS816DECLROMDIR}/process_rom
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APPLEINCS=${NS816DECLROMDIR}/atrap.inc ${NS816DECLROMDIR}/declrom.inc ${NS816DECLROMDIR}/globals.inc
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HRES=1152
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VRES=870
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CSRC=NuBusFPGADrvr_OpenClose.c NuBusFPGADrvr_Ctrl.c NuBusFPGADrvr_Status.c
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CSRC_ASM=${CSRC:.c=.s}
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all: vid_decl_rom.bin vid_decl_rom.srec
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vid_decl_rom.o: vid_decl_rom.s ${APPLEINCS}
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vid_decl_rom.o: vid_decl_rom.s NuBusFPGAPrimaryInit.s NuBusFPGADrvr.s ${APPLEINCS} ${CSRC_ASM} DepVideo.inc
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rm -f res.inc
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echo -e "HRES=${HRES}\nVRES=${VRES}\n" | tee res.inc
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${AS} -march=68020 -mcpu=68020 -I${NS816DECLROMDIR} $< -o $@ -a > vid_decl_rom.l
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NuBusFPGADrvr_OpenClose.s: NuBusFPGADrvr_OpenClose.c NuBusFPGADrvr.h
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${CC} -march=68020 -mcpu=68020 -O2 $< -S -o $@ -DHRES=${HRES} -DVRES=${VRES}
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sed -i -e 's/^\([^a-zA-Z0-9_]*\.globl.*\)/# --- \1/' $@
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sed -i -e 's/\.\(L[0-9][0-9]*\)/.OpenClose_\1/g' $@
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NuBusFPGADrvr_Ctrl.s: NuBusFPGADrvr_Ctrl.c NuBusFPGADrvr.h
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${CC} -march=68020 -mcpu=68020 -O2 $< -S -o $@ -DHRES=${HRES} -DVRES=${VRES}
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sed -i -e 's/^\([^a-zA-Z0-9_]*\.globl.*\)/# --- \1/' $@
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sed -i -e 's/\.\(L[0-9][0-9]*\)/.Ctrl_\1/g' $@
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NuBusFPGADrvr_Status.s: NuBusFPGADrvr_Status.c NuBusFPGADrvr.h
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${CC} -march=68020 -mcpu=68020 -O2 $< -S -o $@ -DHRES=${HRES} -DVRES=${VRES}
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sed -i -e 's/^\([^a-zA-Z0-9_]*\.globl.*\)/# --- \1/' $@
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sed -i -e 's/\.\(L[0-9][0-9]*\)/.Status_\1/g' $@
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vid_decl_rom.srec: vid_decl_rom.o
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${OBJCOPY} $< $@ --input-target=elf32-m68k --output-target=srec
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${OBJCOPY} $^ $@ --input-target=elf32-m68k --output-target=srec
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vid_decl_rom.raw: vid_decl_rom.o
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${OBJCOPY} $< $@ --input-target=elf32-m68k --output-target=binary
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${OBJCOPY} $^ $@ --input-target=elf32-m68k --output-target=binary
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vid_decl_rom.bin: vid_decl_rom.raw
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${NUBUS_CHECKSUM} --input_file $< --output_file $@ --output_size 4096
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${NUBUS_CHECKSUM} --input_file $< --output_file $@ --output_size 32768
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clean:
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rm -f res.inc ${CSRC_ASM} *.o vid_decl_rom.srec vid_decl_rom.raw vid_decl_rom.l
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@ -0,0 +1,74 @@
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#ifndef __NUBUSFPGADRVR_H__
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#define __NUBUSFPGADRVR_H__
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#include <Files.h>
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#include <Devices.h>
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#include <Slots.h>
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#include <MacErrors.h>
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#include <MacMemory.h>
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#include <Video.h>
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#ifndef HRES
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#define HRES 1152
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#warning "Using default HRES"
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#endif
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#ifndef VRES
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#define VRES 870
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#warning "Using default VRES"
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#endif
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#define GOBOFB_BASE 0x00900000
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#define GOBOFB_MODE 0x0
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#define GOBOFB_VBL_MASK 0x4
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//#define GOBOFB_VBL_DIS 0x8
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#define GOBOFB_INTR_CLEAR 0xc
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#define GOBOFB_RESET 0x10
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#define GOBOFB_LUT_ADDR 0x14
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#define GOBOFB_LUT 0x18
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#define GOBOFB_DEBUG 0x20
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#define GOBOFB_INTR_VBL 0x1
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struct MyGammaTbl {
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short gVersion; /*gamma version number*/
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short gType; /*gamma data type*/
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short gFormulaSize; /*Formula data size*/
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short gChanCnt; /*number of channels of data*/
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short gDataCnt; /*number of values/channel*/
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short gDataWidth; /*bits/corrected value (data packed to next larger byte size)*/
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char gFormulaData[3][256]; /*data for formulas followed by gamma values*/
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};
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struct NuBusFPGADriverGlobals {
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AuxDCEPtr dce; // unused
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SlotIntQElement *siqel;
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//unsigned char shadowClut[768];
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char gray;
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char irqen;
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struct MyGammaTbl gamma;
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};
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typedef struct NuBusFPGADriverGlobals NuBusFPGADriverGlobals;
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typedef struct NuBusFPGADriverGlobals *NuBusFPGADriverGlobalsPtr;
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typedef struct NuBusFPGADriverGlobals **NuBusFPGADriverGlobalsHdl;
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static inline void write_reg(AuxDCEPtr dce, unsigned int reg, unsigned int val) {
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*((volatile unsigned int*)(dce->dCtlDevBase+GOBOFB_BASE+reg)) = val;
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}
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static inline unsigned int read_reg(AuxDCEPtr dce, unsigned int reg) {
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return *((volatile unsigned int*)(dce->dCtlDevBase+GOBOFB_BASE+reg));;
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}
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/* ASM */
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extern SlotIntServiceProcPtr interruptRoutine;
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/* ctrl */
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void linearGamma(NuBusFPGADriverGlobalsPtr dStore);
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OSErr changeIRQ(AuxDCEPtr dce, char en, OSErr err);
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OSErr cNuBusFPGACtl(CntrlParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce);
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/* status */
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OSErr cNuBusFPGAStatus(CntrlParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce);
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/* open close */
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OSErr cNuBusFPGAOpen(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce);
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OSErr cNuBusFPGAClose(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce);
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#endif
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@ -0,0 +1,93 @@
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NuBusFPGADrvr:
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.word 0x4c00 /* 0x4c00: ctl, status, needsLock [Devices.a] */
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.word 0
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.word 0
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.word 0
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/* Entry point offset table */
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.word _NuBusFPGAOpen-NuBusFPGADrvr /* open routine */
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.word NuBusFPGADrvr-NuBusFPGADrvr /* no prime */
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.word _NuBusFPGACtl-NuBusFPGADrvr /* control */
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.word _NuBusFPGAStatus-NuBusFPGADrvr /* status */
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.word _NuBusFPGAClose-NuBusFPGADrvr /* close */
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_NuBusFPGATitle:
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.byte _NuBusFPGATitle_StringEnd-.-1 /* pascal string length */
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.ascii ".NuBusFPGA_Drvr"
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_NuBusFPGATitle_StringEnd:
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.word 0 /* version number */
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/* A0 pointer to driver parameter block */
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/* A1 pointer to driver device control entry */
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ALIGN 2
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_NuBusFPGAOpen:
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MOVE.L %A1, -(%A7)
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MOVE.L %A0, -(%A7)
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JSR cNuBusFPGAOpen
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MOVE.L (%A7)+, %a0
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MOVE.L (%A7)+, %a1
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rts
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_NuBusFPGAOpenError:
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moveq #-23,%d0 /* error flag */
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rts
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_NuBusFPGACtl:
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MOVE.L %A1, -(%A7)
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MOVE.L %A0, -(%A7)
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jsr cNuBusFPGACtl
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MOVE.L (%A7)+, %a0
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MOVE.L (%A7)+, %a1
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BTST #9,%a0@(ioTrap) /* noQueueBit is 9 */
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BEQ.S _GoIODone
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rts
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_NuBusFPGAStatus:
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MOVE.L %A1, -(%A7)
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MOVE.L %A0, -(%A7)
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jsr cNuBusFPGAStatus
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MOVE.L (%A7)+, %a0
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MOVE.L (%A7)+, %a1
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BTST #9,%a0@(ioTrap) /* noQueueBit is 9 */
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BEQ.S _GoIODone
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rts
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_NuBusFPGAClose:
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MOVE.L %A1, -(%A7)
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MOVE.L %A0, -(%A7)
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jsr cNuBusFPGAClose
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MOVE.L (%A7)+, %a0
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MOVE.L (%A7)+, %a1
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rts
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_GoIODone:
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/* MOVEA.L JIODone,%A0 */
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/* JMP (%A0) */
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movel JIODone,%sp@-
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rts
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.include "NuBusFPGADrvr_OpenClose.s"
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.text
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.include "NuBusFPGADrvr_Ctrl.s"
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.text
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.include "NuBusFPGADrvr_Status.s"
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.text
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ALIGN 2
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interruptRoutine:
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moveal %a1,%a0
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addal #0x0090000c,%a0 /* FIXME */
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MOVEQ #1,%D0
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_SwapMMUMode
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clrb %a0@ /* we only need to write */
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_SwapMMUMode
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movel %a1,%d0
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roll #8,%d0
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andiw #15,%d0
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moveal #0xd28,%a0 /* JVBLTask */
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/* other codes don't need the intermediate moveal, what's the proper syntax ? */
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moveal (%a0),%a0
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jsr (%a0)
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moveq #1,%d0
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rts
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ALIGN 2
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@ -0,0 +1,307 @@
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#include "NuBusFPGADrvr.h"
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#if 0
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typedef struct AuxDCE {
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Ptr dCtlDriver; /* pointer or handle to driver */
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short dCtlFlags; /* flags */
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QHdr dCtlQHdr; /* I/O queue header */
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long dCtlPosition; /* current R/W byte position */
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Handle dCtlStorage; /* handle to private storage */
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short dCtlRefNum; /* driver reference number */
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long dCtlCurTicks; /* used internally */
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GrafPtr dCtlWindow; /* pointer to driverâs window */
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short dCtlDelay; /* ticks between periodic actions */
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short dCtlEMask; /* desk accessory event mask */
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short dCtlMenu; /* desk accessory menu ID */
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char dCtlSlot; /* slot */
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char dCtlSlotId; /* sResource directory ID */
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long dCtlDevBase; /* slot device base address */
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Ptr dCtlOwner; /* reserved; must be 0 */
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char dCtlExtDev; /* external device ID */
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char fillByte; /* reserved */
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} AuxDCE;
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typedef AuxDCE *AuxDCEPtr, **AuxDCEHandle;
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#endif
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void linearGamma(NuBusFPGADriverGlobalsPtr dStore) {
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int i;
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dStore->gamma.gVersion = 0;
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dStore->gamma.gType = 0;
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dStore->gamma.gFormulaSize = 0;
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dStore->gamma.gChanCnt = 3;
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dStore->gamma.gDataCnt = 256;
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dStore->gamma.gDataWidth = 8;
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for (i = 0 ; i < 256 ; i++) {
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dStore->gamma.gFormulaData[0][i] = i;
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dStore->gamma.gFormulaData[1][i] = i;
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dStore->gamma.gFormulaData[2][i] = i;
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}
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}
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OSErr changeIRQ(AuxDCEPtr dce, char en, OSErr err) {
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NuBusFPGADriverGlobalsHdl dStoreHdl = (NuBusFPGADriverGlobalsHdl)dce->dCtlStorage;
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NuBusFPGADriverGlobalsPtr dStore = *dStoreHdl;
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char busMode = 1;
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if (en != dStore->irqen) {
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/* write_reg(dce, GOBOFB_DEBUG, 0xBEEF000F); */
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/* write_reg(dce, GOBOFB_DEBUG, en); */
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if (en) {
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if (SIntInstall(dStore->siqel, dce->dCtlSlot)) {
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return err;
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}
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} else {
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if (SIntRemove(dStore->siqel, dce->dCtlSlot)) {
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return err;
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}
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}
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SwapMMUMode ( &busMode );
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write_reg(dce, GOBOFB_VBL_MASK, en ? GOBOFB_INTR_VBL : 0);
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SwapMMUMode ( &busMode );
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dStore->irqen = en;
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}
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return noErr;
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}
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/*
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7.1.1:
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11 Debug: 0x00000003
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2 Debug: 0x00000004
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1 Debug: 0x00000005
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4 Debug: 0x00000006
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1 <EFBFBD>Debug: 0x00000002
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7.5.3:
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4 Debug: 0x00000002
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12 Debug: 0x00000003
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3 Debug: 0x00000004
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5 Debug: 0x00000005
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5 Debug: 0x00000006
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5 Debug: 0x00000009
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4 Debug: 0x0000000a
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5 Debug: 0x00000010
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1 <EFBFBD>Debug: 0x00000002
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8.1:
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5 Debug: 0x00000002
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9 Debug: 0x00000003
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1 Debug: 0x00000004
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6 Debug: 0x00000005
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6 Debug: 0x00000006
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4 Debug: 0x00000009
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5 Debug: 0x0000000a
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4 Debug: 0x00000010
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1 <EFBFBD>Debug: 0x00000002
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*/
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OSErr cNuBusFPGACtl(CntrlParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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{
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NuBusFPGADriverGlobalsHdl dStoreHdl = (NuBusFPGADriverGlobalsHdl)dce->dCtlStorage;
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NuBusFPGADriverGlobalsPtr dStore = *dStoreHdl;
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short ret = -1;
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char busMode = 1;
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write_reg(dce, GOBOFB_DEBUG, 0xBEEF0001);
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write_reg(dce, GOBOFB_DEBUG, pb->csCode);
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#if 1
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switch (pb->csCode)
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{
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case -1:
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asm volatile(".word 0xfe16\n");
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break;
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case cscReset:
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{
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VDPageInfo *vPInfo = (VDPageInfo *)*(long *)pb->csParam;
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vPInfo->csMode = eightBitMode;
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vPInfo->csPage = 0;
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vPInfo->csBaseAddr = 0;
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ret = noErr;
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}
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break;
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case cscKillIO:
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asm volatile(".word 0xfe16\n");
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ret = noErr;
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break;
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case cscSetMode:
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{
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VDPageInfo *vPInfo = (VDPageInfo *)*(long *)pb->csParam;
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if (vPInfo->csMode != eightBitMode)
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return paramErr;
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if (vPInfo->csPage != 0)
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return paramErr;
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vPInfo->csBaseAddr = 0;
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ret = noErr;
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}
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break;
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case cscSetEntries: /* 3 */
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if (1) {
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VDSetEntryRecord **vdentry = (VDSetEntryRecord **)(long *)pb->csParam;
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int csCount = (*vdentry)->csCount;
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int csStart = (*vdentry)->csStart;
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int i;
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if (csCount <= 0) {
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ret = noErr;
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goto cscSetMode_done;
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}
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SwapMMUMode ( &busMode );
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if (csStart < 0) {
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for (i = 0 ; i <= csCount ; i++) {
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unsigned char idx = ((*vdentry)->csTable[i].value & 0x0FF);
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/* dStore->shadowClut[idx*3+0] = (*vdentry)->csTable[i].rgb.red; */
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/* dStore->shadowClut[idx*3+1] = (*vdentry)->csTable[i].rgb.green; */
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/* dStore->shadowClut[idx*3+2] = (*vdentry)->csTable[i].rgb.blue; */
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write_reg(dce, GOBOFB_LUT_ADDR, 3 * idx);
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write_reg(dce, GOBOFB_LUT, dStore->gamma.gFormulaData[0][(*vdentry)->csTable[i].rgb.red>>8 & 0xFF]);
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write_reg(dce, GOBOFB_LUT, dStore->gamma.gFormulaData[1][(*vdentry)->csTable[i].rgb.green>>8 & 0xFF]);
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write_reg(dce, GOBOFB_LUT, dStore->gamma.gFormulaData[2][(*vdentry)->csTable[i].rgb.blue>>8 & 0xFF]);
|
||||
/* write_reg(dce, GOBOFB_LUT, (*vdentry)->csTable[i].rgb.red); */
|
||||
/* write_reg(dce, GOBOFB_LUT, (*vdentry)->csTable[i].rgb.green); */
|
||||
/* write_reg(dce, GOBOFB_LUT, (*vdentry)->csTable[i].rgb.blue); */
|
||||
}
|
||||
} else {
|
||||
write_reg(dce, GOBOFB_LUT_ADDR, 3 * (csStart & 0xFF));
|
||||
for (i = 0 ; i <= csCount ; i++) {
|
||||
/* dStore->shadowClut[(i+csStart)*3+0] = (*vdentry)->csTable[i].rgb.red; */
|
||||
/* dStore->shadowClut[(i+csStart)*3+1] = (*vdentry)->csTable[i].rgb.green; */
|
||||
/* dStore->shadowClut[(i+csStart)*3+2] = (*vdentry)->csTable[i].rgb.blue; */
|
||||
|
||||
write_reg(dce, GOBOFB_LUT, dStore->gamma.gFormulaData[0][(*vdentry)->csTable[i].rgb.red>>8 & 0xFF]);
|
||||
write_reg(dce, GOBOFB_LUT, dStore->gamma.gFormulaData[1][(*vdentry)->csTable[i].rgb.green>>8 & 0xFF]);
|
||||
write_reg(dce, GOBOFB_LUT, dStore->gamma.gFormulaData[2][(*vdentry)->csTable[i].rgb.blue>>8 & 0xFF]);
|
||||
/* write_reg(dce, GOBOFB_LUT, (*vdentry)->csTable[i].rgb.red); */
|
||||
/* write_reg(dce, GOBOFB_LUT, (*vdentry)->csTable[i].rgb.green); */
|
||||
/* write_reg(dce, GOBOFB_LUT, (*vdentry)->csTable[i].rgb.blue); */
|
||||
}
|
||||
}
|
||||
SwapMMUMode ( &busMode );
|
||||
ret = noErr;
|
||||
} else {
|
||||
ret = noErr;
|
||||
}
|
||||
cscSetMode_done:
|
||||
break;
|
||||
case cscSetGamma: /* 4 */
|
||||
{
|
||||
VDGammaRecord *vdgamma = (VDGammaRecord *)*(long *)pb->csParam;
|
||||
GammaTbl *gammaTbl = (GammaTbl*)vdgamma->csGTable;
|
||||
int i;
|
||||
if (gammaTbl == NULL) {
|
||||
linearGamma(dStore);
|
||||
} else {
|
||||
if (gammaTbl->gDataWidth != 8)
|
||||
return paramErr;
|
||||
if (gammaTbl->gDataCnt != 256) // 8-bits
|
||||
return paramErr;
|
||||
if ((gammaTbl->gChanCnt != 1) && (gammaTbl->gChanCnt != 3))
|
||||
return paramErr;
|
||||
if ((gammaTbl->gType != 0) && (gammaTbl->gType != 0xFFFFBEEF))
|
||||
return paramErr;
|
||||
if (gammaTbl->gFormulaSize != 0)
|
||||
return paramErr;
|
||||
|
||||
dStore->gamma.gVersion = gammaTbl->gVersion;
|
||||
dStore->gamma.gType = gammaTbl->gType;
|
||||
dStore->gamma.gFormulaSize = gammaTbl->gFormulaSize;
|
||||
dStore->gamma.gChanCnt = gammaTbl->gChanCnt;
|
||||
dStore->gamma.gDataCnt = gammaTbl->gDataCnt;
|
||||
dStore->gamma.gDataWidth = gammaTbl->gDataWidth;
|
||||
|
||||
int og, ob;
|
||||
if (gammaTbl->gChanCnt == 1)
|
||||
og = ob = 0;
|
||||
else {
|
||||
og = 256;
|
||||
ob = 512;
|
||||
}
|
||||
for (i = 0 ; i < gammaTbl->gDataCnt ; i++) {
|
||||
dStore->gamma.gFormulaData[0][i] = ((unsigned char*)gammaTbl->gFormulaData)[i + 0];
|
||||
dStore->gamma.gFormulaData[1][i] = ((unsigned char*)gammaTbl->gFormulaData)[i + og];
|
||||
dStore->gamma.gFormulaData[2][i] = ((unsigned char*)gammaTbl->gFormulaData)[i + ob];
|
||||
}
|
||||
}
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
case cscGrayPage: /* 5 == cscGrayScreen */
|
||||
{
|
||||
/* FIXME: TODO */
|
||||
VDPageInfo *vPInfo = (VDPageInfo *)*(long *)pb->csParam;
|
||||
if (vPInfo->csPage != 0)
|
||||
return paramErr;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
case cscSetGray: /* 6 */
|
||||
{
|
||||
VDGrayRecord *vGInfo = (VDGrayRecord *)*(long *)pb->csParam;
|
||||
dStore->gray = vGInfo->csMode;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscSetInterrupt: /* 7 */
|
||||
{
|
||||
VDFlagRecord *vdflag = (VDFlagRecord *)*(long *)pb->csParam;
|
||||
ret = changeIRQ(dce, 1 - vdflag->csMode, controlErr);
|
||||
}
|
||||
break;
|
||||
|
||||
case cscDirectSetEntries: /* 8 */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
return controlErr;
|
||||
break;
|
||||
|
||||
case cscSetDefaultMode: /* 9 */
|
||||
{
|
||||
VDDefMode *vddefm = (VDDefMode *)*(long *)pb->csParam;
|
||||
if (vddefm->csID != 128)
|
||||
return paramErr;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscSwitchMode: /* 0xa */
|
||||
{
|
||||
VDSwitchInfoRec *vdswitch = *(VDSwitchInfoRec **)(long *)pb->csParam;
|
||||
if (vdswitch->csMode != eightBitMode)
|
||||
return paramErr;
|
||||
if (vdswitch->csData != 128)
|
||||
return paramErr;
|
||||
if (vdswitch->csPage != 0)
|
||||
return paramErr;
|
||||
vdswitch->csBaseAddr = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscSavePreferredConfiguration: /* 0x10 */
|
||||
// is that ony for PCI drivers?
|
||||
#if 1
|
||||
{
|
||||
VDSwitchInfoRec *vdswitch = *(VDSwitchInfoRec **)(long *)pb->csParam;
|
||||
if (vdswitch->csMode != eightBitMode)
|
||||
return paramErr;
|
||||
if (vdswitch->csData != 128)
|
||||
return paramErr;
|
||||
if (vdswitch->csPage != 0)
|
||||
return paramErr;
|
||||
vdswitch->csBaseAddr = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
#else
|
||||
ret = controlErr;
|
||||
#endif
|
||||
break;
|
||||
|
||||
default: /* always return controlErr for unknown csCode */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
ret = controlErr;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
#include "NuBusFPGADrvr.h"
|
||||
|
||||
OSErr cNuBusFPGAOpen(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
|
||||
{
|
||||
OSErr ret = noErr;
|
||||
write_reg(dce, GOBOFB_DEBUG, 0xBEEF0000);
|
||||
write_reg(dce, GOBOFB_DEBUG, (unsigned long)dce->dCtlDevBase);
|
||||
|
||||
if (dce->dCtlStorage == nil)
|
||||
{
|
||||
int i;
|
||||
/* set up flags in the device control entry */
|
||||
/* dce->dCtlFlags |= (dCtlEnableMask | dStatEnableMask | dWritEnableMask |
|
||||
dReadEnableMask | dNeedLockMask | dRAMBasedMask ); */
|
||||
|
||||
/* initialize dCtlStorage */
|
||||
ReserveMemSys(sizeof(NuBusFPGADriverGlobals));
|
||||
dce->dCtlStorage = NewHandleSysClear(sizeof(NuBusFPGADriverGlobals));
|
||||
if (dce->dCtlStorage == nil)
|
||||
return(openErr);
|
||||
HLock(dce->dCtlStorage);
|
||||
NuBusFPGADriverGlobalsHdl dStoreHdl = (NuBusFPGADriverGlobalsHdl)dce->dCtlStorage;
|
||||
/* (*dStore)->dce = dce; */
|
||||
|
||||
/* for (i = 0 ; i < 256 ; i++) { */
|
||||
/* (*dStoreHdl)->shadowClut[i*3+0] = i; */
|
||||
/* (*dStoreHdl)->shadowClut[i*3+1] = i; */
|
||||
/* (*dStoreHdl)->shadowClut[i*3+2] = i; */
|
||||
/* } */
|
||||
|
||||
(*dStoreHdl)->gray = 0;
|
||||
(*dStoreHdl)->irqen = 0;
|
||||
|
||||
SlotIntQElement *siqel = (SlotIntQElement *)NewPtrSysClear(sizeof(SlotIntQElement));
|
||||
if (siqel == NULL) {
|
||||
return openErr;
|
||||
}
|
||||
siqel->sqType = sIQType;
|
||||
siqel->sqPrio = 8;
|
||||
//siqel->sqAddr = interruptRoutine;
|
||||
/* not sure how to get the proper result in C... */
|
||||
SlotIntServiceProcPtr sqAddr;
|
||||
asm("lea %%pc@(interruptRoutine),%0\n" : "=a"(sqAddr));
|
||||
siqel->sqAddr = sqAddr;
|
||||
siqel->sqParm = (long)dce->dCtlDevBase;
|
||||
(*dStoreHdl)->siqel = siqel;
|
||||
|
||||
linearGamma(*dStoreHdl);
|
||||
|
||||
ret = changeIRQ(dce, 1, openErr);
|
||||
}
|
||||
|
||||
return noErr;
|
||||
}
|
||||
|
||||
OSErr cNuBusFPGAClose(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
|
||||
{
|
||||
OSErr ret = noErr;
|
||||
/* write_reg(dce, GOBOFB_DEBUG, 0xBEEF0003); */
|
||||
/* write_reg(dce, GOBOFB_DEBUG, 0x0000DEAD); */
|
||||
asm(".word 0xfe16\n");
|
||||
if (dce->dCtlStorage != nil)
|
||||
{
|
||||
ret = changeIRQ(dce, 0, openErr);
|
||||
DisposePtr((*(NuBusFPGADriverGlobalsHdl)dce->dCtlStorage)->siqel);
|
||||
DisposeHandle(dce->dCtlStorage);
|
||||
dce->dCtlStorage = nil;
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
#include "NuBusFPGADrvr.h"
|
||||
|
||||
/*
|
||||
7.1:
|
||||
2 Debug: 0x00000009
|
||||
1 <EFBFBD>Debug: 0x00000009
|
||||
|
||||
|
||||
7.5.3:
|
||||
6 Debug: 0x00000008
|
||||
112 Debug: 0x0000000a
|
||||
32 Debug: 0x0000000c
|
||||
14 Debug: 0x0000000d
|
||||
3 Debug: 0x0000000e
|
||||
4 Debug: 0x00000010
|
||||
2 Debug: 0x00000011
|
||||
78 Debug: 0x00000012
|
||||
1 Debug: 0x00000014
|
||||
1 <EFBFBD>Debug: 0x0000000a
|
||||
|
||||
8.1:
|
||||
9 Debug: 0x00000008
|
||||
273 Debug: 0x0000000a
|
||||
156 Debug: 0x0000000c
|
||||
16 Debug: 0x0000000d
|
||||
3 Debug: 0x00000010
|
||||
3 Debug: 0x00000011
|
||||
157 Debug: 0x00000012
|
||||
1 Debug: 0x00000014
|
||||
2 Debug: 0x00000018
|
||||
10 Debug: 0x0000001c
|
||||
1 <EFBFBD>Debug: 0x0000000c
|
||||
*/
|
||||
|
||||
|
||||
OSErr cNuBusFPGAStatus(CntrlParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
|
||||
{
|
||||
NuBusFPGADriverGlobalsHdl dStoreHdl = (NuBusFPGADriverGlobalsHdl)dce->dCtlStorage;
|
||||
NuBusFPGADriverGlobalsPtr dStore = *dStoreHdl;
|
||||
short ret = -1;
|
||||
write_reg(dce, GOBOFB_DEBUG, 0xBEEF0002);
|
||||
write_reg(dce, GOBOFB_DEBUG, pb->csCode);
|
||||
#if 1
|
||||
switch (pb->csCode)
|
||||
{
|
||||
case -1:
|
||||
asm volatile(".word 0xfe16\n");
|
||||
break;
|
||||
case 0:
|
||||
ret = statusErr;
|
||||
break;
|
||||
/* case 1: */
|
||||
/* break; */
|
||||
case cscGetMode: /* 2 */
|
||||
{
|
||||
VDPageInfo *vPInfo = (VDPageInfo *)*(long *)pb->csParam;
|
||||
vPInfo->csMode = eightBitMode;
|
||||
vPInfo->csPage = 0;
|
||||
vPInfo->csBaseAddr = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
case cscGetEntries: /* 3 */
|
||||
/* FIXME: TODO */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
ret = noErr;
|
||||
break;
|
||||
case cscGetPageCnt: /* 4 == cscGetPages */
|
||||
{
|
||||
VDPageInfo *vPInfo = (VDPageInfo *)*(long *)pb->csParam;
|
||||
if (vPInfo->csMode != eightBitMode)
|
||||
return paramErr;
|
||||
vPInfo->csPage = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
asm volatile(".word 0xfe16\n");
|
||||
ret = noErr;
|
||||
break;
|
||||
case cscGetPageBase: /* 5 == cscGetBaseAddr */
|
||||
{
|
||||
VDPageInfo *vPInfo = (VDPageInfo *)*(long *)pb->csParam;
|
||||
if (vPInfo->csPage != 0)
|
||||
return paramErr;
|
||||
vPInfo->csBaseAddr = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
asm volatile(".word 0xfe16\n");
|
||||
ret = noErr;
|
||||
break;
|
||||
case cscGetGray: /* 6 */
|
||||
{
|
||||
VDGrayRecord *vGInfo = (VDGrayRecord *)*(long *)pb->csParam;
|
||||
vGInfo->csMode = dStore->gray;
|
||||
ret = noErr;
|
||||
}
|
||||
asm volatile(".word 0xfe16\n");
|
||||
break;
|
||||
case cscGetInterrupt: /* 7 */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
{
|
||||
VDFlagRecord *vdflag = (VDFlagRecord *)*(long *)pb->csParam;
|
||||
vdflag->csMode = 1 - dStore->irqen;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
case cscGetGamma: /* 8 */
|
||||
{
|
||||
VDGammaRecord *vdgamma = (VDGammaRecord *)*(long *)pb->csParam;
|
||||
vdgamma->csGTable = (Ptr)&dStore->gamma;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
case cscGetDefaultMode: /* 9 */
|
||||
{
|
||||
VDDefMode *vddefm = (VDDefMode *)*(long *)pb->csParam;
|
||||
vddefm->csID = 128;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscGetCurMode: /* 0xa */
|
||||
{
|
||||
VDSwitchInfoRec *vdswitch = *(VDSwitchInfoRec **)(long *)pb->csParam;
|
||||
vdswitch->csMode = eightBitMode;
|
||||
vdswitch->csData = 128;
|
||||
vdswitch->csPage = 0;
|
||||
vdswitch->csBaseAddr = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscGetSync: /* 0xb */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
ret = statusErr;
|
||||
break;
|
||||
|
||||
case cscGetConnection: /* 0xc */
|
||||
{
|
||||
VDDisplayConnectInfoRec *vdconn = *(VDDisplayConnectInfoRec **)(long *)pb->csParam;
|
||||
vdconn->csDisplayType = kGenericLCD;
|
||||
vdconn->csConnectTaggedType = 0;
|
||||
vdconn->csConnectTaggedData = 0;
|
||||
vdconn->csConnectFlags = (1<<kTaggingInfoNonStandard) | (1<<kIsMonoDev) | (1<<kAllModesSafe) | (1<<kAllModesValid);
|
||||
vdconn->csDisplayComponent = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscGetModeTiming: /* 0xd */
|
||||
{
|
||||
VDTimingInfoRec *vdtim = *(VDTimingInfoRec **)(long *)pb->csParam;
|
||||
ret = noErr;
|
||||
if ((vdtim->csTimingMode != 128) &&
|
||||
(vdtim->csTimingMode != kDisplayModeIDFindFirstResolution) &&
|
||||
(vdtim->csTimingMode != kDisplayModeIDCurrent))
|
||||
return paramErr;
|
||||
vdtim->csTimingFormat = kDeclROMtables;
|
||||
vdtim->csTimingData = 0;
|
||||
vdtim->csTimingFlags = kModeDefault;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscGetModeBaseAddress: /* 0xe */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
/* undocumented ??? */
|
||||
ret = statusErr;
|
||||
break;
|
||||
|
||||
case cscGetPreferredConfiguration: /* 0x10 */
|
||||
{
|
||||
VDSwitchInfoRec *vdswitch = *(VDSwitchInfoRec **)(long *)pb->csParam;
|
||||
vdswitch->csMode = eightBitMode;
|
||||
vdswitch->csData = 128;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscGetNextResolution: /* 0x11 */
|
||||
{
|
||||
VDResolutionInfoRec *vdres = *(VDResolutionInfoRec **)(long *)pb->csParam;
|
||||
switch (vdres->csPreviousDisplayModeID)
|
||||
{
|
||||
case 128:
|
||||
vdres->csDisplayModeID = kDisplayModeIDNoMoreResolutions;
|
||||
break;
|
||||
case kDisplayModeIDFindFirstResolution:
|
||||
case kDisplayModeIDCurrent:
|
||||
vdres->csDisplayModeID = 128;
|
||||
vdres->csHorizontalPixels = HRES;
|
||||
vdres->csVerticalLines = VRES;
|
||||
vdres->csRefreshRate = 60 << 16; /* Fixed 16+16 */
|
||||
vdres->csMaxDepthMode = kDepthMode1;
|
||||
break;
|
||||
default:
|
||||
return paramErr;
|
||||
}
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscGetVideoParameters: /* 0x12 */
|
||||
{
|
||||
VDVideoParametersInfoRec *vdparam = *(VDVideoParametersInfoRec **)(long *)pb->csParam;
|
||||
if ((vdparam->csDisplayModeID != 128) &&
|
||||
(vdparam->csDisplayModeID != kDisplayModeIDFindFirstResolution) &&
|
||||
(vdparam->csDisplayModeID != kDisplayModeIDCurrent))
|
||||
return paramErr;
|
||||
if (vdparam->csDepthMode != kDepthMode1)
|
||||
return paramErr;
|
||||
VPBlock* vpblock = vdparam->csVPBlockPtr;
|
||||
/* basically the same as the EBVParms ? */
|
||||
vdparam->csPageCount = 0;
|
||||
vdparam->csDeviceType = clutType;
|
||||
vpblock->vpBaseOffset = 0;
|
||||
vpblock->vpRowBytes = HRES;
|
||||
vpblock->vpBounds.left = 0;
|
||||
vpblock->vpBounds.top = 0;
|
||||
vpblock->vpBounds.right = HRES;
|
||||
vpblock->vpBounds.bottom = VRES;
|
||||
vpblock->vpVersion = 0;
|
||||
vpblock->vpPackType = 0;
|
||||
vpblock->vpPackSize = 0;
|
||||
vpblock->vpHRes = 0x480000;
|
||||
vpblock->vpVRes = 0x480000;
|
||||
vpblock->vpPixelType = chunky;
|
||||
vpblock->vpPixelSize = 8;
|
||||
vpblock->vpCmpCount = 1;
|
||||
vpblock->vpCmpSize = 8;
|
||||
vpblock->vpPlaneBytes = 0;
|
||||
ret = noErr;
|
||||
}
|
||||
break;
|
||||
|
||||
case cscGetGammaInfoList: /* 0x14 */
|
||||
ret = statusErr;
|
||||
break;
|
||||
|
||||
case cscRetrieveGammaTable: /* 0x17 */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
ret = statusErr;
|
||||
break;
|
||||
|
||||
case cscGetConvolution: /* 0x18 */
|
||||
ret = statusErr;
|
||||
break;
|
||||
|
||||
case cscGetMultiConnect: /* 0x1c */
|
||||
ret = statusErr;
|
||||
break;
|
||||
|
||||
default: /* always return statusErr for unknown csCode */
|
||||
asm volatile(".word 0xfe16\n");
|
||||
ret = statusErr;
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
|
||||
.byte sExec2 /* Code revision (Primary init) */
|
||||
.byte sCPU68020 /* CPU type is 68020 */
|
||||
.short 0 /* Reserved */
|
||||
.long Begin-. /* Offset to code. */
|
||||
|
||||
Begin:
|
||||
movew #1,%A0@(seStatus) /* VendorStatus <- 1 {Code was executed} */
|
||||
movel %A0,%A3 /* save param block {A0 is destroyed} */
|
||||
|
||||
/* Turn the slot number into a base address. */
|
||||
moveq #0,%D0 /* D0 <- 00000000 */
|
||||
MOVE.B %A0@(seSlot),%D0 /* D0 <- 0000000s */
|
||||
LSL.W #4,%D0 /* D0 <- 000000s0 */
|
||||
/* OR.B %A0@(seSlot),%D0 /* D0 <- 000000ss */
|
||||
OR.W #0xF00,%D0 /* D0 <- 00000Fss */
|
||||
SWAP %D0 /* D0 <- 0Fss0000 */
|
||||
LSL.L #4,%D0 /* D0 <- Fss00000 */
|
||||
movel %D0,%A2 /* A2 <- Base address to the slot. */
|
||||
|
||||
|
||||
/* Reset the hardware. */
|
||||
/* DO YOUR RESET STUFF HERE */
|
||||
|
||||
/* Set mode to one bit per pixel. ; */
|
||||
/* DO YOUR MODE SETTING HERE */
|
||||
|
||||
/* Disable interrupts. ; */
|
||||
movel %A2,%A0 /* get slot base */
|
||||
ADD.L #0x00900004,%A0 /* Adjust the base */ /* FIXME */
|
||||
CLR.B (%A0) /* Disable interrupt from card */
|
||||
|
||||
/* set the color table to black and white */
|
||||
/* SET THE TABLE HERE */
|
||||
|
||||
|
||||
/* The Apple Video card configuration ROM has two video sResources conforming to the */
|
||||
/* two possible different memory configurations. Now we want to figure out which */
|
||||
/* of the configurations we have, and delete the incorrect video sResource from */
|
||||
/* the slot resource table. */
|
||||
/* */
|
||||
/* size the RAM on the video card. To do this, we look for a nice longword in the second */
|
||||
/* half of the frame buffer array that doesn't show up on the screen. I've selected the */
|
||||
/* last longword of the first scanline that is a multiple of 8 in the second RAM bank (line 264). */
|
||||
/* This alignment guarantees that this memory is off the right edge in all pixel depths */
|
||||
/* when the frame buffer base addr is on a normal page boundary. */
|
||||
/* */
|
||||
/* */
|
||||
/* */
|
||||
TestPos = (265*1024)-4 /* */
|
||||
TestPat = 0x4d434132 /* test bit pattern */
|
||||
|
||||
SUBA #smParamBlockSize,%SP /* make an SDM parameter block on stack */
|
||||
movel %SP,%A0 /* get pointer to parm block now */
|
||||
MOVE.B seSlot(%A3),spSlot(%A0) /* put slot in pBlock */
|
||||
CLR.B spExtDev(%A0) /* external device = 0 */
|
||||
|
||||
/* movel #TestPos,%D1 /* get offset in %D1 */
|
||||
/* movel #TestPat,(%A2,%D1.L) /* write to alleged RAM */
|
||||
/* movel #-1,-(%SP) /* write out some garbage to clear data lines */
|
||||
/* ADDQ #4,%SP /* and pitch it */
|
||||
/* movel (%A2,%D1.L),%D0 /* read pattern back */
|
||||
/* CMP.L #TestPat,%D0 /* did it stick? */
|
||||
/* BEQ.S ram /* if equal, we have ram */
|
||||
/* MOVE.B #sRsrc_Video8,spID(%A0) /* if not, remove 8-bit table */
|
||||
/* BRA.S noram
|
||||
/*ram:
|
||||
/* MOVE.B #sRsrc_Video4,spID(%A0) /* remove 4-bit table if we have ram */
|
||||
/*noram:
|
||||
/* _sDeleteSRTRec */ /* remove the invalid entry */
|
||||
/* movel #SDeleteSRTRec,%d0
|
||||
/* _SlotManager
|
||||
/* BNE.S done /* */
|
||||
MOVE #2,seStatus(%A3) /* mark the change */
|
||||
done: ADDA #smParamBlockSize,%SP /* clean up */
|
||||
|
||||
/* Clear video RAM to a nice gray */
|
||||
movel #0xAAAAAAAA,%D0 /* graypat1 := $AAAAAAAA */
|
||||
movel %D0,%D1
|
||||
NOT.L %D1
|
||||
|
||||
MOVE.W #defScrnRow,%D4 /* sRow := defScrnRow {Bytes per pixel line} */
|
||||
MOVE.W #defmBounds_Bs-1,%D3 /* sHei := defScrnHeight {Screen Height in pixels} */
|
||||
|
||||
movel %A2,%A1 /* init row pointer /* REPEAT */
|
||||
NxtRow: movel %A1,%A0 /* get next row */
|
||||
MOVE.W #defScrnRow/4-1,%D2 /* rowlongs := defScrnRow/4 - 1 {How many Longs there are} */
|
||||
NxtLong: movel %D0,(%A0)+ /* (%A0) := graypat(1/2) */
|
||||
DBF %D2,NxtLong /* UNTIL rowlongs < 0 */
|
||||
EXG %D0,%D1 /* graypat1 <-> graypat2 */
|
||||
ADD.W %D4,%A1 /* %A1 := %A1 + sRow */
|
||||
DBF %D3,NxtRow /* UNTIL sHei < 0 */
|
||||
|
||||
/* Exit */
|
||||
Exit: RTS /* Return */
|
||||
|
||||
|
||||
/* <PUT YOUR VALUES FOR INIT TABLE, OTHER TABLES, ETC. HERE IF NEEDED> */
|
||||
|
||||
/* END PrimaryInit */
|
||||
|
||||
|
||||
|
||||
|
|
@ -18,26 +18,28 @@ _sRsrc_Board:
|
|||
OSLstEntry sRsrcType,_BoardType /* offset to board descriptor */
|
||||
OSLstEntry sRsrcName,_BoardName /* offset to name of board */
|
||||
DatLstEntry boardId,NuBusFPGAID /* board ID # (assigned by DTS) */
|
||||
/* OSLstEntry PrimaryInit,_sPInitRec */ /* offset to PrimaryInit exec blk */
|
||||
OSLstEntry primaryInit,_sPInitRec /* offset to PrimaryInit exec blk */
|
||||
OSLstEntry vendorInfo,_VendorInfo /* offset to vendor info record */
|
||||
/* OSLstEntry SecondaryInit,_sSInitRec */ /* offset to SecondaryInit block */
|
||||
OSLstEntry sRsrcVidNames, _VModeName
|
||||
.long EndOfList
|
||||
|
||||
_BoardType:
|
||||
.short catBoard /* board sResource */
|
||||
.short typBoard
|
||||
.short typeBoard
|
||||
.short 0
|
||||
.short 0
|
||||
|
||||
_BoardName:
|
||||
.String "SBusFPGA Video" /* name of board */
|
||||
_BoardName:
|
||||
.string "NuBusFPGA Video\0" /* name of board */
|
||||
ALIGN 2
|
||||
|
||||
/* _VidICON ; optional icon, not needed */
|
||||
/* _sVidNameDir ; optional name(s), not needed */
|
||||
|
||||
_sPInitRec:
|
||||
.long _EndsPInitRec-_sPInitRec /* physical block size */
|
||||
/* INCLUDE "NuBusFPGAPrimaryInit.a" /* the header/code */ */
|
||||
.include "NuBusFPGAPrimaryInit.s" /* the header/code */
|
||||
ALIGN 2
|
||||
_EndsPInitRec:
|
||||
|
||||
|
|
@ -47,34 +49,54 @@ _EndsPInitRec:
|
|||
/* ALIGN 2 */
|
||||
/* _EndsSInitRec */
|
||||
|
||||
ALIGN 2
|
||||
_VendorInfo:
|
||||
OSLstEntry vendorId,_VendorId /* offset to vendor ID */
|
||||
OSLstEntry serialNum,_SerialNum /* offset to revision */
|
||||
OSLstEntry revLevel,_RevLevel /* offset to revision */
|
||||
OSLstEntry partNum,_PartNum /* offset to part number record */
|
||||
OSLstEntry date,_Date /* offset to ROM build date */
|
||||
.long EndOfList
|
||||
|
||||
_VendorId:
|
||||
.string "Romain Dolbeau" /* vendor ID */
|
||||
.string "Romain Dolbeau\0" /* vendor ID */
|
||||
_SerialNum:
|
||||
.string "0000000001\0" /* serial number */
|
||||
_RevLevel:
|
||||
.string "NuBusFPGA V1.0" /* revision level */
|
||||
.string "NuBusFPGA V1.0\0" /* revision level */
|
||||
_PartNum:
|
||||
.string "Part Number" /* part number */
|
||||
.string "Part Number\0" /* part number */
|
||||
_Date:
|
||||
.string "&SysDate" /* date */
|
||||
.string "&SysDate" /* date */
|
||||
|
||||
ALIGN 2
|
||||
|
||||
_VModeName:
|
||||
OSLstEntry sRsrc_VidS8, _ScreenNameVidS8
|
||||
DatLstEntry endOfList, 0
|
||||
|
||||
ALIGN 2
|
||||
_ScreenNameVidS8:
|
||||
.long _ScreenNameVidS8End - _ScreenNameVidS8
|
||||
.word 0
|
||||
.string "That one resolution\0"
|
||||
_ScreenNameVidS8End:
|
||||
|
||||
ALIGN 2
|
||||
_sRsrc_VidS8:
|
||||
OSLstEntry sRsrcType,_VideoType /* video type descriptor */
|
||||
OSLstEntry sRsrcName,_VideoName /* offset to driver name string */
|
||||
/* OSLstEntry sRsrcDrvrDir,_VidDrvrDir ; offset to driver directory */
|
||||
OSLstEntry sRsrcDrvrDir,_VidDrvrDir /* offset to driver directory */
|
||||
DatLstEntry sRsrcFlags,6 /* force 32 bits mode & open */
|
||||
DatLstEntry sRsrcHWDevId,1 /* hardware device ID */
|
||||
OSLstEntry MinorBaseOS,_MinorBase /* offset to frame buffer array */
|
||||
OSLstEntry MinorLength,_MinorLength /* offset to frame buffer length */
|
||||
OSLstEntry sGammaDir,_GammaDirS /* directory for 640x480 monitor */
|
||||
/* OSLstEntry sGammaDir,_GammaDirS /* directory for 640x480 monitor */
|
||||
/* Parameters */
|
||||
OSLstEntry firstVidMode,_EBMs /* offset to EightBitMode parms */
|
||||
.long EndOfList /* end of list */
|
||||
|
||||
ALIGN 2
|
||||
_VideoType:
|
||||
.short catDisplay /* <Category> */
|
||||
.short typeVideo /* <Type> */
|
||||
|
|
@ -88,49 +110,52 @@ _MinorBase:
|
|||
_MinorLength:
|
||||
.long defMinorLength /* frame buffer length */
|
||||
|
||||
/* _VidDrvrDir */
|
||||
/* OSLstEntry sMacOS68020,_sMacOS68020 driver directory for Mac OS */
|
||||
/* .long EndOfList */
|
||||
/* */
|
||||
/* _sMacOS68020 */
|
||||
/* .long _End020Drvr- sMacOS68020 ; physical block size */
|
||||
/* INCLUDE 'NuBusFPGADrvr.a' ; driver code */
|
||||
/* _End020Drvr */
|
||||
ALIGN 2
|
||||
_VidDrvrDir:
|
||||
OSLstEntry sMacOS68020,_DrvrMacOS68020 /* driver directory for Mac OS */
|
||||
.long EndOfList
|
||||
|
||||
ALIGN 2
|
||||
_DrvrMacOS68020:
|
||||
.long _End020Drvr-. /* physical block size */
|
||||
.include "NuBusFPGADrvr.s" /* driver code */
|
||||
.text
|
||||
_End020Drvr:
|
||||
|
||||
_GammaDirS: /* for the 640x480 monitor */
|
||||
OSLstEntry 128,_SmallGamma
|
||||
.long EndOfList
|
||||
|
||||
_SmallGamma:
|
||||
.long _EndSmallGamma-_SmallGamma
|
||||
.short SGammaResID
|
||||
.string "Small Gamma" /* Monitors name */
|
||||
ALIGN 2
|
||||
.short $0000 /* gVersion */
|
||||
.short DrHwNuBusFPGA /* gType */
|
||||
.short $0000 /* gFormulaSize */
|
||||
.short $0001 /* gChanCnt */
|
||||
.short $0100 /* gDataCnt */
|
||||
.short $0008 /* gChanWidth */
|
||||
.long $0005090B,$0E101315,$17191B1D,$1E202224
|
||||
.long $2527282A,$2C2D2F30,$31333436,$37383A3B
|
||||
.long $3C3E3F40,$42434445,$4748494A,$4B4D4E4F
|
||||
.long $50515254,$55565758,$595A5B5C,$5E5F6061
|
||||
.long $62636465,$66676869,$6A6B6C6D,$6E6F7071
|
||||
.long $72737475,$76777879,$7A7B7C7D,$7E7F8081
|
||||
.long $81828384,$85868788,$898A8B8C,$8C8D8E8F
|
||||
.long $90919293,$94959596,$9798999A,$9B9B9C9D
|
||||
.long $9E9FA0A1,$A1A2A3A4,$A5A6A6A7,$A8A9AAAB
|
||||
.long $ABACADAE,$AFB0B0B1,$B2B3B4B4,$B5B6B7B8
|
||||
.long $B8B9BABB,$BCBCBDBE,$BFC0C0C1,$C2C3C3C4
|
||||
.long $C5C6C7C7,$C8C9CACA,$CBCCCDCD,$CECFD0D0
|
||||
.long $D1D2D3D3,$D4D5D6D6,$D7D8D9D9,$DADBDCDC
|
||||
.long $DDDEDFDF,$E0E1E1E2,$E3E4E4E5,$E6E7E7E8
|
||||
.long $E9B9EAEB,$ECECEDEE,$EEEFF0F1,$F1F2F3F3
|
||||
.long $F4F5F5F6,$F7F8F8F9,$FAFAFBFC,$FCFDFEFF
|
||||
_EndSmallGamma:
|
||||
/* ALIGN 2 */
|
||||
/* _GammaDirS: */
|
||||
/* OSLstEntry 128,_SmallGamma */
|
||||
/* .long EndOfList */
|
||||
/* _SmallGamma: */
|
||||
/* .long _EndSmallGamma-_SmallGamma */
|
||||
/* .short SGammaResID */
|
||||
/* .string "Small Gamma" /* Monitors name */
|
||||
/* ALIGN 2 */
|
||||
/* .short 0x0000 /* gVersion */
|
||||
/* .short DrHwNuBusFPGA /* gType */
|
||||
/* .short 0x0000 /* gFormulaSize */
|
||||
/* .short 0x0001 /* gChanCnt */
|
||||
/* .short 0x0100 /* gDataCnt */
|
||||
/* .short 0x0008 /* gChanWidth */
|
||||
/* .long 0x0005090B,0x0E101315,0x17191B1D,0x1E202224
|
||||
.long 0x2527282A,0x2C2D2F30,0x31333436,0x37383A3B
|
||||
.long 0x3C3E3F40,0x42434445,0x4748494A,0x4B4D4E4F
|
||||
.long 0x50515254,0x55565758,0x595A5B5C,0x5E5F6061
|
||||
.long 0x62636465,0x66676869,0x6A6B6C6D,0x6E6F7071
|
||||
.long 0x72737475,0x76777879,0x7A7B7C7D,0x7E7F8081
|
||||
.long 0x81828384,0x85868788,0x898A8B8C,0x8C8D8E8F
|
||||
.long 0x90919293,0x94959596,0x9798999A,0x9B9B9C9D
|
||||
.long 0x9E9FA0A1,0xA1A2A3A4,0xA5A6A6A7,0xA8A9AAAB
|
||||
.long 0xABACADAE,0xAFB0B0B1,0xB2B3B4B4,0xB5B6B7B8
|
||||
.long 0xB8B9BABB,0xBCBCBDBE,0xBFC0C0C1,0xC2C3C3C4
|
||||
.long 0xC5C6C7C7,0xC8C9CACA,0xCBCCCDCD,0xCECFD0D0
|
||||
.long 0xD1D2D3D3,0xD4D5D6D6,0xD7D8D9D9,0xDADBDCDC
|
||||
.long 0xDDDEDFDF,0xE0E1E1E2,0xE3E4E4E5,0xE6E7E7E8
|
||||
.long 0xE9B9EAEB,0xECECEDEE,0xEEEFF0F1,0xF1F2F3F3
|
||||
.long 0xF4F5F5F6,0xF7F8F8F9,0xFAFAFBFC,0xFCFDFEFF */
|
||||
/* _EndSmallGamma: */
|
||||
|
||||
ALIGN 2
|
||||
_EBMs:
|
||||
OSLstEntry mVidParams,_EBVParms /* offset to vid parameters */
|
||||
DatLstEntry mPageCnt,Pages8s /* number of video pages */
|
||||
|
|
@ -139,21 +164,22 @@ _EBMs:
|
|||
_EBVParms:
|
||||
.long _EndEBVParms-_EBVParms /* physical block size */
|
||||
.long defmBaseOffset /* QuickDraw base offset ; vpBaseOffset */
|
||||
.short RB8s /* physRowBytes ; vpRowBytes */
|
||||
.short defmBounds_Ts,defmBounds_Ls,defmBounds_Bs,defmBounds_Rs /* vpBounds */
|
||||
.short defVersion /* bmVersion ; vpVersion */
|
||||
.short 0 /* packType not used ; vpPackType */
|
||||
.word RB8s /* physRowBytes ; vpRowBytes */
|
||||
.word defmBounds_Ts,defmBounds_Ls,defmBounds_Bs,defmBounds_Rs /* vpBounds */
|
||||
.word defVersion /* bmVersion ; vpVersion */
|
||||
.word 0 /* packType not used ; vpPackType */
|
||||
.long 0 /* packSize not used ; vpPackSize */
|
||||
.long defmHRes /* bmHRes */
|
||||
.long defmVRes /* bmVRes */
|
||||
.short ChunkyIndexed /* bmPixelType */
|
||||
.short 8 /* bmPixelSize */
|
||||
.short 1 /* bmCmpCount */
|
||||
.short 8 /* bmCmpSize */
|
||||
.word ChunkyIndexed /* bmPixelType */
|
||||
.word 8 /* bmPixelSize */
|
||||
.word 1 /* bmCmpCount */
|
||||
.word 8 /* bmCmpSize */
|
||||
.long defmPlaneBytes /* bmPlaneBytes */
|
||||
_EndEBVParms:
|
||||
|
||||
/* Declaration ROM directory at end */
|
||||
ALIGN 2
|
||||
DeclROMDir:
|
||||
OSLstEntry 0, _sRsrcDir
|
||||
.long DeclRomEnd-_sRsrcDir /* Length should be 0x824 */
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@
|
|||
source /opt/Xilinx/Vivado/2020.1/settings64.sh
|
||||
export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
|
||||
|
||||
python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.0 --sys-clk-freq 100e6
|
||||
python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.0 --goblin --goblin-res 1280x1024@60Hz --sys-clk-freq 100e6
|
||||
) 2>&1 | tee build_V1_0.log
|
||||
# --toby --toby-res 1280x1024@60Hz
|
||||
# --goblin --goblin-res 1280x1024@60Hz
|
||||
# --hdmi
|
||||
|
||||
grep -A10 'Design Timing Summary' build/ztex213_nubus_V1_0/gateware/ztex213_nubus_V1_0_timing.rpt
|
||||
|
|
|
|||
|
|
@ -0,0 +1,35 @@
|
|||
from migen import *
|
||||
|
||||
from litedram.frontend.dma import LiteDRAMDMAReader;
|
||||
|
||||
# LiteDRAMDFBMAReader --------------------------------------------------------------------------------
|
||||
# Hardwire the loop, uses control signals instead of CSRs
|
||||
|
||||
class LiteDRAMFBDMAReader(LiteDRAMDMAReader):
|
||||
def __init__(self, port, fifo_depth=16, default_base=0, default_length=0):
|
||||
LiteDRAMDMAReader.__init__(self = self, port = port, fifo_depth = fifo_depth, fifo_buffered = True, with_csr = False)
|
||||
|
||||
enable = self.enable = Signal(reset = 0)
|
||||
base = self.base = Signal(self.port.address_width, reset = default_base)
|
||||
offset = self.offset = Signal(self.port.address_width, reset = 0)
|
||||
length = self.length = Signal(self.port.address_width, reset = default_length)
|
||||
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
fsm = ResetInserter()(fsm)
|
||||
self.submodules.fsm = fsm
|
||||
self.comb += fsm.reset.eq(~enable)
|
||||
fsm.act("IDLE",
|
||||
NextValue(offset, 0),
|
||||
NextState("RUN"),
|
||||
)
|
||||
fsm.act("RUN",
|
||||
self.sink.valid.eq(1),
|
||||
self.sink.last.eq(offset == (length - 1)),
|
||||
self.sink.address.eq(base + offset),
|
||||
If(self.sink.ready,
|
||||
NextValue(offset, offset + 1),
|
||||
If(self.sink.last,
|
||||
NextValue(offset, 0)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,122 @@
|
|||
import os
|
||||
import math
|
||||
|
||||
from migen import *
|
||||
from migen.genlib.cdc import MultiReg
|
||||
|
||||
from litex.soc.interconnect.csr import *
|
||||
from litex.soc.interconnect import stream
|
||||
from litex.soc.cores.code_tmds import TMDSEncoder
|
||||
|
||||
from litex.build.io import SDROutput, DDROutput
|
||||
|
||||
from litex.soc.cores.video import *
|
||||
|
||||
|
||||
# FB Video Timing Generator ---------------------------------------------------------------------------
|
||||
# Same as the normal one except (a) _enable isn't a CSR
|
||||
|
||||
class FBVideoTimingGenerator(Module, AutoCSR):
|
||||
def __init__(self, default_video_timings="800x600@60Hz"):
|
||||
# Check / Get Video Timings (can be str or dict)
|
||||
if isinstance(default_video_timings, str):
|
||||
try:
|
||||
self.video_timings = vt = video_timings[default_video_timings]
|
||||
except KeyError:
|
||||
msg = [f"Video Timings {default_video_timings} not supported, availables:"]
|
||||
for video_timing in video_timings.keys():
|
||||
msg.append(f" - {video_timing} / {video_timings[video_timing]['pix_clk']/1e6:3.2f}MHz.")
|
||||
raise ValueError("\n".join(msg))
|
||||
else:
|
||||
self.video_timings = vt = default_video_timings
|
||||
|
||||
# MMAP Control/Status Registers.
|
||||
self._enable = Signal(reset = 0)
|
||||
|
||||
self._hres = CSRStorage(hbits, vt["h_active"])
|
||||
self._hsync_start = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"])
|
||||
self._hsync_end = CSRStorage(hbits, vt["h_active"] + vt["h_sync_offset"] + vt["h_sync_width"])
|
||||
self._hscan = CSRStorage(hbits, vt["h_active"] + vt["h_blanking"])
|
||||
|
||||
self._vres = CSRStorage(vbits, vt["v_active"])
|
||||
self._vsync_start = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"])
|
||||
self._vsync_end = CSRStorage(vbits, vt["v_active"] + vt["v_sync_offset"] + vt["v_sync_width"])
|
||||
self._vscan = CSRStorage(vbits, vt["v_active"] + vt["v_blanking"])
|
||||
|
||||
# Video Timing Source
|
||||
self.source = source = stream.Endpoint(video_timing_layout)
|
||||
|
||||
# # #
|
||||
|
||||
# Resynchronize Enable to Video clock domain.
|
||||
self.enable = enable = Signal()
|
||||
self.specials += MultiReg(self._enable, enable)
|
||||
|
||||
# Resynchronize Horizontal Timings to Video clock domain.
|
||||
self.hres = hres = Signal(hbits)
|
||||
self.hsync_start = hsync_start = Signal(hbits)
|
||||
self.hsync_end = hsync_end = Signal(hbits)
|
||||
self.hscan = hscan = Signal(hbits)
|
||||
self.specials += MultiReg(self._hres.storage, hres)
|
||||
self.specials += MultiReg(self._hsync_start.storage, hsync_start)
|
||||
self.specials += MultiReg(self._hsync_end.storage, hsync_end)
|
||||
self.specials += MultiReg(self._hscan.storage, hscan)
|
||||
|
||||
# Resynchronize Vertical Timings to Video clock domain.
|
||||
self.vres = vres = Signal(vbits)
|
||||
self.vsync_start = vsync_start = Signal(vbits)
|
||||
self.vsync_end = vsync_end = Signal(vbits)
|
||||
self.vscan = vscan = Signal(vbits)
|
||||
self.specials += MultiReg(self._vres.storage, vres)
|
||||
self.specials += MultiReg(self._vsync_start.storage, vsync_start)
|
||||
self.specials += MultiReg(self._vsync_end.storage, vsync_end)
|
||||
self.specials += MultiReg(self._vscan.storage, vscan)
|
||||
|
||||
# Generate timings.
|
||||
hactive = Signal()
|
||||
vactive = Signal()
|
||||
fsm = FSM(reset_state="IDLE")
|
||||
fsm = ResetInserter()(fsm)
|
||||
self.submodules.fsm = fsm
|
||||
self.comb += fsm.reset.eq(~enable)
|
||||
fsm.act("IDLE",
|
||||
NextValue(hactive, 0),
|
||||
NextValue(vactive, 0),
|
||||
NextValue(source.hres, hres),
|
||||
NextValue(source.vres, vres),
|
||||
NextValue(source.hcount, 0),
|
||||
NextValue(source.vcount, 0),
|
||||
NextState("RUN")
|
||||
)
|
||||
self.comb += source.de.eq(hactive & vactive) # DE when both HActive and VActive.
|
||||
self.sync += source.first.eq((source.hcount == 0) & (source.vcount == 0)),
|
||||
self.sync += source.last.eq( (source.hcount == hscan) & (source.vcount == vscan)),
|
||||
fsm.act("RUN",
|
||||
source.valid.eq(1),
|
||||
If(source.ready,
|
||||
# Increment HCount.
|
||||
NextValue(source.hcount, source.hcount + 1),
|
||||
# Generate HActive / HSync.
|
||||
If(source.hcount == 0, NextValue(hactive, 1)), # Start of HActive.
|
||||
If(source.hcount == hres, NextValue(hactive, 0)), # End of HActive.
|
||||
If(source.hcount == hsync_start, NextValue(source.hsync, 1)), # Start of HSync.
|
||||
If(source.hcount == hsync_end, NextValue(source.hsync, 0)), # End of HSync.
|
||||
# End of HScan.
|
||||
If(source.hcount == hscan,
|
||||
# Reset HCount.
|
||||
NextValue(source.hcount, 0),
|
||||
# Increment VCount.
|
||||
NextValue(source.vcount, source.vcount + 1),
|
||||
# Generate VActive / VSync.
|
||||
If(source.vcount == 0, NextValue(vactive, 1)), # Start of VActive.
|
||||
If(source.vcount == vres, NextValue(vactive, 0)), # End of HActive.
|
||||
If(source.vcount == vsync_start, NextValue(source.vsync, 1)), # Start of VSync.
|
||||
If(source.vcount == vsync_end, NextValue(source.vsync, 0)), # End of VSync.
|
||||
# End of VScan.
|
||||
If(source.vcount == vscan,
|
||||
# Reset VCount.
|
||||
NextValue(source.vcount, 0),
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,365 @@
|
|||
from migen import *
|
||||
from migen.genlib.fifo import *
|
||||
|
||||
from litex.soc.interconnect.csr import *
|
||||
from litex.soc.interconnect import stream
|
||||
from litex.soc.interconnect import wishbone
|
||||
from litex.soc.cores.code_tmds import TMDSEncoder
|
||||
|
||||
from litex.build.io import SDROutput, DDROutput
|
||||
|
||||
from litex.soc.cores.video import *
|
||||
|
||||
from fb_video import *
|
||||
|
||||
from math import ceil
|
||||
|
||||
cmap_layout = [
|
||||
("color", 2),
|
||||
("address", 8),
|
||||
("data", 8),
|
||||
]
|
||||
omap_layout = [
|
||||
("color", 2),
|
||||
("address", 2),
|
||||
("data", 8),
|
||||
]
|
||||
|
||||
def goblin_rounded_size(hres, vres):
|
||||
mib = int(ceil(((hres * vres) + 0) / 1048576))
|
||||
if (mib == 3):
|
||||
mib = 4
|
||||
if (mib > 4 and mib < 8):
|
||||
mib = 8
|
||||
if (mib > 8 or mib < 1):
|
||||
print(f"{mib} mebibytes framebuffer not supported")
|
||||
assert(False)
|
||||
return int(1048576 * mib)
|
||||
|
||||
class VideoFrameBuffer256c(Module, AutoCSR):
|
||||
"""Video FrameBuffer256c"""
|
||||
def __init__(self, dram_port, upd_clut_fifo = None, hres=800, vres=600, base=0x00000000, fifo_depth=65536, clock_domain="sys", clock_faster_than_sys=False):
|
||||
|
||||
print(f"FRAMEBUFFER: dram_port.data_width = {dram_port.data_width}, {hres}x{vres}, 0x{base:x}, in {clock_domain}, clock_faster_than_sys={clock_faster_than_sys}")
|
||||
|
||||
npixelsdiv8 = hres * vres // 8
|
||||
|
||||
# mode, as x in 2^x (so 1, 2, 4, 8 bits)
|
||||
# should only be changed while in reset
|
||||
self.mode = Signal(2, reset = 3)
|
||||
self.vblping = Signal(reset = 0)
|
||||
|
||||
self.vtg_sink = vtg_sink = stream.Endpoint(video_timing_layout)
|
||||
self.source = source = stream.Endpoint(video_data_layout)
|
||||
self.underflow = Signal()
|
||||
|
||||
#source_buf_ready = Signal()
|
||||
source_buf_valid = Signal()
|
||||
source_buf_de = Signal()
|
||||
source_buf_hsync = Signal()
|
||||
source_buf_vsync = Signal()
|
||||
data_buf = Signal(8)
|
||||
|
||||
#source_out_ready = Signal()
|
||||
source_out_valid = Signal()
|
||||
source_out_de = Signal()
|
||||
source_out_hsync = Signal()
|
||||
source_out_vsync = Signal()
|
||||
source_out_r = Signal(8)
|
||||
source_out_g = Signal(8)
|
||||
source_out_b = Signal(8)
|
||||
|
||||
# # #
|
||||
# First the Color Look-up Table (for all but 1 bit)
|
||||
# updated from the FIFO
|
||||
# 8-and-less-than-8-bits mode used the 2^x first entries
|
||||
clut = Array(Array(Signal(8, reset = (255-i)) for i in range(0, 256)) for j in range(0, 3))
|
||||
|
||||
upd_clut_fifo_dout = Record(cmap_layout)
|
||||
self.comb += upd_clut_fifo_dout.raw_bits().eq(upd_clut_fifo.dout)
|
||||
|
||||
vga_sync = getattr(self.sync, clock_domain)
|
||||
vga_sync += [
|
||||
If(upd_clut_fifo.readable,
|
||||
upd_clut_fifo.re.eq(1),
|
||||
clut[upd_clut_fifo_dout.color][upd_clut_fifo_dout.address].eq(upd_clut_fifo_dout.data),
|
||||
).Else(
|
||||
upd_clut_fifo.re.eq(0),
|
||||
)
|
||||
]
|
||||
|
||||
# # #
|
||||
|
||||
# Video DMA.
|
||||
from fb_dma import LiteDRAMFBDMAReader
|
||||
# length should be changed to match mode
|
||||
self.submodules.fb_dma = LiteDRAMFBDMAReader(dram_port,
|
||||
fifo_depth=fifo_depth//(dram_port.data_width//8),
|
||||
default_base = base,
|
||||
default_length = npixelsdiv8 * 8)
|
||||
|
||||
# If DRAM Data Width > 8-bit and Video clock is faster than sys_clk:
|
||||
# actually always use that case to simplify the design
|
||||
# if (dram_port.data_width > 8) and clock_faster_than_sys:
|
||||
# Do Clock Domain Crossing first...
|
||||
self.submodules.cdc = stream.ClockDomainCrossing([("data", dram_port.data_width)], cd_from="sys", cd_to=clock_domain)
|
||||
self.comb += self.fb_dma.source.connect(self.cdc.sink)
|
||||
# ... and then Data-Width Conversion.
|
||||
# we have 4 possible conversion and mux/connect the appropriate one
|
||||
self.submodules.conv8 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 8))
|
||||
self.submodules.conv4 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 4))
|
||||
self.submodules.conv2 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 2))
|
||||
self.submodules.conv1 = ClockDomainsRenamer({"sys": clock_domain})(stream.Converter(dram_port.data_width, 1))
|
||||
self.comb += Case(self.mode, {
|
||||
0x3: self.cdc.source.connect(self.conv8.sink),
|
||||
0x2: self.cdc.source.connect(self.conv4.sink),
|
||||
0x1: self.cdc.source.connect(self.conv2.sink),
|
||||
0x0: self.cdc.source.connect(self.conv1.sink),
|
||||
})
|
||||
|
||||
# Video Generation.
|
||||
# buffered by 1 cycle to accomodate the look-ups
|
||||
self.comb += [
|
||||
vtg_sink.ready.eq(1),
|
||||
If(vtg_sink.valid & vtg_sink.de,
|
||||
Case(self.mode, {
|
||||
0x3: [ source_buf_valid.eq(self.conv8.source.valid),
|
||||
self.conv8.source.connect(source, keep={"ready"}),
|
||||
data_buf.eq(self.conv8.source.data),
|
||||
],
|
||||
0x2: [ source_buf_valid.eq(self.conv4.source.valid),
|
||||
self.conv4.source.connect(source, keep={"ready"}),
|
||||
data_buf.eq(Cat(self.conv4.source.data, Signal(4, reset = 0))),
|
||||
],
|
||||
0x1: [ source_buf_valid.eq(self.conv2.source.valid),
|
||||
self.conv2.source.connect(source, keep={"ready"}),
|
||||
data_buf.eq(Cat(self.conv2.source.data, Signal(6, reset = 0))),
|
||||
],
|
||||
0x0: [ source_buf_valid.eq(self.conv1.source.valid),
|
||||
self.conv1.source.connect(source, keep={"ready"}),
|
||||
data_buf.eq(Replicate(self.conv2.source.data, 8)),
|
||||
],
|
||||
}),
|
||||
vtg_sink.ready.eq(source_buf_valid & source.ready),
|
||||
),
|
||||
source_buf_de.eq(vtg_sink.de),
|
||||
source_buf_hsync.eq(vtg_sink.hsync),
|
||||
source_buf_vsync.eq(vtg_sink.vsync),
|
||||
]
|
||||
|
||||
vga_sync += [
|
||||
source_out_de.eq(source_buf_de),
|
||||
source_out_hsync.eq(source_buf_hsync),
|
||||
source_out_vsync.eq(source_buf_vsync),
|
||||
source_out_valid.eq(source_buf_valid),
|
||||
#source_buf_ready.eq(source_out_ready), # ready flow the other way
|
||||
If(source_buf_de,
|
||||
If(self.mode == 0x0,
|
||||
source_out_r.eq(data_buf),
|
||||
source_out_g.eq(data_buf),
|
||||
source_out_b.eq(data_buf)
|
||||
).Else(
|
||||
source_out_r.eq(clut[0][data_buf]),
|
||||
source_out_g.eq(clut[1][data_buf]),
|
||||
source_out_b.eq(clut[2][data_buf])
|
||||
)
|
||||
).Else(source_out_r.eq(0),
|
||||
source_out_g.eq(0),
|
||||
source_out_b.eq(0)
|
||||
) ]
|
||||
|
||||
self.comb += [
|
||||
source.de.eq(source_out_de),
|
||||
source.hsync.eq(source_out_hsync),
|
||||
source.vsync.eq(source_out_vsync),
|
||||
source.valid.eq(source_out_valid),
|
||||
#source_out_ready.eq(source.ready), # ready flow the other way
|
||||
source.r.eq(source_out_r),
|
||||
source.g.eq(source_out_g),
|
||||
source.b.eq(source_out_b),
|
||||
]
|
||||
|
||||
# Underflow.
|
||||
self.comb += self.underflow.eq(~source.valid)
|
||||
|
||||
# track mode changes
|
||||
# in sys cd, not vga cd, as that's where the DMA runs
|
||||
# whenever the mode change, we fully reset the DMA
|
||||
# (we also need to reset the VTG at the same time)
|
||||
old_mode = Signal(2, reset = 3)
|
||||
force_reset = Signal(reset = 0)
|
||||
finish_reset = Signal(reset = 0)
|
||||
old_enable = Signal()
|
||||
self.sync += [
|
||||
old_mode.eq(self.mode),
|
||||
If(old_mode != self.mode,
|
||||
force_reset.eq(1),),
|
||||
If(force_reset == 1,
|
||||
old_enable.eq(self.fb_dma.enable),
|
||||
self.fb_dma.enable.eq(0),
|
||||
self.fb_dma.length.eq(npixelsdiv8 << self.mode),
|
||||
force_reset.eq(0),
|
||||
finish_reset.eq(1),),
|
||||
If(finish_reset == 1,
|
||||
self.fb_dma.enable.eq(old_enable),
|
||||
finish_reset.eq(0)),
|
||||
]
|
||||
|
||||
# VBL handling
|
||||
# create a pulse in self.vlbping in sys at the end of the frame
|
||||
from migen.genlib.cdc import PulseSynchronizer
|
||||
old_last = Signal()
|
||||
vga_vblping = Signal()
|
||||
vga_sync += [
|
||||
old_last.eq(vtg_sink.last),
|
||||
If((vtg_sink.last == 1) & (old_last == 0),
|
||||
vga_vblping.eq(1),
|
||||
).Else(
|
||||
vga_vblping.eq(0)
|
||||
)
|
||||
]
|
||||
self.submodules.vbl_ps = PulseSynchronizer(idomain = clock_domain, odomain = "sys")
|
||||
self.comb += self.vbl_ps.i.eq(vga_vblping)
|
||||
self.comb += self.vblping.eq(self.vbl_ps.o)
|
||||
|
||||
class goblin(Module, AutoCSR):
|
||||
def __init__(self, soc, phy=None, timings = None, clock_domain="sys"):
|
||||
|
||||
# 2 bits for color (0/r, 1/g, 2/b), 8 for @ and 8 for value
|
||||
self.submodules.upd_cmap_fifo = upd_cmap_fifo = ClockDomainsRenamer({"read": "vga", "write": "sys"})(AsyncFIFOBuffered(width=layout_len(cmap_layout), depth=8))
|
||||
upd_cmap_fifo_din = Record(cmap_layout)
|
||||
self.comb += self.upd_cmap_fifo.din.eq(upd_cmap_fifo_din.raw_bits())
|
||||
|
||||
name = "video_framebuffer"
|
||||
# near duplicate of plaform.add_video_framebuffer
|
||||
# Video Timing Generator.
|
||||
vtg = FBVideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
|
||||
vtg = ClockDomainsRenamer(clock_domain)(vtg)
|
||||
setattr(self.submodules, f"{name}_vtg", vtg)
|
||||
|
||||
# Video FrameBuffer.
|
||||
timings = timings if isinstance(timings, str) else timings[0]
|
||||
base = soc.mem_map.get(name)
|
||||
print(f"goblin: visible memory at {base:x}")
|
||||
hres = int(timings.split("@")[0].split("x")[0])
|
||||
vres = int(timings.split("@")[0].split("x")[1])
|
||||
freq = vtg.video_timings["pix_clk"]
|
||||
print(f"goblin: using {hres} x {vres}, {freq/1e6} MHz pixclk")
|
||||
vfb = VideoFrameBuffer256c(dram_port = soc.sdram.crossbar.get_port(),
|
||||
upd_clut_fifo = upd_cmap_fifo,
|
||||
hres = hres,
|
||||
vres = vres,
|
||||
base = base,
|
||||
clock_domain = clock_domain,
|
||||
clock_faster_than_sys = (vtg.video_timings["pix_clk"] > soc.sys_clk_freq))
|
||||
setattr(self.submodules, name, vfb)
|
||||
|
||||
# Connect Video Timing Generator to Video FrameBuffer.
|
||||
self.comb += vtg.source.connect(vfb.vtg_sink)
|
||||
|
||||
# Connect Video FrameBuffer to Video PHY.
|
||||
self.comb += vfb.source.connect(phy if isinstance(phy, stream.Endpoint) else phy.sink)
|
||||
|
||||
# Constants.
|
||||
soc.add_constant("VIDEO_FRAMEBUFFER_BASE", base)
|
||||
soc.add_constant("VIDEO_FRAMEBUFFER_HRES", hres)
|
||||
soc.add_constant("VIDEO_FRAMEBUFFER_VRES", vres)
|
||||
|
||||
# goblin registers
|
||||
# struct bt_regs {
|
||||
# u_int bt_addr; /* map address register */
|
||||
# u_int bt_cmap; /* colormap data register */
|
||||
# u_int bt_ctrl; /* control register */
|
||||
# u_int bt_omap; /* overlay (cursor) map register */
|
||||
# };
|
||||
|
||||
self.bus = bus = wishbone.Interface()
|
||||
|
||||
# current cmap logic for the goblin, similar to the cg6, minus the HW cursor
|
||||
|
||||
bt_mode = Signal(4, reset = 0) # 0 is 3, 2 is 0, 4 is 1, 8 is 2, and bit depth is 2^
|
||||
bt_addr = Signal(8, reset = 0)
|
||||
bt_cmap_state = Signal(2, reset = 0)
|
||||
m_vbl_disable = Signal(reset = 1)
|
||||
|
||||
vbl_signal = Signal(reset = 0)
|
||||
vbl_irq = soc.platform.request("nmrq_3v3_n")
|
||||
self.comb += vbl_irq.eq(~vbl_signal | m_vbl_disable) # active low
|
||||
|
||||
#self.comb += Case(bt_mode, {
|
||||
# 0x0: self.video_framebuffer.mode.eq(3),
|
||||
# 0x2: self.video_framebuffer.mode.eq(0),
|
||||
# 0x4: self.video_framebuffer.mode.eq(1),
|
||||
# 0x8: self.video_framebuffer.mode.eq(2),
|
||||
# })
|
||||
|
||||
self.submodules.wishbone_fsm = wishbone_fsm = FSM(reset_state = "Reset")
|
||||
wishbone_fsm.act("Reset",
|
||||
NextValue(bus.ack, 0),
|
||||
NextState("Idle"))
|
||||
wishbone_fsm.act("Idle",
|
||||
If(bus.cyc & bus.stb & bus.we & ~bus.ack & upd_cmap_fifo.writable, #write
|
||||
# FIXME: should check for prefix?
|
||||
Case(bus.adr[0:18], {
|
||||
# gobofb_mode
|
||||
0x0: [ NextValue(bt_mode, bus.dat_w[0:8]), ],
|
||||
# gobofb_lut_addr
|
||||
0x5: [ NextValue(bt_addr, bus.dat_w[0:8]),
|
||||
NextValue(bt_cmap_state, 0),
|
||||
],
|
||||
# gobofb_lut
|
||||
0x6: [ upd_cmap_fifo.we.eq(1),
|
||||
upd_cmap_fifo_din.color.eq(bt_cmap_state),
|
||||
upd_cmap_fifo_din.address.eq(bt_addr),
|
||||
upd_cmap_fifo_din.data.eq(bus.dat_w[0:8]),
|
||||
Case(bt_cmap_state, {
|
||||
0: [ NextValue(bt_cmap_state, 1), ],
|
||||
1: [ NextValue(bt_cmap_state, 2), ],
|
||||
2: [ NextValue(bt_cmap_state, 0), NextValue(bt_addr, (bt_addr+1) & 0xFF), ],
|
||||
"default": NextValue(bt_cmap_state, 0),
|
||||
}),
|
||||
],
|
||||
# set vbl
|
||||
0x1: [ NextValue(m_vbl_disable, ~bus.dat_w[0:1]), ],
|
||||
# clear irq
|
||||
0x3: [ NextValue(vbl_signal, 0), ],
|
||||
"default": [],
|
||||
}),
|
||||
NextValue(bus.ack, 1),
|
||||
).Elif(bus.cyc & bus.stb & ~bus.we & ~bus.ack, #read
|
||||
Case(bus.adr[0:18], {
|
||||
# bt_addr
|
||||
0x0: [ NextValue(bus.dat_r, bt_mode), ],
|
||||
"default": [ NextValue(bus.dat_r, 0xDEADBEEF)],
|
||||
}),
|
||||
NextValue(bus.ack, 1),
|
||||
).Else(
|
||||
NextValue(bus.ack, 0),
|
||||
),
|
||||
)
|
||||
# mode switch logic
|
||||
old_bt_mode = Signal(4)
|
||||
vtg_reset_counter = Signal(4, reset = 0) # to put the VTG in reset for a few cyles so that the DMA can restart
|
||||
self.sync += [ old_bt_mode.eq(bt_mode),
|
||||
If(old_bt_mode != bt_mode,
|
||||
Case(bt_mode, {
|
||||
0x2: self.video_framebuffer.mode.eq(0),
|
||||
0x4: self.video_framebuffer.mode.eq(1),
|
||||
0x8: self.video_framebuffer.mode.eq(2),
|
||||
0x0: self.video_framebuffer.mode.eq(3),
|
||||
}),
|
||||
vtg_reset_counter.eq(15),
|
||||
vtg._enable.eq(0),),
|
||||
If(vtg_reset_counter == 1,
|
||||
vtg._enable.eq(1),),
|
||||
If(vtg_reset_counter > 0,
|
||||
vtg_reset_counter.eq(vtg_reset_counter - 1),),
|
||||
]
|
||||
|
||||
|
||||
# VBL logic
|
||||
self.sync += [
|
||||
If(self.video_framebuffer.vblping == 1,
|
||||
vbl_signal.eq(1),
|
||||
),]
|
||||
|
||||
|
|
@ -64,7 +64,7 @@ class NuBus(Module):
|
|||
i_grant = platform.request("grant"),
|
||||
o_tmoen = platform.request("tmoen"),
|
||||
o_NUBUS_AD_DIR = platform.request("nubus_ad_dir"),
|
||||
io_nub_nmrqn = platform.request("nmrq_3v3_n"),
|
||||
# io_nub_nmrqn = platform.request("nmrq_3v3_n"),
|
||||
# io_nub_spn = self.nubus_sp_n,
|
||||
# io_nub_spvn = self.nubus_spv_n,
|
||||
o_mem_valid = self.mem_valid,
|
||||
|
|
|
|||
|
|
@ -42,7 +42,8 @@ module nubus
|
|||
output tmoen,
|
||||
output NUBUS_AD_DIR,
|
||||
|
||||
inout nub_nmrqn, // Non-Master Request
|
||||
//inout nub_nmrqn, // Non-Master Request, handled in the Litex code
|
||||
|
||||
// inout nub_spn, // System Parity
|
||||
// inout nub_spvn, // System Parity Valid
|
||||
|
||||
|
|
@ -65,8 +66,8 @@ module nubus
|
|||
output mem_local,
|
||||
|
||||
// NuBus90 (unimplemented)
|
||||
input nub_clk2xn,
|
||||
inout nub_tm2n
|
||||
input nub_clk2xn,
|
||||
inout nub_tm2n
|
||||
);
|
||||
|
||||
`include "nubus.svh"
|
||||
|
|
@ -99,6 +100,13 @@ module nubus
|
|||
wire nub_adoe = slv_slave & slv_tm1n
|
||||
/*SLAVE read of card*/
|
||||
;
|
||||
|
||||
wire rqst_n, rqst_oe_n;
|
||||
|
||||
assign rqst_n = 'b1; // no master yet
|
||||
assign nub_rqstn = ~rqst_oe_n ? rqst_n : 'bZ;
|
||||
|
||||
|
||||
// Output to nubus the
|
||||
assign nub_adn = nub_adoe ? ~nub_ad : 'bZ;
|
||||
|
||||
|
|
@ -177,7 +185,7 @@ module nubus
|
|||
.nub_ackn_o(nub_ackn), // Achnowlege
|
||||
.nub_startn_o(nub_startn), // Transfer start
|
||||
.nub_rqstn_o(nub_rqstn), // Bus request
|
||||
.nub_rqstoen_o(nub_qstoen), // Bus request enable
|
||||
.nub_rqstoen_o(rqst_oe_n), // Bus request enable
|
||||
.drv_tmoen_o(drv_tmoen), // Transfer mode enable
|
||||
.drv_mstdn_o(drv_mstdn) // Guess: Slave sends /ACK. Master responds with /MSTDN, which allows slave to clear /ACK and listen for next transaction.
|
||||
);
|
||||
|
|
|
|||
|
|
@ -27,17 +27,66 @@ from migen.genlib.cdc import BusSynchronizer
|
|||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
from litex.soc.cores.video import VideoVGAPHY
|
||||
import toby_fb
|
||||
import goblin_fb
|
||||
|
||||
# Wishbone stuff
|
||||
from sbus_wb import WishboneDomainCrossingMaster
|
||||
from nubus_mem_wb import NuBus2Wishbone
|
||||
|
||||
# CRG ----------------------------------------------------------------------------------------------
|
||||
class _CRG_MINI_SIM(Module):
|
||||
def __init__(self, platform, sys_clk_freq,
|
||||
goblin=False,
|
||||
hdmi=False,
|
||||
pix_clk=0):
|
||||
self.clock_domains.cd_sys = ClockDomain()
|
||||
self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset, we don't want the delay after a warm reset)
|
||||
self.clock_domains.cd_nubus = ClockDomain() # 10 MHz NuBus, reset'ed by NuBus, native NuBus clock domain (25% duty cycle)
|
||||
self.clock_domains.cd_nubus90 = ClockDomain() # 20 MHz NuBus90, reset'ed by NuBus, native NuBus90 clock domain (25% duty cycle)
|
||||
|
||||
# # #
|
||||
clk48 = platform.request("clk48")
|
||||
###### explanations from betrusted-io/betrusted-soc/betrusted_soc.py
|
||||
# Note: below feature cannot be used because Litex appends this *after* platform commands! This causes the generated
|
||||
# clock derived constraints immediately below to fail, because .xdc file is parsed in-order, and the main clock needs
|
||||
# to be created before the derived clocks. Instead, we use the line afterwards.
|
||||
platform.add_platform_command("create_clock -name clk48 -period 20.8333 [get_nets clk48]")
|
||||
# The above constraint must strictly proceed the below create_generated_clock constraints in the .XDC file
|
||||
# This allows PLLs/MMCMEs to be placed anywhere and reference the input clock
|
||||
self.clk48_bufg = Signal()
|
||||
self.specials += Instance("BUFG", i_I=clk48, o_O=self.clk48_bufg)
|
||||
self.comb += self.cd_native.clk.eq(self.clk48_bufg)
|
||||
#self.cd_native.clk = clk48
|
||||
|
||||
clk_nubus = platform.request("clk_3v3_n")
|
||||
if (clk_nubus is None):
|
||||
print(" ***** ERROR ***** Can't find the NuBus Clock !!!!\n");
|
||||
assert(false)
|
||||
self.cd_nubus.clk = clk_nubus
|
||||
rst_nubus_n = platform.request("reset_3v3_n")
|
||||
self.comb += self.cd_nubus.rst.eq(~rst_nubus_n)
|
||||
platform.add_platform_command("create_clock -name nubus_clk -period 100.0 -waveform {{0.0 75.0}} [get_ports clk_3v3_n]")
|
||||
|
||||
clk2x_nubus = platform.request("clk2x_3v3_n")
|
||||
if (clk2x_nubus is None):
|
||||
print(" ***** ERROR ***** Can't find the NuBus90 Clock !!!!\n");
|
||||
assert(false)
|
||||
self.cd_nubus90.clk = clk2x_nubus
|
||||
self.comb += self.cd_nubus90.rst.eq(~rst_nubus_n)
|
||||
platform.add_platform_command("create_clock -name nubus90_clk -period 50.0 -waveform {{0.0 37.5}} [get_ports clk2x_3v3_n]")
|
||||
|
||||
num_adv = 0
|
||||
num_clk = 0
|
||||
|
||||
platform.add_platform_command("create_clock -name sysclk -period 20.8333 [get_nets clk48]")
|
||||
self.sys_bufg = Signal()
|
||||
self.specials += Instance("BUFG", i_I=clk48, o_O=self.sys_bufg)
|
||||
self.comb += self.cd_native.clk.eq(self.sys_bufg)
|
||||
|
||||
|
||||
class _CRG(Module):
|
||||
def __init__(self, platform, sys_clk_freq,
|
||||
toby=False,
|
||||
goblin=False,
|
||||
hdmi=False,
|
||||
pix_clk=0):
|
||||
self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by NuBus (via pll), SoC/Wishbone main clock
|
||||
|
|
@ -47,7 +96,7 @@ class _CRG(Module):
|
|||
self.clock_domains.cd_native = ClockDomain(reset_less=True) # 48MHz native, non-reset'ed (for power-on long delay, never reset, we don't want the delay after a warm reset)
|
||||
self.clock_domains.cd_nubus = ClockDomain() # 10 MHz NuBus, reset'ed by NuBus, native NuBus clock domain (25% duty cycle)
|
||||
self.clock_domains.cd_nubus90 = ClockDomain() # 20 MHz NuBus90, reset'ed by NuBus, native NuBus90 clock domain (25% duty cycle)
|
||||
if (toby):
|
||||
if (goblin):
|
||||
if (not hdmi):
|
||||
self.clock_domains.cd_vga = ClockDomain(reset_less=True)
|
||||
else:
|
||||
|
|
@ -122,7 +171,7 @@ class _CRG(Module):
|
|||
num_adv = num_adv + 1
|
||||
num_clk = 0
|
||||
|
||||
if (toby):
|
||||
if (goblin):
|
||||
self.submodules.video_pll = video_pll = S7MMCM(speedgrade=platform.speedgrade)
|
||||
video_pll.register_clkin(self.clk48_bufg, 48e6)
|
||||
if (not hdmi):
|
||||
|
|
@ -145,7 +194,7 @@ class _CRG(Module):
|
|||
|
||||
|
||||
class NuBusFPGA(SoCCore):
|
||||
def __init__(self, variant, version, sys_clk_freq, toby, hdmi, toby_res, **kwargs):
|
||||
def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, **kwargs):
|
||||
print(f"Building NuBusFPGA for board version {version}")
|
||||
|
||||
kwargs["cpu_type"] = "None"
|
||||
|
|
@ -157,16 +206,16 @@ class NuBusFPGA(SoCCore):
|
|||
|
||||
self.platform = platform = ztex213_nubus.Platform(variant = variant, version = version)
|
||||
|
||||
if (toby):
|
||||
hres = int(toby_res.split("@")[0].split("x")[0])
|
||||
vres = int(toby_res.split("@")[0].split("x")[1])
|
||||
toby_fb_size = toby_fb.toby_rounded_size(hres, vres)
|
||||
print(f"Reserving {toby_fb_size} bytes ({toby_fb_size//1048576} MiB) for the toby")
|
||||
if (goblin):
|
||||
hres = int(goblin_res.split("@")[0].split("x")[0])
|
||||
vres = int(goblin_res.split("@")[0].split("x")[1])
|
||||
goblin_fb_size = goblin_fb.goblin_rounded_size(hres, vres)
|
||||
print(f"Reserving {goblin_fb_size} bytes ({goblin_fb_size//1048576} MiB) for the goblin")
|
||||
else:
|
||||
hres = 0
|
||||
vres = 0
|
||||
toby_fb_size = 0
|
||||
# litex.soc.cores.video.video_timings.update(toby_fb.toby_timings)
|
||||
goblin_fb_size = 0
|
||||
# litex.soc.cores.video.video_timings.update(goblin_fb.goblin_timings)
|
||||
|
||||
SoCCore.__init__(self,
|
||||
platform=platform,
|
||||
|
|
@ -187,33 +236,17 @@ class NuBusFPGA(SoCCore):
|
|||
# in 24 bits it's only one megabyte, $s0 0000 through $sF FFFF
|
||||
# they are translated: '$s0 0000-$sF FFFF' to '$Fs00 0000-$Fs0F FFFF' (for s in range $9 through $E)
|
||||
self.wb_mem_map = wb_mem_map = {
|
||||
"toby_mem": 0x00000000, # up to 512 KiB of FB memory
|
||||
"csr" : 0x000D0000, # CSR in the middle of the first MB, oups
|
||||
"toby_bt" : 0x00080000, # BT for toby just before the ROM, 0x70000 long
|
||||
"rom": 0x000FF000, # ROM at the end of the first MB (4 KiB of it ATM)
|
||||
"goblin_mem": 0x00000000, # up to 8 MiB of FB memory
|
||||
"goblin_bt" : 0x00900000, # BT for goblin
|
||||
"csr" : 0x00a00000, # CSR
|
||||
"rom": 0x00FF8000, # ROM at the end (32 KiB of it ATM)
|
||||
"END OF FIRST MB" : 0x000FFFFF,
|
||||
"rom1": 0x001FF000, # ROM mirrored
|
||||
"rom2": 0x002FF000, # ROM mirrored
|
||||
"rom3": 0x003FF000, # ROM mirrored
|
||||
"rom4": 0x004FF000, # ROM mirrored
|
||||
"rom5": 0x005FF000, # ROM mirrored
|
||||
"rom6": 0x006FF000, # ROM mirrored
|
||||
"rom7": 0x007FF000, # ROM mirrored
|
||||
"rom8": 0x008FF000, # ROM mirrored
|
||||
"toby_mem_dupl" : 0x00900000, # replicated FB memory
|
||||
"rom9": 0x009FF000, # ROM mirrored
|
||||
"roma": 0x00AFF000, # ROM mirrored
|
||||
"romb": 0x00BFF000, # ROM mirrored
|
||||
"romc": 0x00CFF000, # ROM mirrored
|
||||
"romd": 0x00DFF000, # ROM mirrored
|
||||
"rome": 0x00EFF000, # ROM mirrored
|
||||
"romf": 0x00FFF000, # ROM mirrored
|
||||
"END OF SLOT SPACE": 0x00FFFFFF,
|
||||
"main_ram": 0x80000000, # not directly reachable from NuBus
|
||||
"video_framebuffer": 0x80000000 + 0x10000000 - toby_fb_size, # Updated later
|
||||
"video_framebuffer": 0x80000000 + 0x10000000 - goblin_fb_size, # Updated later
|
||||
}
|
||||
self.mem_map.update(wb_mem_map)
|
||||
self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, toby=toby, pix_clk=litex.soc.cores.video.video_timings[toby_res]["pix_clk"])
|
||||
self.submodules.crg = _CRG(platform=platform, sys_clk_freq=sys_clk_freq, goblin=goblin, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"])
|
||||
|
||||
## add our custom timings after the clocks have been defined
|
||||
xdc_timings_filename = None;
|
||||
|
|
@ -236,24 +269,23 @@ class NuBusFPGA(SoCCore):
|
|||
#for i in range(len(rom)):
|
||||
# print(hex(rom[i]))
|
||||
#print("\n****************************************\n")
|
||||
self.add_ram("rom", origin=self.mem_map["rom"], size=2**12, contents=rom_data, mode="r") ### FIXME: round up the prom_data size & check for <= 2**12!
|
||||
# do we need to mirror the rom in *all* 16 mb ?
|
||||
self.bus.add_slave("romf", self.rom.bus, SoCRegion(origin=self.mem_map["romf"], size=2**12, mode="r"))
|
||||
#getattr(self,"rom").mem.init = rom_data
|
||||
#getattr(self,"rom").mem.depth = 2**16
|
||||
self.add_ram("rom", origin=self.mem_map["rom"], size=2**15, contents=rom_data, mode="r") ## 32 KiB, must match mmap
|
||||
|
||||
avail_sdram = 0
|
||||
#self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
||||
# memtype = "DDR3",
|
||||
# nphases = 4,
|
||||
# sys_clk_freq = sys_clk_freq)
|
||||
#self.add_sdram("sdram",
|
||||
# phy = self.ddrphy,
|
||||
# module = MT41J128M16(sys_clk_freq, "1:4"),
|
||||
# l2_cache_size = 0,
|
||||
#)
|
||||
#avail_sdram = self.bus.regions["main_ram"].size
|
||||
avail_sdram = 256 * 1024 * 1024
|
||||
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
|
||||
memtype = "DDR3",
|
||||
nphases = 4,
|
||||
sys_clk_freq = sys_clk_freq)
|
||||
self.add_sdram("sdram",
|
||||
phy = self.ddrphy,
|
||||
module = MT41J128M16(sys_clk_freq, "1:4"),
|
||||
l2_cache_size = 0,
|
||||
)
|
||||
avail_sdram = self.bus.regions["main_ram"].size
|
||||
from sdram_init import DDR3FBInit
|
||||
self.submodules.sdram_init = DDR3FBInit(sys_clk_freq=sys_clk_freq, bitslip=1, delay=25)
|
||||
self.bus.add_master(name="DDR3Init", master=self.sdram_init.bus)
|
||||
#avail_sdram = 256 * 1024 * 1024
|
||||
|
||||
self.submodules.leds = LedChaser(
|
||||
pads = platform.request_all("user_led"),
|
||||
|
|
@ -261,9 +293,9 @@ class NuBusFPGA(SoCCore):
|
|||
self.add_csr("leds")
|
||||
|
||||
base_fb = self.wb_mem_map["main_ram"] + avail_sdram - 1048576 # placeholder
|
||||
if (toby):
|
||||
if (avail_sdram >= toby_fb_size):
|
||||
avail_sdram = avail_sdram - toby_fb_size
|
||||
if (goblin):
|
||||
if (avail_sdram >= goblin_fb_size):
|
||||
avail_sdram = avail_sdram - goblin_fb_size
|
||||
base_fb = self.wb_mem_map["main_ram"] + avail_sdram
|
||||
self.wb_mem_map["video_framebuffer"] = base_fb
|
||||
else:
|
||||
|
|
@ -293,16 +325,14 @@ class NuBusFPGA(SoCCore):
|
|||
self.submodules.nubus = nubus.NuBus(platform=platform, cd_nubus="nubus")
|
||||
self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus))
|
||||
|
||||
self.add_ram("ram", origin=self.mem_map["toby_mem"], size=2**16, mode="rw")
|
||||
|
||||
if (toby):
|
||||
if (goblin):
|
||||
if (not hdmi):
|
||||
self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
|
||||
self.submodules.toby = toby_fb.toby(soc=self, phy=self.videophy, timings=toby_res, clock_domain="vga") # clock_domain for the VGA side, toby is running in cd_sys
|
||||
self.submodules.goblin = goblin_fb.goblin(soc=self, phy=self.videophy, timings=goblin_res, clock_domain="vga") # clock_domain for the VGA side, goblin is running in cd_sys
|
||||
else:
|
||||
self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi"), clock_domain="hdmi")
|
||||
self.submodules.toby = toby_fb.toby(soc=self, phy=self.videophy, timings=toby_res, clock_domain="hdmi") # clock_domain for the VGA side, toby is running in cd_sys
|
||||
self.bus.add_slave("toby_bt", self.toby.bus, SoCRegion(origin=self.mem_map.get("toby_bt", None), size=0x70000, cached=False))
|
||||
self.submodules.goblin = goblin_fb.goblin(soc=self, phy=self.videophy, timings=goblin_res, clock_domain="hdmi") # clock_domain for the VGA side, goblin is running in cd_sys
|
||||
self.bus.add_slave("goblin_bt", self.goblin.bus, SoCRegion(origin=self.mem_map.get("goblin_bt", None), size=0x1000, cached=False))
|
||||
|
||||
|
||||
def main():
|
||||
|
|
@ -311,9 +341,9 @@ def main():
|
|||
parser.add_argument("--variant", default="ztex2.13a", help="ZTex board variant (default ztex2.13a)")
|
||||
parser.add_argument("--version", default="V1.0", help="NuBusFPGA board version (default V1.0)")
|
||||
parser.add_argument("--sys-clk-freq", default=100e6, help="NuBusFPGA system clock (default 100e6 = 100 MHz)")
|
||||
parser.add_argument("--toby", action="store_true", help="add a toby framebuffer")
|
||||
parser.add_argument("--goblin", action="store_true", help="add a goblin framebuffer")
|
||||
parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA)")
|
||||
parser.add_argument("--toby-res", default="640x480@60Hz", help="Specify the toby resolution")
|
||||
parser.add_argument("--goblin-res", default="640x480@60Hz", help="Specify the goblin resolution")
|
||||
builder_args(parser)
|
||||
vivado_build_args(parser)
|
||||
args = parser.parse_args()
|
||||
|
|
@ -322,9 +352,9 @@ def main():
|
|||
variant=args.variant,
|
||||
version=args.version,
|
||||
sys_clk_freq=int(float(args.sys_clk_freq)),
|
||||
toby=args.toby,
|
||||
goblin=args.goblin,
|
||||
hdmi=args.hdmi,
|
||||
toby_res=args.toby_res)
|
||||
goblin_res=args.goblin_res)
|
||||
|
||||
version_for_filename = args.version.replace(".", "_")
|
||||
|
||||
|
|
|
|||
|
|
@ -262,7 +262,8 @@ F 1 "HDMI_A" H 7079 2505 50 0000 L CNN
|
|||
F 2 "For_SeeedStudio:HDMI_A_Amphenol_10029449-111" H 6675 2550 50 0001 C CNN
|
||||
F 3 "https://en.wikipedia.org/wiki/HDMI" H 6675 2550 50 0001 C CNN
|
||||
F 4 "10029449-111" H 6650 2550 50 0001 C CNN "MPN"
|
||||
F 5 "https://www2.mouser.com/ProductDetail/Amphenol-FCI/10029449-111RLF?qs=fmpTyLOWOey0HPdD9%2F%2FaXA%3D%3D" H 6650 2550 50 0001 C CNN "URL"
|
||||
F 5 "https://www2.mouser.com/ProductDetail/Amphenol-FCI/10029449-111RLF?qs=fmpTyLOWOey0HPdD9%2F%2FaXA%3D%3D" H 6650 2550 50 0001 C CNN "URL-ALT"
|
||||
F 6 "https://lcsc.com/product-detail/D-Sub-DVI-HDMI-Connectors_Amphenol-ICC-10029449-111RLF_C427307.html" H 6650 2550 50 0001 C CNN "URL"
|
||||
1 6650 2550
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,11 +1,11 @@
|
|||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.2+dfsg1-1~bpo9+1*
|
||||
G04 #@! TF.CreationDate,2022-01-29T10:57:36+01:00*
|
||||
G04 #@! TF.CreationDate,2022-02-05T15:09:40+01:00*
|
||||
G04 #@! TF.ProjectId,nubus-to-ztex,6e756275-732d-4746-9f2d-7a7465782e6b,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Profile,NP*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Jan 29 10:57:36 2022*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Feb 5 15:09:40 2022*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,12 +1,12 @@
|
|||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.2+dfsg1-1~bpo9+1*
|
||||
G04 #@! TF.CreationDate,2022-01-29T10:57:36+01:00*
|
||||
G04 #@! TF.CreationDate,2022-02-05T15:09:40+01:00*
|
||||
G04 #@! TF.ProjectId,nubus-to-ztex,6e756275-732d-4746-9f2d-7a7465782e6b,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Soldermask,Top*
|
||||
G04 #@! TF.FilePolarity,Negative*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Jan 29 10:57:36 2022*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Feb 5 15:09:40 2022*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.2+dfsg1-1~bpo9+1*
|
||||
G04 #@! TF.CreationDate,2022-01-29T10:57:36+01:00*
|
||||
G04 #@! TF.CreationDate,2022-02-05T15:09:40+01:00*
|
||||
G04 #@! TF.ProjectId,nubus-to-ztex,6e756275-732d-4746-9f2d-7a7465782e6b,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Paste,Top*
|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Jan 29 10:57:36 2022*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Feb 5 15:09:40 2022*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.2+dfsg1-1~bpo9+1*
|
||||
G04 #@! TF.CreationDate,2022-01-29T10:57:36+01:00*
|
||||
G04 #@! TF.CreationDate,2022-02-05T15:09:40+01:00*
|
||||
G04 #@! TF.ProjectId,nubus-to-ztex,6e756275-732d-4746-9f2d-7a7465782e6b,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Legend,Top*
|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Jan 29 10:57:36 2022*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Feb 5 15:09:40 2022*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.2+dfsg1-1~bpo9+1*
|
||||
G04 #@! TF.CreationDate,2022-01-29T10:57:36+01:00*
|
||||
G04 #@! TF.CreationDate,2022-02-05T15:09:40+01:00*
|
||||
G04 #@! TF.ProjectId,nubus-to-ztex,6e756275-732d-4746-9f2d-7a7465782e6b,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Copper,L2,Inr*
|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Jan 29 10:57:36 2022*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Feb 5 15:09:40 2022*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
|
|
@ -870,6 +870,16 @@ X183600000Y-71000000D03*
|
|||
X116300000Y-16437500D03*
|
||||
X246062500Y-59100000D03*
|
||||
X267000000Y-61050000D03*
|
||||
X244180000Y-99750000D03*
|
||||
X236450000Y-82730000D03*
|
||||
X254302500Y-45750000D03*
|
||||
X230600000Y-64600000D03*
|
||||
X170640000Y-21260000D03*
|
||||
X115850000Y-48950000D03*
|
||||
X158100000Y-92000000D03*
|
||||
X196200000Y-92480000D03*
|
||||
X196200000Y-89100000D03*
|
||||
X123800000Y-93000000D03*
|
||||
G04 #@! TO.N,+3V3*
|
||||
X256000000Y-22250000D03*
|
||||
X140112500Y-65000000D03*
|
||||
|
|
@ -1026,7 +1036,7 @@ X222362400Y-89060000D02*
|
|||
X218800000Y-89060000D01*
|
||||
D28*
|
||||
X256010000Y-87920000D02*
|
||||
X239420000Y-104510000D01*
|
||||
X244180000Y-99750000D01*
|
||||
X248850000Y-22250000D02*
|
||||
X248950000Y-22250000D01*
|
||||
X116600000Y-67800000D02*
|
||||
|
|
@ -1157,10 +1167,6 @@ X218240000Y-89620000D01*
|
|||
D28*
|
||||
X256000000Y-32734315D02*
|
||||
X256000000Y-31500000D01*
|
||||
D27*
|
||||
X132540000Y-33600000D02*
|
||||
X132540000Y-59210000D01*
|
||||
D28*
|
||||
X131600000Y-65900000D02*
|
||||
X132540000Y-64960000D01*
|
||||
X256220000Y-61875000D02*
|
||||
|
|
@ -1484,7 +1490,7 @@ X198190000Y-75210000D01*
|
|||
X145400000Y-88100000D02*
|
||||
X146900000Y-88100000D01*
|
||||
X252900000Y-82730000D02*
|
||||
X228692400Y-82730000D01*
|
||||
X236450000Y-82730000D01*
|
||||
X202250000Y-71000000D02*
|
||||
X202400000Y-71000000D01*
|
||||
X262640000Y-79355000D02*
|
||||
|
|
@ -1493,10 +1499,10 @@ X127500000Y-65900000D02*
|
|||
X123500000Y-65900000D01*
|
||||
D27*
|
||||
X123800000Y-94920000D02*
|
||||
X123800000Y-92000000D01*
|
||||
X123800000Y-93000000D01*
|
||||
D28*
|
||||
X255040000Y-46487500D02*
|
||||
X248840000Y-40287500D01*
|
||||
X254302500Y-45750000D01*
|
||||
D27*
|
||||
X146660000Y-94920000D02*
|
||||
X146660000Y-92000000D01*
|
||||
|
|
@ -1523,7 +1529,7 @@ X140550000Y-75450000D02*
|
|||
X140550000Y-75950000D01*
|
||||
D26*
|
||||
X196200000Y-97460000D02*
|
||||
X196200000Y-82592500D01*
|
||||
X196200000Y-92480000D01*
|
||||
D27*
|
||||
X208740000Y-59210000D02*
|
||||
X210000000Y-59210000D01*
|
||||
|
|
@ -1560,8 +1566,6 @@ X211060000Y-59210000D02*
|
|||
X212100000Y-60250000D01*
|
||||
X212100000Y-66400000D02*
|
||||
X207500000Y-71000000D01*
|
||||
X212100000Y-60250000D02*
|
||||
X212100000Y-66400000D01*
|
||||
X142700000Y-75950000D02*
|
||||
X146500000Y-79750000D01*
|
||||
X146500000Y-79750000D02*
|
||||
|
|
@ -1676,6 +1680,53 @@ X133620000Y-83900000D02*
|
|||
X128980000Y-79260000D01*
|
||||
X135152523Y-83900000D02*
|
||||
X133620000Y-83900000D01*
|
||||
X244180000Y-99750000D02*
|
||||
X239420000Y-104510000D01*
|
||||
X236450000Y-82730000D02*
|
||||
X228692400Y-82730000D01*
|
||||
X254302500Y-45750000D02*
|
||||
X248840000Y-40287500D01*
|
||||
X212100000Y-60250000D02*
|
||||
X212100000Y-66250000D01*
|
||||
X212100000Y-66250000D02*
|
||||
X228950000Y-66250000D01*
|
||||
X212100000Y-66250000D02*
|
||||
X212100000Y-66400000D01*
|
||||
X228950000Y-66250000D02*
|
||||
X230600000Y-64600000D01*
|
||||
X230600000Y-64600000D02*
|
||||
X230600000Y-64600000D01*
|
||||
D27*
|
||||
X170640000Y-21260000D02*
|
||||
X170640000Y-21260000D01*
|
||||
D28*
|
||||
X132540000Y-48950000D02*
|
||||
X115850000Y-48950000D01*
|
||||
D27*
|
||||
X132540000Y-33600000D02*
|
||||
X132540000Y-48950000D01*
|
||||
X132540000Y-48950000D02*
|
||||
X132540000Y-59210000D01*
|
||||
D28*
|
||||
X115850000Y-48950000D02*
|
||||
X115850000Y-48950000D01*
|
||||
X153000000Y-92000000D02*
|
||||
X158100000Y-92000000D01*
|
||||
X163150000Y-92000000D02*
|
||||
X158100000Y-92000000D01*
|
||||
X168250000Y-92000000D02*
|
||||
X163150000Y-92000000D01*
|
||||
D26*
|
||||
X158100000Y-92000000D02*
|
||||
X158100000Y-92000000D01*
|
||||
X196200000Y-89100000D02*
|
||||
X196200000Y-82592500D01*
|
||||
X196200000Y-92480000D02*
|
||||
X196200000Y-89100000D01*
|
||||
D27*
|
||||
X123800000Y-93000000D02*
|
||||
X123800000Y-92000000D01*
|
||||
D28*
|
||||
G04 #@! TO.N,SHIELD*
|
||||
X267690000Y-46360000D02*
|
||||
X267920000Y-46130000D01*
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
G04 #@! TF.GenerationSoftware,KiCad,Pcbnew,5.0.2+dfsg1-1~bpo9+1*
|
||||
G04 #@! TF.CreationDate,2022-01-29T10:57:36+01:00*
|
||||
G04 #@! TF.CreationDate,2022-02-05T15:09:40+01:00*
|
||||
G04 #@! TF.ProjectId,nubus-to-ztex,6e756275-732d-4746-9f2d-7a7465782e6b,rev?*
|
||||
G04 #@! TF.SameCoordinates,Original*
|
||||
G04 #@! TF.FileFunction,Copper,L3,Inr*
|
||||
G04 #@! TF.FilePolarity,Positive*
|
||||
%FSLAX46Y46*%
|
||||
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Jan 29 10:57:36 2022*
|
||||
G04 Created by KiCad (PCBNEW 5.0.2+dfsg1-1~bpo9+1) date Sat Feb 5 15:09:40 2022*
|
||||
%MOMM*%
|
||||
%LPD*%
|
||||
G01*
|
||||
|
|
@ -864,6 +864,16 @@ X183600000Y-71000000D03*
|
|||
X116300000Y-16437500D03*
|
||||
X246062500Y-59100000D03*
|
||||
X267000000Y-61050000D03*
|
||||
X244180000Y-99750000D03*
|
||||
X236450000Y-82730000D03*
|
||||
X254302500Y-45750000D03*
|
||||
X230600000Y-64600000D03*
|
||||
X170640000Y-21260000D03*
|
||||
X115850000Y-48950000D03*
|
||||
X158100000Y-92000000D03*
|
||||
X196200000Y-92480000D03*
|
||||
X196200000Y-89100000D03*
|
||||
X123800000Y-93000000D03*
|
||||
G04 #@! TO.N,+3V3*
|
||||
X256000000Y-22250000D03*
|
||||
X140112500Y-65000000D03*
|
||||
|
|
@ -1501,6 +1511,22 @@ X256215874Y-88955000D01*
|
|||
X256596280Y-88797431D01*
|
||||
X256873000Y-88520711D01*
|
||||
X256873000Y-93473000D01*
|
||||
X196507271Y-93473000D01*
|
||||
X196786280Y-93357431D01*
|
||||
X197077431Y-93066280D01*
|
||||
X197235000Y-92685874D01*
|
||||
X197235000Y-92274126D01*
|
||||
X197077431Y-91893720D01*
|
||||
X196786280Y-91602569D01*
|
||||
X196405874Y-91445000D01*
|
||||
X195994126Y-91445000D01*
|
||||
X195613720Y-91602569D01*
|
||||
X195322569Y-91893720D01*
|
||||
X195165000Y-92274126D01*
|
||||
X195165000Y-92685874D01*
|
||||
X195322569Y-93066280D01*
|
||||
X195613720Y-93357431D01*
|
||||
X195892729Y-93473000D01*
|
||||
X189311200Y-93473000D01*
|
||||
X189311200Y-90419999D01*
|
||||
X216722560Y-90419999D01*
|
||||
|
|
@ -1554,11 +1580,30 @@ X189325132Y-89749999D01*
|
|||
X189311200Y-89679957D01*
|
||||
X189311200Y-89679954D01*
|
||||
X189269936Y-89472504D01*
|
||||
X189264067Y-89463720D01*
|
||||
X189158597Y-89305874D01*
|
||||
X189152424Y-89296635D01*
|
||||
X189152422Y-89296633D01*
|
||||
X189112746Y-89237254D01*
|
||||
X189053367Y-89197578D01*
|
||||
X188749915Y-88894126D01*
|
||||
X195165000Y-88894126D01*
|
||||
X195165000Y-89305874D01*
|
||||
X195322569Y-89686280D01*
|
||||
X195613720Y-89977431D01*
|
||||
X195994126Y-90135000D01*
|
||||
X196405874Y-90135000D01*
|
||||
X196786280Y-89977431D01*
|
||||
X197077431Y-89686280D01*
|
||||
X197235000Y-89305874D01*
|
||||
X197235000Y-88894126D01*
|
||||
X197077431Y-88513720D01*
|
||||
X196786280Y-88222569D01*
|
||||
X196405874Y-88065000D01*
|
||||
X195994126Y-88065000D01*
|
||||
X195613720Y-88222569D01*
|
||||
X195322569Y-88513720D01*
|
||||
X195165000Y-88894126D01*
|
||||
X188749915Y-88894126D01*
|
||||
X187309915Y-87454126D01*
|
||||
X252815000Y-87454126D01*
|
||||
X252815000Y-87865874D01*
|
||||
|
|
@ -1605,7 +1650,38 @@ X183644126Y-86035000D01*
|
|||
X183879212Y-86035000D01*
|
||||
X187888801Y-90044590D01*
|
||||
X187888801Y-93473000D01*
|
||||
X124724353Y-93473000D01*
|
||||
X124835000Y-93205874D01*
|
||||
X124835000Y-92794126D01*
|
||||
X124677431Y-92413720D01*
|
||||
X124386280Y-92122569D01*
|
||||
X124005874Y-91965000D01*
|
||||
X123594126Y-91965000D01*
|
||||
X123213720Y-92122569D01*
|
||||
X122922569Y-92413720D01*
|
||||
X122765000Y-92794126D01*
|
||||
X122765000Y-93205874D01*
|
||||
X122875647Y-93473000D01*
|
||||
X113726847Y-93473000D01*
|
||||
X113724827Y-91794126D01*
|
||||
X157065000Y-91794126D01*
|
||||
X157065000Y-92205874D01*
|
||||
X157222569Y-92586280D01*
|
||||
X157513720Y-92877431D01*
|
||||
X157894126Y-93035000D01*
|
||||
X158305874Y-93035000D01*
|
||||
X158686280Y-92877431D01*
|
||||
X158977431Y-92586280D01*
|
||||
X159135000Y-92205874D01*
|
||||
X159135000Y-91794126D01*
|
||||
X158977431Y-91413720D01*
|
||||
X158686280Y-91122569D01*
|
||||
X158305874Y-90965000D01*
|
||||
X157894126Y-90965000D01*
|
||||
X157513720Y-91122569D01*
|
||||
X157222569Y-91413720D01*
|
||||
X157065000Y-91794126D01*
|
||||
X113724827Y-91794126D01*
|
||||
X113719388Y-87274126D01*
|
||||
X114165000Y-87274126D01*
|
||||
X114165000Y-87685874D01*
|
||||
|
|
@ -1854,6 +1930,16 @@ X186027431Y-83486280D01*
|
|||
X186185000Y-83105874D01*
|
||||
X186185000Y-82694126D01*
|
||||
X186114584Y-82524126D01*
|
||||
X235415000Y-82524126D01*
|
||||
X235415000Y-82935874D01*
|
||||
X235572569Y-83316280D01*
|
||||
X235863720Y-83607431D01*
|
||||
X236244126Y-83765000D01*
|
||||
X236655874Y-83765000D01*
|
||||
X237036280Y-83607431D01*
|
||||
X237327431Y-83316280D01*
|
||||
X237485000Y-82935874D01*
|
||||
X237485000Y-82524126D01*
|
||||
X251865000Y-82524126D01*
|
||||
X251865000Y-82935874D01*
|
||||
X252022569Y-83316280D01*
|
||||
|
|
@ -1871,6 +1957,14 @@ X252694126Y-81695000D01*
|
|||
X252313720Y-81852569D01*
|
||||
X252022569Y-82143720D01*
|
||||
X251865000Y-82524126D01*
|
||||
X237485000Y-82524126D01*
|
||||
X237327431Y-82143720D01*
|
||||
X237036280Y-81852569D01*
|
||||
X236655874Y-81695000D01*
|
||||
X236244126Y-81695000D01*
|
||||
X235863720Y-81852569D01*
|
||||
X235572569Y-82143720D01*
|
||||
X235415000Y-82524126D01*
|
||||
X186114584Y-82524126D01*
|
||||
X186027431Y-82313720D01*
|
||||
X185736280Y-82022569D01*
|
||||
|
|
@ -2536,6 +2630,25 @@ X117833993Y-65288864D01*
|
|||
X117544457Y-64855543D01*
|
||||
X117461331Y-64800000D01*
|
||||
X117544457Y-64744457D01*
|
||||
X117778540Y-64394126D01*
|
||||
X229565000Y-64394126D01*
|
||||
X229565000Y-64805874D01*
|
||||
X229722569Y-65186280D01*
|
||||
X230013720Y-65477431D01*
|
||||
X230394126Y-65635000D01*
|
||||
X230805874Y-65635000D01*
|
||||
X231186280Y-65477431D01*
|
||||
X231477431Y-65186280D01*
|
||||
X231635000Y-64805874D01*
|
||||
X231635000Y-64394126D01*
|
||||
X231477431Y-64013720D01*
|
||||
X231186280Y-63722569D01*
|
||||
X230805874Y-63565000D01*
|
||||
X230394126Y-63565000D01*
|
||||
X230013720Y-63722569D01*
|
||||
X229722569Y-64013720D01*
|
||||
X229565000Y-64394126D01*
|
||||
X117778540Y-64394126D01*
|
||||
X117833993Y-64311136D01*
|
||||
X117935664Y-63800000D01*
|
||||
X117833993Y-63288864D01*
|
||||
|
|
@ -3218,6 +3331,25 @@ X125163720Y-51466589D01*
|
|||
X124872569Y-51757740D01*
|
||||
X124715000Y-52138146D01*
|
||||
X113677107Y-52138146D01*
|
||||
X113673022Y-48744126D01*
|
||||
X114815000Y-48744126D01*
|
||||
X114815000Y-49155874D01*
|
||||
X114972569Y-49536280D01*
|
||||
X115263720Y-49827431D01*
|
||||
X115644126Y-49985000D01*
|
||||
X116055874Y-49985000D01*
|
||||
X116436280Y-49827431D01*
|
||||
X116727431Y-49536280D01*
|
||||
X116885000Y-49155874D01*
|
||||
X116885000Y-48744126D01*
|
||||
X116727431Y-48363720D01*
|
||||
X116436280Y-48072569D01*
|
||||
X116055874Y-47915000D01*
|
||||
X115644126Y-47915000D01*
|
||||
X115263720Y-48072569D01*
|
||||
X114972569Y-48363720D01*
|
||||
X114815000Y-48744126D01*
|
||||
X113673022Y-48744126D01*
|
||||
X113670648Y-46771168D01*
|
||||
X124565000Y-46771168D01*
|
||||
X124565000Y-47182916D01*
|
||||
|
|
@ -3237,6 +3369,25 @@ X125013720Y-46099611D01*
|
|||
X124722569Y-46390762D01*
|
||||
X124565000Y-46771168D01*
|
||||
X113670648Y-46771168D01*
|
||||
X113669172Y-45544126D01*
|
||||
X253267500Y-45544126D01*
|
||||
X253267500Y-45955874D01*
|
||||
X253425069Y-46336280D01*
|
||||
X253716220Y-46627431D01*
|
||||
X254096626Y-46785000D01*
|
||||
X254508374Y-46785000D01*
|
||||
X254888780Y-46627431D01*
|
||||
X255179931Y-46336280D01*
|
||||
X255337500Y-45955874D01*
|
||||
X255337500Y-45544126D01*
|
||||
X255179931Y-45163720D01*
|
||||
X254888780Y-44872569D01*
|
||||
X254508374Y-44715000D01*
|
||||
X254096626Y-44715000D01*
|
||||
X253716220Y-44872569D01*
|
||||
X253425069Y-45163720D01*
|
||||
X253267500Y-45544126D01*
|
||||
X113669172Y-45544126D01*
|
||||
X113667079Y-43804500D01*
|
||||
X124565000Y-43804500D01*
|
||||
X124565000Y-44216248D01*
|
||||
|
|
@ -4173,7 +4324,18 @@ X153505874Y-23035000D01*
|
|||
X153886280Y-22877431D01*
|
||||
X154177431Y-22586280D01*
|
||||
X154335000Y-22205874D01*
|
||||
X154335000Y-22044126D01*
|
||||
X154335000Y-21794126D01*
|
||||
X154177431Y-21413720D01*
|
||||
X153886280Y-21122569D01*
|
||||
X153721044Y-21054126D01*
|
||||
X169605000Y-21054126D01*
|
||||
X169605000Y-21465874D01*
|
||||
X169762569Y-21846280D01*
|
||||
X170053720Y-22137431D01*
|
||||
X170434126Y-22295000D01*
|
||||
X170845874Y-22295000D01*
|
||||
X171226280Y-22137431D01*
|
||||
X171319585Y-22044126D01*
|
||||
X245215000Y-22044126D01*
|
||||
X245215000Y-22455874D01*
|
||||
X245372569Y-22836280D01*
|
||||
|
|
@ -4210,10 +4372,18 @@ X246044126Y-21215000D01*
|
|||
X245663720Y-21372569D01*
|
||||
X245372569Y-21663720D01*
|
||||
X245215000Y-22044126D01*
|
||||
X154335000Y-22044126D01*
|
||||
X154335000Y-21794126D01*
|
||||
X154177431Y-21413720D01*
|
||||
X153886280Y-21122569D01*
|
||||
X171319585Y-22044126D01*
|
||||
X171517431Y-21846280D01*
|
||||
X171675000Y-21465874D01*
|
||||
X171675000Y-21054126D01*
|
||||
X171517431Y-20673720D01*
|
||||
X171226280Y-20382569D01*
|
||||
X170845874Y-20225000D01*
|
||||
X170434126Y-20225000D01*
|
||||
X170053720Y-20382569D01*
|
||||
X169762569Y-20673720D01*
|
||||
X169605000Y-21054126D01*
|
||||
X153721044Y-21054126D01*
|
||||
X153505874Y-20965000D01*
|
||||
X153094126Y-20965000D01*
|
||||
X152713720Y-21122569D01*
|
||||
|
|
@ -4472,6 +4642,22 @@ X256215874Y-88955000D01*
|
|||
X256596280Y-88797431D01*
|
||||
X256873000Y-88520711D01*
|
||||
X256873000Y-93473000D01*
|
||||
X196507271Y-93473000D01*
|
||||
X196786280Y-93357431D01*
|
||||
X197077431Y-93066280D01*
|
||||
X197235000Y-92685874D01*
|
||||
X197235000Y-92274126D01*
|
||||
X197077431Y-91893720D01*
|
||||
X196786280Y-91602569D01*
|
||||
X196405874Y-91445000D01*
|
||||
X195994126Y-91445000D01*
|
||||
X195613720Y-91602569D01*
|
||||
X195322569Y-91893720D01*
|
||||
X195165000Y-92274126D01*
|
||||
X195165000Y-92685874D01*
|
||||
X195322569Y-93066280D01*
|
||||
X195613720Y-93357431D01*
|
||||
X195892729Y-93473000D01*
|
||||
X189311200Y-93473000D01*
|
||||
X189311200Y-90419999D01*
|
||||
X216722560Y-90419999D01*
|
||||
|
|
@ -4525,11 +4711,30 @@ X189325132Y-89749999D01*
|
|||
X189311200Y-89679957D01*
|
||||
X189311200Y-89679954D01*
|
||||
X189269936Y-89472504D01*
|
||||
X189264067Y-89463720D01*
|
||||
X189158597Y-89305874D01*
|
||||
X189152424Y-89296635D01*
|
||||
X189152422Y-89296633D01*
|
||||
X189112746Y-89237254D01*
|
||||
X189053367Y-89197578D01*
|
||||
X188749915Y-88894126D01*
|
||||
X195165000Y-88894126D01*
|
||||
X195165000Y-89305874D01*
|
||||
X195322569Y-89686280D01*
|
||||
X195613720Y-89977431D01*
|
||||
X195994126Y-90135000D01*
|
||||
X196405874Y-90135000D01*
|
||||
X196786280Y-89977431D01*
|
||||
X197077431Y-89686280D01*
|
||||
X197235000Y-89305874D01*
|
||||
X197235000Y-88894126D01*
|
||||
X197077431Y-88513720D01*
|
||||
X196786280Y-88222569D01*
|
||||
X196405874Y-88065000D01*
|
||||
X195994126Y-88065000D01*
|
||||
X195613720Y-88222569D01*
|
||||
X195322569Y-88513720D01*
|
||||
X195165000Y-88894126D01*
|
||||
X188749915Y-88894126D01*
|
||||
X187309915Y-87454126D01*
|
||||
X252815000Y-87454126D01*
|
||||
X252815000Y-87865874D01*
|
||||
|
|
@ -4576,7 +4781,38 @@ X183644126Y-86035000D01*
|
|||
X183879212Y-86035000D01*
|
||||
X187888801Y-90044590D01*
|
||||
X187888801Y-93473000D01*
|
||||
X124724353Y-93473000D01*
|
||||
X124835000Y-93205874D01*
|
||||
X124835000Y-92794126D01*
|
||||
X124677431Y-92413720D01*
|
||||
X124386280Y-92122569D01*
|
||||
X124005874Y-91965000D01*
|
||||
X123594126Y-91965000D01*
|
||||
X123213720Y-92122569D01*
|
||||
X122922569Y-92413720D01*
|
||||
X122765000Y-92794126D01*
|
||||
X122765000Y-93205874D01*
|
||||
X122875647Y-93473000D01*
|
||||
X113726847Y-93473000D01*
|
||||
X113724827Y-91794126D01*
|
||||
X157065000Y-91794126D01*
|
||||
X157065000Y-92205874D01*
|
||||
X157222569Y-92586280D01*
|
||||
X157513720Y-92877431D01*
|
||||
X157894126Y-93035000D01*
|
||||
X158305874Y-93035000D01*
|
||||
X158686280Y-92877431D01*
|
||||
X158977431Y-92586280D01*
|
||||
X159135000Y-92205874D01*
|
||||
X159135000Y-91794126D01*
|
||||
X158977431Y-91413720D01*
|
||||
X158686280Y-91122569D01*
|
||||
X158305874Y-90965000D01*
|
||||
X157894126Y-90965000D01*
|
||||
X157513720Y-91122569D01*
|
||||
X157222569Y-91413720D01*
|
||||
X157065000Y-91794126D01*
|
||||
X113724827Y-91794126D01*
|
||||
X113719388Y-87274126D01*
|
||||
X114165000Y-87274126D01*
|
||||
X114165000Y-87685874D01*
|
||||
|
|
@ -4825,6 +5061,16 @@ X186027431Y-83486280D01*
|
|||
X186185000Y-83105874D01*
|
||||
X186185000Y-82694126D01*
|
||||
X186114584Y-82524126D01*
|
||||
X235415000Y-82524126D01*
|
||||
X235415000Y-82935874D01*
|
||||
X235572569Y-83316280D01*
|
||||
X235863720Y-83607431D01*
|
||||
X236244126Y-83765000D01*
|
||||
X236655874Y-83765000D01*
|
||||
X237036280Y-83607431D01*
|
||||
X237327431Y-83316280D01*
|
||||
X237485000Y-82935874D01*
|
||||
X237485000Y-82524126D01*
|
||||
X251865000Y-82524126D01*
|
||||
X251865000Y-82935874D01*
|
||||
X252022569Y-83316280D01*
|
||||
|
|
@ -4842,6 +5088,14 @@ X252694126Y-81695000D01*
|
|||
X252313720Y-81852569D01*
|
||||
X252022569Y-82143720D01*
|
||||
X251865000Y-82524126D01*
|
||||
X237485000Y-82524126D01*
|
||||
X237327431Y-82143720D01*
|
||||
X237036280Y-81852569D01*
|
||||
X236655874Y-81695000D01*
|
||||
X236244126Y-81695000D01*
|
||||
X235863720Y-81852569D01*
|
||||
X235572569Y-82143720D01*
|
||||
X235415000Y-82524126D01*
|
||||
X186114584Y-82524126D01*
|
||||
X186027431Y-82313720D01*
|
||||
X185736280Y-82022569D01*
|
||||
|
|
@ -5507,6 +5761,25 @@ X117833993Y-65288864D01*
|
|||
X117544457Y-64855543D01*
|
||||
X117461331Y-64800000D01*
|
||||
X117544457Y-64744457D01*
|
||||
X117778540Y-64394126D01*
|
||||
X229565000Y-64394126D01*
|
||||
X229565000Y-64805874D01*
|
||||
X229722569Y-65186280D01*
|
||||
X230013720Y-65477431D01*
|
||||
X230394126Y-65635000D01*
|
||||
X230805874Y-65635000D01*
|
||||
X231186280Y-65477431D01*
|
||||
X231477431Y-65186280D01*
|
||||
X231635000Y-64805874D01*
|
||||
X231635000Y-64394126D01*
|
||||
X231477431Y-64013720D01*
|
||||
X231186280Y-63722569D01*
|
||||
X230805874Y-63565000D01*
|
||||
X230394126Y-63565000D01*
|
||||
X230013720Y-63722569D01*
|
||||
X229722569Y-64013720D01*
|
||||
X229565000Y-64394126D01*
|
||||
X117778540Y-64394126D01*
|
||||
X117833993Y-64311136D01*
|
||||
X117935664Y-63800000D01*
|
||||
X117833993Y-63288864D01*
|
||||
|
|
@ -6189,6 +6462,25 @@ X125163720Y-51466589D01*
|
|||
X124872569Y-51757740D01*
|
||||
X124715000Y-52138146D01*
|
||||
X113677107Y-52138146D01*
|
||||
X113673022Y-48744126D01*
|
||||
X114815000Y-48744126D01*
|
||||
X114815000Y-49155874D01*
|
||||
X114972569Y-49536280D01*
|
||||
X115263720Y-49827431D01*
|
||||
X115644126Y-49985000D01*
|
||||
X116055874Y-49985000D01*
|
||||
X116436280Y-49827431D01*
|
||||
X116727431Y-49536280D01*
|
||||
X116885000Y-49155874D01*
|
||||
X116885000Y-48744126D01*
|
||||
X116727431Y-48363720D01*
|
||||
X116436280Y-48072569D01*
|
||||
X116055874Y-47915000D01*
|
||||
X115644126Y-47915000D01*
|
||||
X115263720Y-48072569D01*
|
||||
X114972569Y-48363720D01*
|
||||
X114815000Y-48744126D01*
|
||||
X113673022Y-48744126D01*
|
||||
X113670648Y-46771168D01*
|
||||
X124565000Y-46771168D01*
|
||||
X124565000Y-47182916D01*
|
||||
|
|
@ -6208,6 +6500,25 @@ X125013720Y-46099611D01*
|
|||
X124722569Y-46390762D01*
|
||||
X124565000Y-46771168D01*
|
||||
X113670648Y-46771168D01*
|
||||
X113669172Y-45544126D01*
|
||||
X253267500Y-45544126D01*
|
||||
X253267500Y-45955874D01*
|
||||
X253425069Y-46336280D01*
|
||||
X253716220Y-46627431D01*
|
||||
X254096626Y-46785000D01*
|
||||
X254508374Y-46785000D01*
|
||||
X254888780Y-46627431D01*
|
||||
X255179931Y-46336280D01*
|
||||
X255337500Y-45955874D01*
|
||||
X255337500Y-45544126D01*
|
||||
X255179931Y-45163720D01*
|
||||
X254888780Y-44872569D01*
|
||||
X254508374Y-44715000D01*
|
||||
X254096626Y-44715000D01*
|
||||
X253716220Y-44872569D01*
|
||||
X253425069Y-45163720D01*
|
||||
X253267500Y-45544126D01*
|
||||
X113669172Y-45544126D01*
|
||||
X113667079Y-43804500D01*
|
||||
X124565000Y-43804500D01*
|
||||
X124565000Y-44216248D01*
|
||||
|
|
@ -7144,7 +7455,18 @@ X153505874Y-23035000D01*
|
|||
X153886280Y-22877431D01*
|
||||
X154177431Y-22586280D01*
|
||||
X154335000Y-22205874D01*
|
||||
X154335000Y-22044126D01*
|
||||
X154335000Y-21794126D01*
|
||||
X154177431Y-21413720D01*
|
||||
X153886280Y-21122569D01*
|
||||
X153721044Y-21054126D01*
|
||||
X169605000Y-21054126D01*
|
||||
X169605000Y-21465874D01*
|
||||
X169762569Y-21846280D01*
|
||||
X170053720Y-22137431D01*
|
||||
X170434126Y-22295000D01*
|
||||
X170845874Y-22295000D01*
|
||||
X171226280Y-22137431D01*
|
||||
X171319585Y-22044126D01*
|
||||
X245215000Y-22044126D01*
|
||||
X245215000Y-22455874D01*
|
||||
X245372569Y-22836280D01*
|
||||
|
|
@ -7181,10 +7503,18 @@ X246044126Y-21215000D01*
|
|||
X245663720Y-21372569D01*
|
||||
X245372569Y-21663720D01*
|
||||
X245215000Y-22044126D01*
|
||||
X154335000Y-22044126D01*
|
||||
X154335000Y-21794126D01*
|
||||
X154177431Y-21413720D01*
|
||||
X153886280Y-21122569D01*
|
||||
X171319585Y-22044126D01*
|
||||
X171517431Y-21846280D01*
|
||||
X171675000Y-21465874D01*
|
||||
X171675000Y-21054126D01*
|
||||
X171517431Y-20673720D01*
|
||||
X171226280Y-20382569D01*
|
||||
X170845874Y-20225000D01*
|
||||
X170434126Y-20225000D01*
|
||||
X170053720Y-20382569D01*
|
||||
X169762569Y-20673720D01*
|
||||
X169605000Y-21054126D01*
|
||||
X153721044Y-21054126D01*
|
||||
X153505874Y-20965000D01*
|
||||
X153094126Y-20965000D01*
|
||||
X152713720Y-21122569D01*
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
%!PS-Adobe-3.0
|
||||
%%Creator: PCBNEW
|
||||
%%CreationDate: Sat Jan 29 10:57:32 2022
|
||||
%%CreationDate: Sat Feb 5 15:09:37 2022
|
||||
%%Title: /home/dolbeau/MAC/NuBusFPGA/nubus-to-ztex/nubus-to-ztex-NPTH-drl_map.ps
|
||||
%%Pages: 1
|
||||
%%PageOrder: Ascend
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
M48
|
||||
;DRILL file {KiCad 5.0.2+dfsg1-1~bpo9+1} date Sat Jan 29 10:57:31 2022
|
||||
;DRILL file {KiCad 5.0.2+dfsg1-1~bpo9+1} date Sat Feb 5 15:09:36 2022
|
||||
;FORMAT={-:-/ absolute / inch / decimal}
|
||||
FMAT,2
|
||||
INCH,TZ
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
%!PS-Adobe-3.0
|
||||
%%Creator: PCBNEW
|
||||
%%CreationDate: Sat Jan 29 10:57:32 2022
|
||||
%%CreationDate: Sat Feb 5 15:09:37 2022
|
||||
%%Title: /home/dolbeau/MAC/NuBusFPGA/nubus-to-ztex/nubus-to-ztex-PTH-drl_map.ps
|
||||
%%Pages: 1
|
||||
%%PageOrder: Ascend
|
||||
|
|
@ -185,6 +185,14 @@ newpath
|
|||
26405.9 46368.2 lineto
|
||||
stroke
|
||||
newpath
|
||||
26421.6 60518.5 moveto
|
||||
26588.3 60351.8 lineto
|
||||
stroke
|
||||
newpath
|
||||
26588.3 60518.5 moveto
|
||||
26421.6 60351.8 lineto
|
||||
stroke
|
||||
newpath
|
||||
26609.1 76247.4 moveto
|
||||
26775.8 76080.7 lineto
|
||||
stroke
|
||||
|
|
@ -265,6 +273,14 @@ newpath
|
|||
28651.4 45417.9 lineto
|
||||
stroke
|
||||
newpath
|
||||
29735.1 42158.5 moveto
|
||||
29901.8 41991.8 lineto
|
||||
stroke
|
||||
newpath
|
||||
29901.8 42158.5 moveto
|
||||
29735.1 41991.8 lineto
|
||||
stroke
|
||||
newpath
|
||||
30485.4 65050.3 moveto
|
||||
30652.1 64883.6 lineto
|
||||
stroke
|
||||
|
|
@ -729,6 +745,14 @@ newpath
|
|||
42888.2 47514.4 lineto
|
||||
stroke
|
||||
newpath
|
||||
44031.3 42575.3 moveto
|
||||
44198 42408.6 lineto
|
||||
stroke
|
||||
newpath
|
||||
44198 42575.3 moveto
|
||||
44031.3 42408.6 lineto
|
||||
stroke
|
||||
newpath
|
||||
44943 72480.6 moveto
|
||||
45109.8 72313.9 lineto
|
||||
stroke
|
||||
|
|
@ -769,6 +793,14 @@ newpath
|
|||
48306.6 47514.4 lineto
|
||||
stroke
|
||||
newpath
|
||||
49257.9 72059.6 moveto
|
||||
49424.7 71892.9 lineto
|
||||
stroke
|
||||
newpath
|
||||
49424.7 72059.6 moveto
|
||||
49257.9 71892.9 lineto
|
||||
stroke
|
||||
newpath
|
||||
50366.6 50202.7 moveto
|
||||
50533.3 50036 lineto
|
||||
stroke
|
||||
|
|
@ -921,6 +953,22 @@ newpath
|
|||
59351.7 47514.4 lineto
|
||||
stroke
|
||||
newpath
|
||||
59911.3 43784.1 moveto
|
||||
60078 43617.3 lineto
|
||||
stroke
|
||||
newpath
|
||||
60078 43784.1 moveto
|
||||
59911.3 43617.3 lineto
|
||||
stroke
|
||||
newpath
|
||||
59911.3 42375.3 moveto
|
||||
60078 42208.6 lineto
|
||||
stroke
|
||||
newpath
|
||||
60078 42375.3 moveto
|
||||
59911.3 42208.6 lineto
|
||||
stroke
|
||||
newpath
|
||||
70181.2 40087.1 moveto
|
||||
70347.9 39920.3 lineto
|
||||
stroke
|
||||
|
|
@ -945,6 +993,14 @@ newpath
|
|||
71556.6 40741.4 lineto
|
||||
stroke
|
||||
newpath
|
||||
74249.1 53995.6 moveto
|
||||
74415.9 53828.9 lineto
|
||||
stroke
|
||||
newpath
|
||||
74415.9 53995.6 moveto
|
||||
74249.1 53828.9 lineto
|
||||
stroke
|
||||
newpath
|
||||
75499.5 65666 moveto
|
||||
75666.3 65499.2 lineto
|
||||
stroke
|
||||
|
|
@ -953,6 +1009,14 @@ newpath
|
|||
75499.5 65499.2 lineto
|
||||
stroke
|
||||
newpath
|
||||
76687.4 46439.1 moveto
|
||||
76854.1 46272.3 lineto
|
||||
stroke
|
||||
newpath
|
||||
76854.1 46439.1 moveto
|
||||
76687.4 46272.3 lineto
|
||||
stroke
|
||||
newpath
|
||||
78671.4 65924.4 moveto
|
||||
78838.1 65757.6 lineto
|
||||
stroke
|
||||
|
|
@ -977,6 +1041,14 @@ newpath
|
|||
79738.4 66091.1 lineto
|
||||
stroke
|
||||
newpath
|
||||
79909.3 39345.2 moveto
|
||||
80076 39178.4 lineto
|
||||
stroke
|
||||
newpath
|
||||
80076 39345.2 moveto
|
||||
79909.3 39178.4 lineto
|
||||
stroke
|
||||
newpath
|
||||
80480.3 56756.9 moveto
|
||||
80647 56590.2 lineto
|
||||
stroke
|
||||
|
|
@ -1113,6 +1185,14 @@ newpath
|
|||
83939.7 44217.5 lineto
|
||||
stroke
|
||||
newpath
|
||||
84128.3 61852.3 moveto
|
||||
84295 61685.5 lineto
|
||||
stroke
|
||||
newpath
|
||||
84295 61852.3 moveto
|
||||
84128.3 61685.5 lineto
|
||||
stroke
|
||||
newpath
|
||||
84435.7 58491.8 moveto
|
||||
84602.4 58325.1 lineto
|
||||
stroke
|
||||
|
|
@ -5082,20 +5162,13 @@ newpath
|
|||
43600.7 33538.8 lineto
|
||||
stroke
|
||||
newpath
|
||||
44669.3 33876.3 moveto
|
||||
45400.4 33876.3 lineto
|
||||
45006.7 33426.3 lineto
|
||||
45175.5 33426.3 lineto
|
||||
45288 33370.1 lineto
|
||||
45344.2 33313.8 lineto
|
||||
45400.4 33201.4 lineto
|
||||
45400.4 32920.1 lineto
|
||||
45344.2 32807.7 lineto
|
||||
45288 32751.4 lineto
|
||||
45175.5 32695.2 lineto
|
||||
44838 32695.2 lineto
|
||||
44725.5 32751.4 lineto
|
||||
44669.3 32807.7 lineto
|
||||
45288 33482.6 moveto
|
||||
45288 32695.2 lineto
|
||||
stroke
|
||||
newpath
|
||||
45006.7 33932.5 moveto
|
||||
44725.5 33088.9 lineto
|
||||
45456.7 33088.9 lineto
|
||||
stroke
|
||||
newpath
|
||||
45962.9 32695.2 moveto
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
M48
|
||||
;DRILL file {KiCad 5.0.2+dfsg1-1~bpo9+1} date Sat Jan 29 10:57:31 2022
|
||||
;DRILL file {KiCad 5.0.2+dfsg1-1~bpo9+1} date Sat Feb 5 15:09:36 2022
|
||||
;FORMAT={-:-/ absolute / inch / decimal}
|
||||
FMAT,2
|
||||
INCH,TZ
|
||||
|
|
@ -23,6 +23,7 @@ X4.5354Y-3.4441
|
|||
X4.5354Y-3.5209
|
||||
X4.5354Y-3.572
|
||||
X4.5595Y-3.248
|
||||
X4.561Y-1.9272
|
||||
X4.5787Y-0.4414
|
||||
X4.5787Y-0.6471
|
||||
X4.6142Y-3.3378
|
||||
|
|
@ -33,6 +34,7 @@ X4.6575Y-3.1417
|
|||
X4.6719Y-1.5551
|
||||
X4.6719Y-1.7913
|
||||
X4.7717Y-3.3378
|
||||
X4.874Y-3.6614
|
||||
X4.9449Y-1.4991
|
||||
X4.9449Y-1.6159
|
||||
X4.9449Y-1.7327
|
||||
|
|
@ -91,11 +93,13 @@ X6.0354Y-0.7382
|
|||
X6.0354Y-0.8661
|
||||
X6.0851Y-0.5197
|
||||
X6.1164Y-3.1398
|
||||
X6.2244Y-3.622
|
||||
X6.3105Y-0.7972
|
||||
X6.3386Y-0.5787
|
||||
X6.3681Y-2.9011
|
||||
X6.4173Y-2.7953
|
||||
X6.6282Y-3.1398
|
||||
X6.7181Y-0.837
|
||||
X6.8228Y-2.9016
|
||||
X6.8701Y-2.7953
|
||||
X7.0787Y-3.315
|
||||
|
|
@ -115,13 +119,18 @@ X7.3583Y-2.9055
|
|||
X7.4114Y-2.9011
|
||||
X7.4606Y-2.7953
|
||||
X7.6716Y-3.1398
|
||||
X7.7244Y-3.5079
|
||||
X7.7244Y-3.6409
|
||||
X8.6945Y-3.8571
|
||||
X8.7613Y-2.3228
|
||||
X8.8244Y-3.7795
|
||||
X9.0787Y-2.5433
|
||||
X9.1969Y-1.4409
|
||||
X9.3091Y-3.2571
|
||||
X9.4965Y-1.4165
|
||||
X9.5618Y-1.1878
|
||||
X9.5972Y-1.385
|
||||
X9.6134Y-3.9272
|
||||
X9.6673Y-2.2825
|
||||
X9.6875Y-2.3268
|
||||
X9.6941Y-2.4359
|
||||
|
|
@ -139,6 +148,7 @@ X9.9213Y-1.4528
|
|||
X9.9362Y-2.436
|
||||
X9.9567Y-3.2571
|
||||
X9.9941Y-3.4512
|
||||
X10.0119Y-1.8012
|
||||
X10.0409Y-2.1186
|
||||
X10.0492Y-1.0728
|
||||
X10.0591Y-2.3081
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
### Module positions - created on Sat Jan 29 10:58:25 2022 ###
|
||||
### Module positions - created on Sat Feb 5 15:09:58 2022 ###
|
||||
### Printed by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
|
||||
## Unit = mm, Angle = deg.
|
||||
## Side : bottom
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
Drill report for /home/dolbeau/MAC/NuBusFPGA/nubus-to-ztex/nubus-to-ztex.kicad_pcb
|
||||
Created on Sat Jan 29 10:57:34 2022
|
||||
Created on Sat Feb 5 15:09:39 2022
|
||||
|
||||
Copper Layer Stackup:
|
||||
=============================================================
|
||||
|
|
@ -12,7 +12,7 @@ Copper Layer Stackup:
|
|||
Drill file 'nubus-to-ztex-PTH.drl' contains
|
||||
plated through holes:
|
||||
=============================================================
|
||||
T1 0.40mm 0.016" (139 holes)
|
||||
T1 0.40mm 0.016" (149 holes)
|
||||
T2 0.60mm 0.024" (2 holes) (with 2 slots)
|
||||
T3 0.80mm 0.031" (2 holes)
|
||||
T4 0.85mm 0.033" (2 holes)
|
||||
|
|
@ -25,7 +25,7 @@ Drill file 'nubus-to-ztex-PTH.drl' contains
|
|||
T11 1.30mm 0.051" (4 holes)
|
||||
T12 3.05mm 0.120" (2 holes)
|
||||
|
||||
Total plated holes count 429
|
||||
Total plated holes count 439
|
||||
|
||||
|
||||
Drill file 'nubus-to-ztex-NPTH.drl' contains
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
### Module positions - created on Sat Jan 29 10:58:25 2022 ###
|
||||
### Module positions - created on Sat Feb 5 15:09:58 2022 ###
|
||||
### Printed by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
|
||||
## Unit = mm, Angle = deg.
|
||||
## Side : top
|
||||
|
|
|
|||
|
|
@ -8,15 +8,15 @@ R28,0603WAF5360T5E,1,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount
|
|||
"R1,R2,R3,R9,R10,R11,R12,R13,R14,R15,R16,R17,R18,R19,R20,R21",0603WAF5490T5E,16,https://lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-0603WAF5490T5E_C23079.html
|
||||
"R30,R31,R32",0603WAF750JT5E,3,https://www.lcsc.com/product-detail/Chip-Resistor-Surface-Mount_Uniroyal-Elec-0603WAF750JT5E_C4275.html
|
||||
"JAB1,JCD1",10-89-7642,2,https://www2.mouser.com/ProductDetail/Molex/10-89-7642?qs=%2Fha2pyFadugCxzQFZUdvioDcljDVidgd4vXrOFuSRYM%3D
|
||||
J5,10029449-111,1,https://www2.mouser.com/ProductDetail/Amphenol-FCI/10029449-111RLF?qs=fmpTyLOWOey0HPdD9%2F%2FaXA%3D%3D
|
||||
J5,10029449-111,1,https://lcsc.com/product-detail/D-Sub-DVI-HDMI-Connectors_Amphenol-ICC-10029449-111RLF_C427307.html
|
||||
J6,105017-0001,1,https://lcsc.com/product-detail/USB-Connectors_MOLEX-1050170001_C136000.html
|
||||
R33,1210W2F1004T5E,1,https://www.lcsc.com/product-detail/Chip-Resistor-Surface-Mount_UNI-ROYAL-Uniroyal-Elec-1210W2F1004T5E_C620664.html
|
||||
J7,640456-3,1,https://www.lcsc.com/product-detail/Wire-To-Board-Wire-To-Wire-Connector_TE-Connectivity-640456-3_C86503.html
|
||||
"U1,U2,U3","74LVT125PW,118",3,https://eu.mouser.com/ProductDetail/Nexperia/74LVT125PW118?qs=me8TqzrmIYWdhdg6%252BsGGHw%3D%3D
|
||||
"U5,U6,U7,U8","74LVT245BPW,118",4,https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D
|
||||
"U5,U6,U7,U8","74LVT245BPW,118",4,https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957
|
||||
J4,85003-0567,1,https://www.mouser.fr/ProductDetail/Molex/85003-0567?qs=U4pz39agNJB6P1oBpJ4bJA%3D%3D
|
||||
"J1,J2",87831-1420,2,https://www2.mouser.com/ProductDetail/Molex/87831-1420?qs=QtQX4uD3c2VDCL534TqpVg%3D%3D
|
||||
U13,AD1580ARTZ,1,https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580ARTZ-REEL7?qs=NmRFExCfTkENN3U3%252BacLbA%3D%3D
|
||||
U13,AD1580BRTZ,1,https://www.digikey.fr/fr/products/detail/analog-devices-inc/AD1580BRTZ-REEL7/936475
|
||||
U12,ADV7125JSTZ240,1,https://lcsc.com/product-detail/Digital-To-Analog-Converters-DACs_Analog-Devices-ADV7125JSTZ240_C514373.html
|
||||
"C3,C21,C28,C29",C2012X5R1A476MTJ00E,4,https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_TDK-C2012X5R1A476MTJ00E_C76636.html
|
||||
"C7,C8,C11,C15,C20,C34,C35,C36",CC0603KRX7R8BB103,8,https://lcsc.com/product-detail/Multilayer-Ceramic-Capacitors-MLCC-SMD-SMT_YAGEO-CC0603KRX7R8BB103_C327204.html
|
||||
|
|
|
|||
|
|
|
@ -56,6 +56,16 @@ P DIM N
|
|||
317GND VIA MD0157PA00X+045787Y-006471X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+096875Y-023268X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+105118Y-024035X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+096134Y-039272X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+093091Y-032571X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+100119Y-018012X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+090787Y-025433X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+067181Y-008370X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+045610Y-019272X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+062244Y-036220X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+077244Y-036409X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+077244Y-035079X0315Y0000R000S3
|
||||
317GND VIA MD0157PA00X+048740Y-036614X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+100787Y-008760X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+055162Y-025591X0315Y0000R000S3
|
||||
317+3V3 VIA MD0157PA00X+056496Y-030689X0315Y0000R000S3
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,4 @@
|
|||
## Footprint report - date Sat Jan 29 10:58:30 2022
|
||||
## Footprint report - date Sat Feb 5 15:10:10 2022
|
||||
## Created by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
|
||||
## Unit = mm, Angle = deg.
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
<export version="D">
|
||||
<design>
|
||||
<source>/home/dolbeau/MAC/NuBusFPGA/nubus-to-ztex/nubus-to-ztex.sch</source>
|
||||
<date>Sat Jan 29 10:58:45 2022</date>
|
||||
<date>Sat Feb 5 15:10:52 2022</date>
|
||||
<tool>Eeschema 5.0.2+dfsg1-1~bpo9+1</tool>
|
||||
<sheet number="1" name="/" tstamps="/">
|
||||
<title_block>
|
||||
|
|
@ -376,7 +376,8 @@
|
|||
<datasheet>http://www.ti.com/lit/gpn/sn74LS245</datasheet>
|
||||
<fields>
|
||||
<field name="MPN">74LVT245BPW,118</field>
|
||||
<field name="URL">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
<field name="URL">https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957</field>
|
||||
<field name="URL-mouser">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
</fields>
|
||||
<libsource lib="74xx" part="74LS245" description="Octal BUS Transceivers, 3-State outputs"/>
|
||||
<sheetpath names="/nubus/" tstamps="/618F532C/"/>
|
||||
|
|
@ -404,7 +405,8 @@
|
|||
<datasheet>http://www.ti.com/lit/gpn/sn74LS245</datasheet>
|
||||
<fields>
|
||||
<field name="MPN">74LVT245BPW,118</field>
|
||||
<field name="URL">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
<field name="URL">https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957</field>
|
||||
<field name="URL-mouser">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
</fields>
|
||||
<libsource lib="74xx" part="74LS245" description="Octal BUS Transceivers, 3-State outputs"/>
|
||||
<sheetpath names="/nubus/" tstamps="/618F532C/"/>
|
||||
|
|
@ -432,7 +434,8 @@
|
|||
<datasheet>http://www.ti.com/lit/gpn/sn74LS245</datasheet>
|
||||
<fields>
|
||||
<field name="MPN">74LVT245BPW,118</field>
|
||||
<field name="URL">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
<field name="URL">https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957</field>
|
||||
<field name="URL-mouser">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
</fields>
|
||||
<libsource lib="74xx" part="74LS245" description="Octal BUS Transceivers, 3-State outputs"/>
|
||||
<sheetpath names="/nubus/" tstamps="/618F532C/"/>
|
||||
|
|
@ -463,7 +466,8 @@
|
|||
<field name="Drawings">https://www.renesas.com/us/en/package/pcg20</field>
|
||||
<field name="MPN">74LVT245BPW,118</field>
|
||||
<field name="Package Drawings">https://assets.nexperia.com/documents/package-information/SOT360-1.pdf</field>
|
||||
<field name="URL">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
<field name="URL">https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957</field>
|
||||
<field name="URL-mouser">https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D</field>
|
||||
</fields>
|
||||
<libsource lib="74xx" part="74LS245" description="Octal BUS Transceivers, 3-State outputs"/>
|
||||
<sheetpath names="/nubus/" tstamps="/618F532C/"/>
|
||||
|
|
@ -1192,7 +1196,8 @@
|
|||
<datasheet>https://en.wikipedia.org/wiki/HDMI</datasheet>
|
||||
<fields>
|
||||
<field name="MPN">10029449-111</field>
|
||||
<field name="URL">https://www2.mouser.com/ProductDetail/Amphenol-FCI/10029449-111RLF?qs=fmpTyLOWOey0HPdD9%2F%2FaXA%3D%3D</field>
|
||||
<field name="URL">https://lcsc.com/product-detail/D-Sub-DVI-HDMI-Connectors_Amphenol-ICC-10029449-111RLF_C427307.html</field>
|
||||
<field name="URL-ALT">https://www2.mouser.com/ProductDetail/Amphenol-FCI/10029449-111RLF?qs=fmpTyLOWOey0HPdD9%2F%2FaXA%3D%3D</field>
|
||||
</fields>
|
||||
<libsource lib="Connector" part="HDMI_A" description="HDMI type A connector"/>
|
||||
<sheetpath names="/hdmi/" tstamps="/61B62C00/"/>
|
||||
|
|
@ -1709,10 +1714,11 @@
|
|||
<value>AD1580</value>
|
||||
<footprint>Package_TO_SOT_SMD:SOT-23</footprint>
|
||||
<fields>
|
||||
<field name="MPN">AD1580ARTZ</field>
|
||||
<field name="MPN-ALT">AD1580BRTZ</field>
|
||||
<field name="URL">https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580ARTZ-REEL7?qs=NmRFExCfTkENN3U3%252BacLbA%3D%3D</field>
|
||||
<field name="MPN">AD1580BRTZ</field>
|
||||
<field name="MPN-ALT">AD1580ARTZ</field>
|
||||
<field name="URL">https://www.digikey.fr/fr/products/detail/analog-devices-inc/AD1580BRTZ-REEL7/936475</field>
|
||||
<field name="URL-ALT">https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580BRTZ-REEL7?qs=NmRFExCfTkFZVi9%2F1ZfkXg%3D%3D</field>
|
||||
<field name="URL-mouser">https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580ARTZ-REEL7?qs=NmRFExCfTkENN3U3%252BacLbA%3D%3D</field>
|
||||
</fields>
|
||||
<libsource lib="ad1580" part="AD1580" description=""/>
|
||||
<sheetpath names="/vga/" tstamps="/6193AB43/"/>
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -971,8 +971,9 @@ F 0 "U8" H 17350 4428 50 0000 C CNN
|
|||
F 1 "74LVT245BPW,118" H 17350 4337 50 0000 C CNN
|
||||
F 2 "For_SeeedStudio:TSSOP-20_4.4x6.5mm_P0.65mm_ForSeeedStudio" H 17350 3450 50 0001 C CNN
|
||||
F 3 "http://www.ti.com/lit/gpn/sn74LS245" H 17350 3450 50 0001 C CNN
|
||||
F 4 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 17350 3450 50 0001 C CNN "URL"
|
||||
F 4 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 17350 3450 50 0001 C CNN "URL-mouser"
|
||||
F 5 "74LVT245BPW,118" H 17350 3450 50 0001 C CNN "MPN"
|
||||
F 6 "https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957" H 17350 3450 50 0001 C CNN "URL"
|
||||
1 17350 3450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
|
|
@ -1043,7 +1044,8 @@ F 1 "74LVT245BPW,118" H 15350 4337 50 0000 C CNN
|
|||
F 2 "For_SeeedStudio:TSSOP-20_4.4x6.5mm_P0.65mm_ForSeeedStudio" H 15350 3450 50 0001 C CNN
|
||||
F 3 "http://www.ti.com/lit/gpn/sn74LS245" H 15350 3450 50 0001 C CNN
|
||||
F 4 "74LVT245BPW,118" H 15350 3450 50 0001 C CNN "MPN"
|
||||
F 5 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 15350 3450 50 0001 C CNN "URL"
|
||||
F 5 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 15350 3450 50 0001 C CNN "URL-mouser"
|
||||
F 6 "https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957" H 15350 3450 50 0001 C CNN "URL"
|
||||
1 15350 3450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
|
|
@ -1114,7 +1116,8 @@ F 1 "74LVT245BPW,118" H 13300 4337 50 0000 C CNN
|
|||
F 2 "For_SeeedStudio:TSSOP-20_4.4x6.5mm_P0.65mm_ForSeeedStudio" H 13300 3450 50 0001 C CNN
|
||||
F 3 "http://www.ti.com/lit/gpn/sn74LS245" H 13300 3450 50 0001 C CNN
|
||||
F 4 "74LVT245BPW,118" H 13300 3450 50 0001 C CNN "MPN"
|
||||
F 5 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 13300 3450 50 0001 C CNN "URL"
|
||||
F 5 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 13300 3450 50 0001 C CNN "URL-mouser"
|
||||
F 6 "https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957" H 13300 3450 50 0001 C CNN "URL"
|
||||
1 13300 3450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
|
|
@ -1185,10 +1188,11 @@ F 1 "74LVT245BPW,118" H 11250 4337 50 0000 C CNN
|
|||
F 2 "For_SeeedStudio:TSSOP-20_4.4x6.5mm_P0.65mm_ForSeeedStudio" H 11250 3450 50 0001 C CNN
|
||||
F 3 "http://www.ti.com/lit/gpn/sn74LS245" H 11250 3450 50 0001 C CNN
|
||||
F 4 "74LVT245BPW,118" H 11250 3450 50 0001 C CNN "MPN"
|
||||
F 5 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 11250 3450 50 0001 C CNN "URL"
|
||||
F 5 "https://eu.mouser.com/ProductDetail/?qs=me8TqzrmIYVnC5%252BK4SaiTg%3D%3D" H 11250 3450 50 0001 C CNN "URL-mouser"
|
||||
F 6 "https://www.renesas.com/us/en/package/pcg20" H 11250 3450 50 0001 C CNN "Drawings"
|
||||
F 7 "https://www.renesas.com/document/psc/pcpcg-package-outline-150-body-width-qsop-025-pitch?language=en" H 11250 3450 50 0001 C CNN "Datasheet - Packaging"
|
||||
F 8 "https://assets.nexperia.com/documents/package-information/SOT360-1.pdf" H 11250 3450 50 0001 C CNN "Package Drawings"
|
||||
F 9 "https://www.digikey.fr/fr/products/detail/nexperia-usa-inc/74LVT245BPW-118/1231957" H 11250 3450 50 0001 C CNN "URL"
|
||||
1 11250 3450
|
||||
-1 0 0 -1
|
||||
$EndComp
|
||||
|
|
|
|||
|
|
@ -682,10 +682,11 @@ F 0 "U13" H 5950 2725 50 0000 C CNN
|
|||
F 1 "AD1580" H 5950 2634 50 0000 C CNN
|
||||
F 2 "Package_TO_SOT_SMD:SOT-23" H 5950 2500 50 0001 C CNN
|
||||
F 3 "" H 5950 2500 50 0001 C CNN
|
||||
F 4 "AD1580ARTZ" H 5950 2500 50 0001 C CNN "MPN"
|
||||
F 5 "https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580ARTZ-REEL7?qs=NmRFExCfTkENN3U3%252BacLbA%3D%3D" H 5950 2500 50 0001 C CNN "URL"
|
||||
F 6 "AD1580BRTZ" H 5950 2500 50 0001 C CNN "MPN-ALT"
|
||||
F 4 "AD1580BRTZ" H 5950 2500 50 0001 C CNN "MPN"
|
||||
F 5 "https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580ARTZ-REEL7?qs=NmRFExCfTkENN3U3%252BacLbA%3D%3D" H 5950 2500 50 0001 C CNN "URL-mouser"
|
||||
F 6 "AD1580ARTZ" H 5950 2500 50 0001 C CNN "MPN-ALT"
|
||||
F 7 "https://www.mouser.fr/ProductDetail/Analog-Devices/AD1580BRTZ-REEL7?qs=NmRFExCfTkFZVi9%2F1ZfkXg%3D%3D" H 5950 2500 50 0001 C CNN "URL-ALT"
|
||||
F 8 "https://www.digikey.fr/fr/products/detail/analog-devices-inc/AD1580BRTZ-REEL7/936475" H 5950 2500 50 0001 C CNN "URL"
|
||||
1 5950 2500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
|
|
|
|||
Loading…
Reference in New Issue