mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-12-22 10:29:53 +00:00
LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650
This commit is contained in:
Romain Dolbeau
parent
2d2cbdbafe
commit
173c87ea02
1
nubus-to-ztex-gateware/.gitignore
vendored
1
nubus-to-ztex-gateware/.gitignore
vendored
@ -11,3 +11,4 @@ blit.raw
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blit.s
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*.patch
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OLD
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nubusfpga_csr_*.h
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7
nubus-to-ztex-gateware/DeclROM/.gitignore
vendored
Normal file
7
nubus-to-ztex-gateware/DeclROM/.gitignore
vendored
Normal file
@ -0,0 +1,7 @@
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vid_decl_rom.bin
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vid_decl_rom.dir
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vid_decl_rom.l
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vid_decl_rom.o
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vid_decl_rom.raw
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vid_decl_rom.srec
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*.bin
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@ -93,6 +93,7 @@ vid_decl_rom.dir: vid_decl_rom.raw append_romdir
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vid_decl_rom.bin: vid_decl_rom.dir
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${NUBUS_CHECKSUM} --input_file $< --output_file $@ --output_size 32768
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dd if=dump.cpr of=vid_decl_rom.bin bs=1 conv=notrunc
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clean:
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rm -f res.inc ${CSRC_ASM} *.o vid_decl_rom.srec vid_decl_rom.raw vid_decl_rom.dir vid_decl_rom.l
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@ -18,6 +18,8 @@
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#endif
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#define GOBOFB_BASE 0x00900000
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#define GOBOFB_ACCEL 0x00901000
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#define GOBOFB_ACCEL_LE 0x00901800
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//#define GOBOFB_REG_BASE 0x00900000
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//#define GOBOFB_MEM_BASE 0x00000000 /* remapped to 0x8f800000 by HW */
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@ -44,6 +46,34 @@
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#define GOBOFB_MODE_24BIT 0x10
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#define GOBOFB_MODE_15BIT 0x11
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#define u_int32_t volatile unsigned long
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struct goblin_accel_regs {
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u_int32_t reg_status; // 0
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u_int32_t reg_cmd;
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u_int32_t reg_r5_cmd;
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u_int32_t resv0;
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u_int32_t reg_width; // 4
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u_int32_t reg_height;
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u_int32_t reg_fgcolor;
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u_int32_t resv2;
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u_int32_t reg_bitblt_src_x; // 8
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u_int32_t reg_bitblt_src_y;
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u_int32_t reg_bitblt_dst_x;
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u_int32_t reg_bitblt_dst_y;
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u_int32_t reg_src_stride; // 12
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u_int32_t reg_dst_stride;
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u_int32_t reg_src_ptr; // 12
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u_int32_t reg_dst_ptr;
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};
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// status
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#define WORK_IN_PROGRESS_BIT 0
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// cmd
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#define DO_BLIT_BIT 0 // hardwired in goblin_accel.py
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#define DO_FILL_BIT 1 // hardwired in goblin_accel.py
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#define DO_TEST_BIT 3 // hardwired in goblin_accel.py
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struct MyGammaTbl {
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short gVersion; /*gamma version number*/
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short gType; /*gamma data type*/
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@ -276,10 +276,12 @@ OSErr cNuBusFPGACtl(CntrlParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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UInt32 a32_4p0, a32_4p1;
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const uint32_t wb = HRES >> idx;
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unsigned short j, i;
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if (vPInfo->csPage != 0)
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return paramErr;
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SwapMMUMode ( &busMode );
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#if 0
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if ((dStore->curMode != kDepthMode5) && (dStore->curMode != kDepthMode6)) {
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/* grey the screen */
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a32_l0 = a32;
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@ -313,6 +315,25 @@ OSErr cNuBusFPGACtl(CntrlParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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a32_l1 += 2*HRES*4;
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}
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}
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#else
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#define WAIT_FOR_HW_LE(accel_le) \
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while (accel_le->reg_status & (1<<WORK_IN_PROGRESS_BIT))
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const UInt32 fgcolor = 0; // FIXME: per-depth?
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struct goblin_accel_regs* accel_le = (struct goblin_accel_regs*)(dce->dCtlDevBase+GOBOFB_ACCEL_LE);
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WAIT_FOR_HW_LE(accel_le);
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accel_le->reg_width = HRES; // pixels
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accel_le->reg_height = VRES;
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accel_le->reg_bitblt_dst_x = 0; // pixels
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accel_le->reg_bitblt_dst_y = 0;
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accel_le->reg_dst_ptr = 0;
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accel_le->reg_fgcolor = fgcolor;
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accel_le->reg_cmd = (1<<DO_FILL_BIT);
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WAIT_FOR_HW_LE(accel_le);
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#undef WAIT_FOR_HW_LE
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#endif
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SwapMMUMode ( &busMode );
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ret = noErr;
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@ -24,6 +24,7 @@ UInt32 Primary(SEBlock* seblock) {
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/* PRIM_WRITEREG(GOBOFB_DEBUG, busMode);// trace */
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/* grey the screen */
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/* should switch to HW ? */
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a32_l0 = a32;
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a32_l1 = a32 + HRES;
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for (j = 0 ; j < VRES ; j+= 2) {
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@ -12,11 +12,6 @@
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struct RAMDrvContext {
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DrvSts2 drvsts;
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//Ptr origcopyfunc;
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//Ptr origdisk; /* keep unstripped pointers for Dispose*/
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//unsigned char * disk;
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//char initialized;
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//char alreadyalloced;
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};
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#define DRIVE_SIZE_BYTES ((256ul-8ul)*1024ul*1024ul) // FIXME: mem size minus fb size
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@ -6,22 +6,27 @@
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OSErr cNuBusFPGARAMDskOpen(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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{
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DrvSts2 *dsptr; // pointer to the DrvSts2 in our context
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DrvQElPtr dq;
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int drvnum = 1;
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struct RAMDrvContext *ctx;
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OSErr ret = noErr;
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char busMode;
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dce->dCtlDevBase = 0xfc000000;
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busMode = 1;
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SwapMMUMode ( &busMode ); // to32 // this likely won't work on older MacII ???
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dce->dCtlDevBase = 0xfc000000; // FIXME: why do we not get our slot properly ?
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write_reg(dce, GOBOFB_DEBUG, 0xDEAD0000);
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/* write_reg(dce, GOBOFB_DEBUG, dce->dCtlRefNum); */
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if (dce->dCtlStorage == nil) {
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DrvQElPtr dq;
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for(dq = (DrvQElPtr)(GetDrvQHdr())->qHead; dq; dq = (DrvQElPtr)dq->qLink) {
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if (dq->dQDrive >= drvnum)
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drvnum = dq->dQDrive+1;
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}
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ReserveMemSys(sizeof(struct RAMDrvContext));
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dce->dCtlStorage = NewHandleSysClear(sizeof(struct RAMDrvContext));
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if (dce->dCtlStorage == nil) {
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ret = openErr;
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@ -65,7 +70,7 @@ OSErr cNuBusFPGARAMDskOpen(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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write_reg(dce, GOBOFB_DEBUG, compressed[2]);
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write_reg(dce, GOBOFB_DEBUG, compressed[3]);
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*/
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res = rledec(superslot, compressed, 730);
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res = rledec(superslot, compressed, 730); // FIXME: 730 = 2920/4 (compressed size in words)
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/*
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write_reg(dce, GOBOFB_DEBUG, res);
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write_reg(dce, GOBOFB_DEBUG, 0xDEEEEEAD);
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@ -76,6 +81,7 @@ OSErr cNuBusFPGARAMDskOpen(IOParamPtr pb, /* DCtlPtr */ AuxDCEPtr dce)
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MyAddDrive(dsptr->dQRefNum, drvnum, (DrvQElPtr)&dsptr->qLink);
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}
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SwapMMUMode ( &busMode );
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done:
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return ret;
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@ -60,15 +60,20 @@ uint32_t rledec(uint32_t* out, const uint32_t* in, const uint32_t len) {
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#endif
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if (c >= 0) {
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chk += (1 + c);
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if (c < 10000) // !!!!!!!!!!!!!!!!!!!!!!!!!!
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for (k = 0 ; k < c+1 ; k++)
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if (c < 300000) { // !!!!!!!!!!!!!!!!!!!!!!!!!!
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for (k = 0 ; k < (c + 1) ; k++)
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out[j++] = in[i+1];
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else
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} else { // do a small subset at the beginning and end instead of the full range and assume this is padding otherwise
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for (k = 0 ; k < 4 ; k++)
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out[j+k] = in[i+1];
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for (k = c-3 ; k < (c + 1) ; k++)
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out[j+k] = in[i+1];
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j += c+1;
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}
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i += 2;
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} else {
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chk += 1 + -c;
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for (k = 0 ; k < 1 + -c ; k++)
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chk += (1 + -c);
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for (k = 0 ; k < (1 + -c) ; k++)
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out[j++] = in[i+1+k];
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i += 2 + -c;
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}
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@ -19,12 +19,12 @@ object GenGoblinAccel { // extends App {
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val config = VexRiscvConfig(
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plugins = List(
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new IBusCachedPlugin(
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resetVector = 0x70910000, // beginning of ROM
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resetVector = 0xF0910000l, // beginning of ROM
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relaxedPcCalculation = false,
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prediction = STATIC,
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config = InstructionCacheConfig(
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cacheSize = 512,
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bytePerLine = 32,
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cacheSize = 256,
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bytePerLine = 16,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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@ -42,8 +42,8 @@ object GenGoblinAccel { // extends App {
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 512,
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bytePerLine = 32,
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cacheSize = 256,
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bytePerLine = 16,
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wayCount = 2,
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addressWidth = 32,
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cpuDataWidth = 128,
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@ -51,7 +51,7 @@ object GenGoblinAccel { // extends App {
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catchAccessError = false,
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catchIllegal = false,
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catchUnaligned = false,
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pendingMax = 8, // 64
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pendingMax = 8, // 64 ; irrelevant? only for SMP?
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withWriteAggregation = true // required if memDataWidth > 32
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),
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dBusCmdMasterPipe = false, // prohibited if memDataWidth > 32
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@ -68,8 +68,8 @@ object GenGoblinAccel { // extends App {
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new DecoderSimplePlugin(
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catchIllegalInstruction = false
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),
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new RegFilePlugin(
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regFileReadyKind = plugin.SYNC,
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new RegFileOddEvenPlugin(
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regFileReadyKind = plugin.ASYNC, // FIXME why is even-odd failing with SYNC??? (and what's the difference...)
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zeroBoot = false
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),
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new IntAluPlugin,
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@ -83,7 +83,7 @@ object GenGoblinAccel { // extends App {
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//new BitManipZbaPlugin(earlyInjection = false), // sh.add
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//new BitManipZbbPlugin(earlyInjection = false), // zero-ext, min/max, others
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//new BitManipZbtPlugin(earlyInjection = false), // cmov, cmix, funnel
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new CG6Plugin(earlyInjection = false),
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new CG6Plugin(earlyInjection = false), // full-custom list
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new HazardSimplePlugin(
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bypassExecute = true,
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bypassMemory = true,
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File diff suppressed because it is too large
Load Diff
@ -81,6 +81,8 @@ struct goblin_accel_regs {
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//#include "./rvintrin.h"
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#include "ldsdsupport.h"
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void from_reset(void) __attribute__ ((noreturn)); // nothrow,
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static inline void flush_cache(void) {
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@ -376,6 +378,17 @@ static void rectfill(const unsigned_param_type xd,
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}
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if (wi > 3) {
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unsigned int u32color = (unsigned int)u8color | ((unsigned int)u8color)<<8 | ((unsigned int)u8color)<<16 | ((unsigned int)u8color)<<24;
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if ((wi>15) && (((unsigned int)dptr_elt&0x7)==0)) {
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register unsigned int s8 asm("s8");
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register unsigned int s9 asm("s9");
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s8 = u32color;
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s9 = u32color;
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for ( ; i < (wi-15) ; i+=16) {
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sd(dptr_elt, 0, 0, s8, s9);
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sd(dptr_elt, 8, 0, s8, s9);
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dptr_elt += 16;
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}
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}
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for ( ; i < (wi-3) ; i+=4) {
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*(unsigned int*)dptr_elt = u32color;
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dptr_elt +=4;
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@ -733,9 +746,138 @@ static void invert(const unsigned_param_type xd,
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BLIT_FWD_BWD(NAME, OP) \
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BLIT_BWD_FWD(NAME, OP) \
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#define BLIT_NOTALLDIR(NAME, OP) \
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BLIT_FWD_BWD(NAME, OP) \
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BLIT_BWD_FWD(NAME, OP) \
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BLIT_ALLDIR(copy, COPY)
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//BLIT_ALLDIR(copy, COPY)
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BLIT_NOTALLDIR(copy, COPY)
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BLIT_ALLDIR(xor, XOR)
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BLIT_ALLDIR(copy_pm, COPY_PM)
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BLIT_ALLDIR(xor_pm, XOR_PM)
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static void bitblit_fwd_fwd_copy(const unsigned_param_type xs,
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const unsigned_param_type ys,
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const unsigned_param_type wi,
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const unsigned_param_type re,
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const unsigned_param_type xd,
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const unsigned_param_type yd,
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const unsigned char pm,
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unsigned char* src_ptr,
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unsigned char* dst_ptr,
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const unsigned_param_type src_stride,
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const unsigned_param_type dst_stride) {
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unsigned int j;
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unsigned char *sptr = (src_ptr + (ys * src_stride) + xs);
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unsigned char *dptr = (dst_ptr + (yd * dst_stride) + xd);
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unsigned char *sptr_line = sptr;
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unsigned char *dptr_line = dptr;
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/*const unsigned char npm = ~pm;*/
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for (j = 0 ; j < re ; j++) {
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register unsigned char *sptr_elt = sptr_line;
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unsigned char *dptr_elt = dptr_line;
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const unsigned char *dptr_elt_last = dptr_line + wi;
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if (wi>3) {
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if ((xs & 0x3) != (xd & 0x3)) {
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/* align dest, we'll deal with src via shift realignement using fsr */
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for ( ; (dptr_elt < dptr_elt_last) && ((unsigned int)dptr_elt&0x3)!=0; ) {
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dptr_elt[0] = sptr_elt[0];
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dptr_elt ++;
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sptr_elt ++;
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}
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unsigned char *sptr_elt_al = (unsigned char*)((unsigned int)sptr_elt & ~0x3);
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unsigned int fsr_cst = 8*((unsigned int)sptr_elt & 0x3);
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unsigned int src0 = ((unsigned int*)sptr_elt_al)[0];
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unsigned int u32pm = (unsigned int)pm | ((unsigned int)pm)<<8 | ((unsigned int)pm)<<16 | ((unsigned int)pm)<<24;
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/* handle unaligned src */
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for ( ; (dptr_elt < (dptr_elt_last-3)) ; ) {
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unsigned int src1 = ((unsigned int*)sptr_elt_al)[1];
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unsigned int val;
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asm("fsr %0, %1, %2, %3\n" : "=r"(val) : "r"(src0), "r"(src1), "r"(fsr_cst));
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((unsigned int*)dptr_elt)[0] = val;
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src0 = src1;
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dptr_elt += 4;
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sptr_elt_al += 4;
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}
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sptr_elt = sptr_elt_al + ((unsigned int)sptr_elt & 0x3);
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} else {
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const unsigned int u32pm = (unsigned int)pm | ((unsigned int)pm)<<8 | ((unsigned int)pm)<<16 | ((unsigned int)pm)<<24;
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const unsigned char* dptr_elt_end = dptr_elt + wi;
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||||
/* align dest & src (they are aligned the same here) */
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||||
for ( ; (dptr_elt < dptr_elt_last) && ((unsigned int)dptr_elt&0x3)!=0; ) {
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||||
dptr_elt[0] = sptr_elt[0];
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||||
dptr_elt ++;
|
||||
sptr_elt ++;
|
||||
}
|
||||
/* align to 8 for ls/sd */
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||||
for ( ; (dptr_elt < (dptr_elt_last-3)) && ((unsigned int)dptr_elt&0x7)!=0;) {
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||||
((unsigned int*)dptr_elt)[0] = ((unsigned int*)sptr_elt)[0];
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||||
dptr_elt += 4;
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sptr_elt += 4;
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||||
}
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||||
#if 0
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for ( ; (dptr_elt < (dptr_elt_last-31)) ; ) {
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register unsigned int s4 asm("s4");
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register unsigned int s5 asm("s5");
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register unsigned int s6 asm("s6");
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register unsigned int s7 asm("s7");
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register unsigned int s8 asm("s8");
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register unsigned int s9 asm("s9");
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register unsigned int s10 asm("s10");
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register unsigned int s11 asm("s11");
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ld(sptr_elt, 0, s4, s5);
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ld(sptr_elt, 16, s8, s9);
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ld(sptr_elt, 8, s6, s7);
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sd(dptr_elt, 0, 0, s4, s5);
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sd(dptr_elt, 8, 0, s6, s7);
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ld(sptr_elt, 24, s10, s11);
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sd(dptr_elt, 16, 0, s8, s9);
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sptr_elt += 32;
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sd(dptr_elt, 24, 0, s10, s11);
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||||
dptr_elt += 32;
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||||
|
||||
}
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||||
#endif
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||||
for ( ; (dptr_elt < (dptr_elt_last-15)) ; ) {
|
||||
register unsigned int s8 asm("s8");
|
||||
register unsigned int s9 asm("s9");
|
||||
register unsigned int s10 asm("s10");
|
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register unsigned int s11 asm("s11");
|
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ld(sptr_elt, 0, s8, s9);
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ld(sptr_elt, 8, s10, s11);
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sd(dptr_elt, 0, 0, s8, s9);
|
||||
sptr_elt += 16;
|
||||
sd(dptr_elt, 8, 0, s10, s11);
|
||||
dptr_elt += 16;
|
||||
}
|
||||
#if 0
|
||||
for ( ; (dptr_elt < (dptr_elt_last-7)) ; ) {
|
||||
register unsigned int s8 asm("s8");
|
||||
register unsigned int s9 asm("s9");
|
||||
ld(sptr_elt, 0, s8, s9);
|
||||
sd(dptr_elt, 0, 0, s8, s9);
|
||||
sptr_elt += 8;
|
||||
dptr_elt += 8;
|
||||
}
|
||||
#endif
|
||||
for ( ; (dptr_elt < (dptr_elt_last-3)) ; ) {
|
||||
((unsigned int*)dptr_elt)[0] = ((unsigned int*)sptr_elt)[0];
|
||||
dptr_elt += 4;
|
||||
sptr_elt += 4;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* common tail loop */
|
||||
for ( ; dptr_elt < dptr_elt_last ; ) {
|
||||
dptr_elt[0] = sptr_elt[0];
|
||||
dptr_elt ++;
|
||||
sptr_elt ++;
|
||||
}
|
||||
sptr_line += src_stride;
|
||||
dptr_line += dst_stride;
|
||||
}
|
||||
}
|
||||
|
||||
@ -15,7 +15,7 @@ GCCPFX=riscv32-buildroot-linux-gnu-
|
||||
GCC=${GCCDIR}/bin/${GCCPFX}gcc
|
||||
OBJCOPY=${GCCDIR}/bin/${GCCPFX}objcopy
|
||||
|
||||
OPT=-Os #-fno-inline
|
||||
OPT=-O3 #-fno-inline
|
||||
ARCH=rv32im_zba_zbb_zbt
|
||||
|
||||
PARAM="-DBASE_FB=${BASE_FB}"
|
||||
|
||||
84
nubus-to-ztex-gateware/ldsdsupport.h
Normal file
84
nubus-to-ztex-gateware/ldsdsupport.h
Normal file
@ -0,0 +1,84 @@
|
||||
#pragma once
|
||||
|
||||
asm(".set regnum_x0 , 0");
|
||||
asm(".set regnum_x1 , 1");
|
||||
asm(".set regnum_x2 , 2");
|
||||
asm(".set regnum_x3 , 3");
|
||||
asm(".set regnum_x4 , 4");
|
||||
asm(".set regnum_x5 , 5");
|
||||
asm(".set regnum_x6 , 6");
|
||||
asm(".set regnum_x7 , 7");
|
||||
asm(".set regnum_x8 , 8");
|
||||
asm(".set regnum_x9 , 9");
|
||||
asm(".set regnum_x10 , 10");
|
||||
asm(".set regnum_x11 , 11");
|
||||
asm(".set regnum_x12 , 12");
|
||||
asm(".set regnum_x13 , 13");
|
||||
asm(".set regnum_x14 , 14");
|
||||
asm(".set regnum_x15 , 15");
|
||||
asm(".set regnum_x16 , 16");
|
||||
asm(".set regnum_x17 , 17");
|
||||
asm(".set regnum_x18 , 18");
|
||||
asm(".set regnum_x19 , 19");
|
||||
asm(".set regnum_x20 , 20");
|
||||
asm(".set regnum_x21 , 21");
|
||||
asm(".set regnum_x22 , 22");
|
||||
asm(".set regnum_x23 , 23");
|
||||
asm(".set regnum_x24 , 24");
|
||||
asm(".set regnum_x25 , 25");
|
||||
asm(".set regnum_x26 , 26");
|
||||
asm(".set regnum_x27 , 27");
|
||||
asm(".set regnum_x28 , 28");
|
||||
asm(".set regnum_x29 , 29");
|
||||
asm(".set regnum_x30 , 30");
|
||||
asm(".set regnum_x31 , 31");
|
||||
|
||||
asm(".set regnum_zero, 0");
|
||||
asm(".set regnum_ra , 1");
|
||||
asm(".set regnum_sp , 2");
|
||||
asm(".set regnum_gp , 3");
|
||||
asm(".set regnum_tp , 4");
|
||||
asm(".set regnum_t0 , 5");
|
||||
asm(".set regnum_t1 , 6");
|
||||
asm(".set regnum_t2 , 7");
|
||||
asm(".set regnum_s0 , 8");
|
||||
asm(".set regnum_s1 , 9");
|
||||
asm(".set regnum_a0 , 10");
|
||||
asm(".set regnum_a1 , 11");
|
||||
asm(".set regnum_a2 , 12");
|
||||
asm(".set regnum_a3 , 13");
|
||||
asm(".set regnum_a4 , 14");
|
||||
asm(".set regnum_a5 , 15");
|
||||
asm(".set regnum_a6 , 16");
|
||||
asm(".set regnum_a7 , 17");
|
||||
asm(".set regnum_s2 , 18");
|
||||
asm(".set regnum_s3 , 19");
|
||||
asm(".set regnum_s4 , 20");
|
||||
asm(".set regnum_s5 , 21");
|
||||
asm(".set regnum_s6 , 22");
|
||||
asm(".set regnum_s7 , 23");
|
||||
asm(".set regnum_s8 , 24");
|
||||
asm(".set regnum_s9 , 25");
|
||||
asm(".set regnum_s10 , 26");
|
||||
asm(".set regnum_s11 , 27");
|
||||
asm(".set regnum_t3 , 28");
|
||||
asm(".set regnum_t4 , 29");
|
||||
asm(".set regnum_t5 , 30");
|
||||
asm(".set regnum_t6 , 31");
|
||||
|
||||
#define opcode_ld(opcode, func3, base, imm12, o1, o2) \
|
||||
asm volatile(".word ((" #opcode ") | (regnum_%0 << 7) | (regnum_%2 << 15) | (" #imm12 " << 20) | ((" #func3 ") << 12));" \
|
||||
: "=&r" (o1), "=&r" (o2) \
|
||||
: "r" (base) \
|
||||
); \
|
||||
|
||||
#define ld(base, imm12, o1, o2) opcode_ld(0x03, 0x03, base, imm12, o1, o2)
|
||||
#define ldu(base, imm12, o1, o2) opcode_ld(0x03, 0x07, base, imm12, o1, o2)
|
||||
|
||||
#define opcode_sd(opcode, func3, base, imm04, imm511, i1, i2) \
|
||||
asm volatile(".word ((" #opcode ") | (" #imm04 " << 7) | (regnum_%0 << 15) | (regnum_%1 << 20) | (" #imm511 " << 25) | ((" #func3 ") << 12));" \
|
||||
: \
|
||||
: "r" (base), "r" (i1), "r" (i2) \
|
||||
); \
|
||||
|
||||
#define sd(base, imm04, imm511, i1, i2) opcode_sd(0x23, 0x03, base, imm04, imm511, i1, i2)
|
||||
Loading…
Reference in New Issue
Block a user