Macintosh-HW
/
NuBusFPGA
mirror of https://github.com/rdolbeau/NuBusFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

move to submodules XiBus

This commit is contained in:
Romain Dolbeau 2022-10-31 15:28:08 +01:00
parent 513ba19e29
commit 239b74823f
4 changed files with 18 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitmodules vendored
View File

@ -1,3 +1,4 @@
[submodule "nubus-to-ztex-gateware/XiBus"]
path = nubus-to-ztex-gateware/XiBus
url = git@github.com:rdolbeau/XiBus.git
branch = more_fixes

2
nubus-to-ztex-gateware/XiBus

@ -1 +1 @@
Subproject commit 44d7267ff802b54cebda7e0a643a90cff71247e4
Subproject commit e20f6ca7c45900e841464b6bfd296a245093ca0a

16
nubus-to-ztex-gateware/nubus.py
View File

@ -110,11 +110,11 @@ class NuBus(Module):
def add_sources(self, platform):
platform.add_source("nubus.v", "verilog")
# XiBus is from my github, branch 'more_fixes'
platform.add_source("/home/dolbeau/XiBus/nubus.svh", "verilog")
#platform.add_source("/home/dolbeau/XiBus/nubus_arbiter.v", "verilog") # in the CPLD
platform.add_source("/home/dolbeau/XiBus/nubus_cpubus.v", "verilog")
platform.add_source("/home/dolbeau/XiBus/nubus_driver.v", "verilog")
#platform.add_source("/home/dolbeau/XiBus/nubus_errors.v", "verilog") # unused
platform.add_source("/home/dolbeau/XiBus/nubus_membus.v", "verilog")
platform.add_source("/home/dolbeau/XiBus/nubus_master.v", "verilog")
platform.add_source("/home/dolbeau/XiBus/nubus_slave.v", "verilog")
platform.add_source("XiBus/nubus.svh", "verilog")
#platform.add_source("XiBus/nubus_arbiter.v", "verilog") # in the CPLD
platform.add_source("XiBus/nubus_cpubus.v", "verilog")
platform.add_source("XiBus/nubus_driver.v", "verilog")
#platform.add_source("XiBus/nubus_errors.v", "verilog") # unused
platform.add_source("XiBus/nubus_membus.v", "verilog")
platform.add_source("XiBus/nubus_master.v", "verilog")
platform.add_source("XiBus/nubus_slave.v", "verilog")

8
nubus-to-ztex-gateware/nubus_to_fpga_soc.py
View File

@ -317,6 +317,14 @@ class NuBusFPGA(SoCCore):
self.submodules.wishbone2nubus = ClockDomainsRenamer("nubus")(Wishbone2NuBus(nubus=self.nubus,wb=wishbone_slave_nubus))
self.submodules.wishbone_slave_sys = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_slave_nubus, cd_master="sys", cd_slave="nubus")
self.bus.add_slave("DMA", self.wishbone_slave_sys, SoCRegion(origin=self.mem_map.get("master", None), size=0x40000000, cached=False))
irq_line = self.platform.request("nmrq_3v3_n") # active low
fb_irq = Signal() # active low
led0 = platform.request("user_led", 0)
self.comb += [
led0.eq(~fb_irq),
]
self.comb += irq_line.eq(fb_irq) # active low, enable if one is low
else:
sampling = 1
wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)