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This commit is contained in:
Romain Dolbeau 2022-11-01 12:41:58 +01:00
parent b621ee2eb5
commit 93e7cd20c1
5 changed files with 41 additions and 39 deletions
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38
nubus-to-ztex-gateware/nubus.py
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@ -57,8 +57,10 @@ class NuBus(Module):
grant = Signal() grant = Signal()
tmoen = Signal() tmoen = Signal()
self.nubus_oe = nubus_oe = Signal() # improveme
# those are needed in both Nubus and cpld integrated part now # those are needed in both Nubus and cpld integrated part now
broadcast_id_3v3_n = plaform.request("id_3v3_n") broadcast_id_3v3_n = platform.request("id_3v3_n")
# those are 'return' signals (O part of IO separated in I and O) # those are 'return' signals (O part of IO separated in I and O)
# the 3v3 signals 'see' the 5V signals from the external drivers # the 3v3 signals 'see' the 5V signals from the external drivers
internal_start_3v3_n = Signal() internal_start_3v3_n = Signal()
@ -85,11 +87,11 @@ class NuBus(Module):
i_nub_startn = platform.request("start_3v3_n"), i_nub_startn = platform.request("start_3v3_n"),
i_nub_rqstn = platform.request("rqst_3v3_n"), i_nub_rqstn = platform.request("rqst_3v3_n"),
i_nub_ackn = platform.request("ack_3v3_n"), i_nub_ackn = platform.request("ack_3v3_n"),
o_nub_tm0n = internal_tm0_3v3_n, o_nub_tm0n_o = internal_tm0_3v3_n,
o_nub_tm1n = internal_tm1_3v3_n, o_nub_tm1n_o = internal_tm1_3v3_n,
o_nub_startn = internal_start_3v3_n, o_nub_startn_o = internal_start_3v3_n,
o_nub_rqstn = internal_rqst_3v3_n, o_nub_rqstn_o = internal_rqst_3v3_n,
o_nub_ackn = internal_ack_3v3_n, o_nub_ackn_o = internal_ack_3v3_n,
# io_nub_arbn = platform.request("nubus_arb_n"), # io_nub_arbn = platform.request("nubus_arb_n"),
o_arbcy_n = arbcy_n, # internal now o_arbcy_n = arbcy_n, # internal now
i_grant = grant, # internal now i_grant = grant, # internal now
@ -124,10 +126,10 @@ class NuBus(Module):
i_nub_clk2xn = ClockSignal(cd_nubus90), i_nub_clk2xn = ClockSignal(cd_nubus90),
i_nub_tm2n = platform.request("tm2_3v3_n"), i_nub_tm2n = platform.request("tm2_3v3_n"),
o_nub_tm2n = internal_tm2_3v3_n, o_nub_tm2n_o = internal_tm2_3v3_n,
) )
self.specials += Instance("nubus_cpldinfpga", self.specials += Instance("nubus_cpldinfpga",
i_nubus_oe = nubus_oe, # FIXME: handled in soc i_nubus_oe = nubus_oe, # improveme: handled in soc
i_tmoen = tmoen, i_tmoen = tmoen,
i_nubus_master_dir = nubus_master_dir, i_nubus_master_dir = nubus_master_dir,
i_rqst_oe_n = rqst_oe_n, i_rqst_oe_n = rqst_oe_n,
@ -140,26 +142,26 @@ class NuBus(Module):
o_grant = grant, o_grant = grant,
i_tm0_n_3v3 = internal_tm0_3v3_n, # tm0 driving controlled by tmoen i_tm0_n_3v3 = internal_tm0_3v3_n, # tm0 driving controlled by tmoen
o_tm0_o_n = platform.request("tm_o_n"), o_tm0_o_n = platform.request("tm0_o_n"),
i_tm1_n_3v3 = internal_tm1_3v3_n, # tm1 driving controlled by tmoen i_tm1_n_3v3 = internal_tm1_3v3_n, # tm1 driving controlled by tmoen
o_tm1_o_n = platform_request("tm1_o_n"), o_tm1_o_n = platform.request("tm1_o_n"),
o_tmx_oe_n = platform_request("tmx_oe_n"), o_tmx_oe_n = platform.request("tmx_oe_n"),
i_tm2_n_3v3 = internal_tm2_3v3_n, # tm2 currently never driven i_tm2_n_3v3 = internal_tm2_3v3_n, # tm2 currently never driven
o_tm2_o_n = platform_request("tm2_o_n"), o_tm2_o_n = platform.request("tm2_o_n"),
o_tm2_oe_n = platform_request("tm2_oe_n"), o_tm2_oe_n = platform.request("tm2_oe_n"),
i_start_n_3v3 = internal_start_3v3_n, # start driving enabled by nubus_master_dir i_start_n_3v3 = internal_start_3v3_n, # start driving enabled by nubus_master_dir
o_start_o_n = platform_request("start_o_n"), o_start_o_n = platform.request("start_o_n"),
o_start_oe_n = platform_request("start_oe_n"), o_start_oe_n = platform.request("start_oe_n"),
i_ack_n_3v3 = internal_ack_3v3_n, # ack driving controlled by tmoen i_ack_n_3v3 = internal_ack_3v3_n, # ack driving controlled by tmoen
o_ack_o_n = platform_request("ack_o_n"), o_ack_o_n = platform.request("ack_o_n"),
o_ack_oe_n = platform_request("ack_oe_n"), o_ack_oe_n = platform.request("ack_oe_n"),
i_rqst_n_3v3 = internal_rqst_3v3_n, # rqst driving ocntroller by rqst_oe_n i_rqst_n_3v3 = internal_rqst_3v3_n, # rqst driving ocntroller by rqst_oe_n
o_rqst_o_n = platform_request("rqst_o_n") o_rqst_o_n = platform.request("rqst_o_n")
) )

1
nubus-to-ztex-gateware/nubus_cpldinfpga.v
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@ -43,7 +43,6 @@ module nubus_cpldinfpga
); );
// placeholders // placeholders
assign tm2_n_3v3 = tm2_n_5v;
assign tm2_o_n = 0; assign tm2_o_n = 0;
assign tm2_oe_n = 1; assign tm2_oe_n = 1;

13
nubus-to-ztex-gateware/nubus_to_fpga_soc.py
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@ -247,7 +247,7 @@ class NuBusFPGA(SoCCore):
#self.submodules.wa2d = WA2D(self.platform) #self.submodules.wa2d = WA2D(self.platform)
#self.bus.add_slave("WA2D", self.wa2d.bus, SoCRegion(origin=0x00C00000, size=0x00400000, cached=False)) #self.bus.add_slave("WA2D", self.wa2d.bus, SoCRegion(origin=0x00C00000, size=0x00400000, cached=False))
notsimul = 1 notsimul = 0
if (notsimul): if (notsimul):
avail_sdram = 0 avail_sdram = 0
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
@ -303,13 +303,14 @@ class NuBusFPGA(SoCCore):
# Interface NuBus to wishbone # Interface NuBus to wishbone
# we need to cross clock domains # we need to cross clock domains
xibus=0 xibus=1
if (xibus): if (xibus):
wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width) wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys") self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys) self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys)
self.submodules.nubus = nubus.NuBus(platform=platform, cd_nubus="nubus") self.submodules.nubus = nubus.NuBus(platform=platform, cd_nubus="nubus")
#self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus)) #self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus))
self.comb += self.nubus.nubus_oe.eq(hold_reset) # improveme
nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width) nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
self.submodules.nubus2wishbone = NuBus2WishboneFIFO(platform=self.platform,nubus=self.nubus,wb_read=self.wishbone_master_nubus,wb_write=nubus_writemaster_sys) self.submodules.nubus2wishbone = NuBus2WishboneFIFO(platform=self.platform,nubus=self.nubus,wb_read=self.wishbone_master_nubus,wb_write=nubus_writemaster_sys)
self.bus.add_master(name="NuBusBridgeToWishboneWrite", master=nubus_writemaster_sys) self.bus.add_master(name="NuBusBridgeToWishboneWrite", master=nubus_writemaster_sys)
@ -321,10 +322,10 @@ class NuBusFPGA(SoCCore):
irq_line = self.platform.request("nmrq_3v3_n") # active low irq_line = self.platform.request("nmrq_3v3_n") # active low
fb_irq = Signal() # active low fb_irq = Signal() # active low
led0 = platform.request("user_led", 0) #led0 = platform.request("user_led", 0)
self.comb += [ #self.comb += [
led0.eq(~fb_irq), # led0.eq(~fb_irq),
] #]
self.comb += irq_line.eq(fb_irq) # active low, enable if one is low self.comb += irq_line.eq(fb_irq) # active low, enable if one is low
else: else:
sampling = 1 sampling = 1

10
nubus-to-ztex-gateware/slave_V1.2_tb.sv
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@ -134,19 +134,15 @@ module nubus_slave_tb ();
.A({reset_n_3v3, tm2_n_3v3, tm0_n_3v3, tm1_n_3v3}), .A({reset_n_3v3, tm2_n_3v3, tm0_n_3v3, tm1_n_3v3}),
.B({nub_resetn, nub_tm2n, nub_tm0n, nub_tm1n })); .B({nub_resetn, nub_tm2n, nub_tm0n, nub_tm1n }));
assign clk2x_n_3v3 = nub_clk2n; assign clk2x_n_3v3 = nub_clk2xn;
ztex213_nubus_V1_2 UNuBus ( ztex213_nubus_V1_2 UNuBus (
// NuBus lines only // NuBus lines only
.clk48(bd_clk48), .clk48(bd_clk48),
.clk_3v3_n(clk_n_3v3), .clk_3v3_n(clk_n_3v3),
.reset_3v3_n(reset_n_3v3), .reset_3v3_n(reset_n_3v3),
.nubus_clk2x_n(clk2x_n_3v3),
.user_led0(leds[0]), .user_led0(leds[0]),
.user_led1(leds[1]), .user_led1(leds[1]),
.user_led2(leds[2]),
.user_led3(leds[3]),
.nubus_tm2_n(tm2_n_3v3),
.id_3v3_n(id_n_3v3), .id_3v3_n(id_n_3v3),
.ad_3v3_n(ad_n_3v3), .ad_3v3_n(ad_n_3v3),
.tm0_3v3_n(tm0_n_3v3), .tm0_3v3_n(tm0_n_3v3),
@ -160,10 +156,10 @@ module nubus_slave_tb ();
.rqst_3v3_n(rqst_n_3v3), .rqst_3v3_n(rqst_n_3v3),
.rqst_o_n(rqst_o_n), .rqst_o_n(rqst_o_n),
.nmrq_3v3_n(nmrq_n_3v3), // output only, direct to driver .nmrq_3v3_n(nmrq_n_3v3), // output only, direct to driver
.ack_3v3_n(ack_n_3v3), .ack_3v3_n(ack_3v3_n),
.ack_o_n(ack_o_n), .ack_o_n(ack_o_n),
.ack_oe_n(ack_oe_n), .ack_oe_n(ack_oe_n),
.arb_n_3v3(arb_n_3v3), .arb_3v3_n(arb_3v3_n),
.arb_o_n(arb_o_n), .arb_o_n(arb_o_n),
.nubus_ad_dir(nubus_ad_dir), .nubus_ad_dir(nubus_ad_dir),
.nubus_oe(nubus_oe), .nubus_oe(nubus_oe),

18
nubus-to-ztex-gateware/ztex213_nubus.py
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@ -202,7 +202,7 @@ _nubus_nubus_v1_2 = [
("tm2_oe_n", 0, Pins("R6"), IOStandard("lvttl")), ("tm2_oe_n", 0, Pins("R6"), IOStandard("lvttl")),
("nubus_oe", 0, Pins("G13"), IOStandard("lvttl")), ("nubus_oe", 0, Pins("G13"), IOStandard("lvttl")),
("nubus_ad_dir", 0, Pins("G17"), IOStandard("lvttl"))), ("nubus_ad_dir", 0, Pins("G17"), IOStandard("lvttl")),
] ]
# Connectors --------------------------------------------------------------------------------------- # Connectors ---------------------------------------------------------------------------------------
@ -214,10 +214,10 @@ connectors_v1_2 = [
# Ethernet ---------------------------------------------------------------------------------------------- # Ethernet ----------------------------------------------------------------------------------------------
# custom not-quite-pmod # custom not-quite-pmod
def rmii_eth_pmod_io(extpmod): def rmii_eth_extpmod_io(extpmod):
return [ return [
("eth_clocks", 0, ("eth_clocks", 0,
Subsignal("ref_clk", Pins(f"{extpmod}:10"))), Subsignal("ref_clk", Pins(f"{extpmod}:10")),
IOStandard("LVCMOS33"), IOStandard("LVCMOS33"),
), ),
("eth", 0, ("eth", 0,
@ -225,12 +225,12 @@ def rmii_eth_pmod_io(extpmod):
Subsignal("rx_data", Pins(f"{extpmod}:8 {extpmod}:11")), Subsignal("rx_data", Pins(f"{extpmod}:8 {extpmod}:11")),
Subsignal("crs_dv", Pins(f"{extpmod}:6")), Subsignal("crs_dv", Pins(f"{extpmod}:6")),
Subsignal("tx_en", Pins(f"{extpmod}:2")), Subsignal("tx_en", Pins(f"{extpmod}:2")),
Subsignal("tx_data", Pins(f"{extpmod}:0 {extpmod}:1"))), Subsignal("tx_data", Pins(f"{extpmod}:0 {extpmod}:1")),
Subsignal("mdc", Pins(f"{extpmod}:4")), Subsignal("mdc", Pins(f"{extpmod}:4")),
Subsignal("mdio", Pins(f"{extpmod}:7")), Subsignal("mdio", Pins(f"{extpmod}:7")),
Subsignal("rx_er", Pins(f"{extpmod}:9"))), Subsignal("rx_er", Pins(f"{extpmod}:9")),
Subsignal("int_n", Pins(f"{extpmod}:5"))), Subsignal("int_n", Pins(f"{extpmod}:5")),
IOStandard("LVCMOS33") IOStandard("LVCMOS33"),
), ),
] ]
_rmii_eth_extpmod_io_v1_2 = rmii_eth_extpmod_io("P1") _rmii_eth_extpmod_io_v1_2 = rmii_eth_extpmod_io("P1")
@ -257,6 +257,10 @@ class Platform(XilinxPlatform):
"V1.0" : _nubus_nubus_v1_0, "V1.0" : _nubus_nubus_v1_0,
"V1.2" : _nubus_nubus_v1_2, "V1.2" : _nubus_nubus_v1_2,
}[version] }[version]
connectors = {
"V1.0" : connectors_v1_0,
"V1.2" : connectors_v1_2,
}[version]
self.speedgrade = -1 self.speedgrade = -1
if (device[-1] == '2'): if (device[-1] == '2'):
self.speedgrade = -2 self.speedgrade = -2