draft integration of CPLD in FPGA - can't have internal tri-state signals...
This commit is contained in:
Romain Dolbeau
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b621ee2eb5
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@ -49,8 +49,25 @@ class NuBus(Module):
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#self.sync.nubus += [ grant_mem.eq(grant | grant_mem) ]
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#self.comb += pad_user_led_0.eq(arbcy_n_mem)
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#self.comb += pad_user_led_1.eq(grant_mem)
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# FPGA<->CPLD only, now internal signal
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nubus_master_dir = Signal()
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rqst_oe_n = Signal()
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arbcy_n = Signal()
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grant = Signal()
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tmoen = Signal()
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# those are needed in both Nubus and cpld integrated part now
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broadcast_id_3v3_n = plaform.request("id_3v3_n")
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# those are 'return' signals (O part of IO separated in I and O)
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# the 3v3 signals 'see' the 5V signals from the external drivers
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internal_start_3v3_n = Signal()
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internal_tm0_3v3_n = Signal()
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internal_tm1_3v3_n = Signal()
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internal_tm2_3v3_n = Signal()
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internal_ack_3v3_n = Signal()
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internal_rqst_3v3_n = Signal()
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#fixme: parameters
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self.specials += Instance(self.get_netlist_name(),
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# master side
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#p_SIMPLE_MAP = 0x0,
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@ -60,20 +77,25 @@ class NuBus(Module):
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p_LOCAL_SPACE_EXPOSED_TO_NUBUS = 0,
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i_nub_clkn = ClockSignal(cd_nubus),
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i_nub_resetn = ~ResetSignal(cd_nubus),
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i_nub_idn = platform.request("id_3v3_n"),
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i_nub_idn = broadcast_id_3v3_n, # internal now
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# io_nub_pfwn = self.nubus_pwf_n,
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io_nub_adn = platform.request("ad_3v3_n"),
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io_nub_tm0n = platform.request("tm0_3v3_n"),
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io_nub_tm1n = platform.request("tm1_3v3_n"),
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io_nub_startn = platform.request("start_3v3_n"),
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io_nub_rqstn = platform.request("rqst_3v3_n"),
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io_nub_ackn = platform.request("ack_3v3_n"),
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i_nub_tm0n = platform.request("tm0_3v3_n"),
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i_nub_tm1n = platform.request("tm1_3v3_n"),
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i_nub_startn = platform.request("start_3v3_n"),
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i_nub_rqstn = platform.request("rqst_3v3_n"),
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i_nub_ackn = platform.request("ack_3v3_n"),
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o_nub_tm0n = internal_tm0_3v3_n,
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o_nub_tm1n = internal_tm1_3v3_n,
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o_nub_startn = internal_start_3v3_n,
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o_nub_rqstn = internal_rqst_3v3_n,
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o_nub_ackn = internal_ack_3v3_n,
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# io_nub_arbn = platform.request("nubus_arb_n"),
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o_arbcy_n = platform.request("arbcy_n"),
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i_grant = platform.request("grant"),
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o_tmoen = platform.request("tmoen"),
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o_arbcy_n = arbcy_n, # internal now
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i_grant = grant, # internal now
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o_tmoen = tmoen, # internal now
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o_NUBUS_AD_DIR = platform.request("nubus_ad_dir"),
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o_nubus_master_dir = platform.request("nubus_master_dir"),
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o_nubus_master_dir = nubus_master_dir, # internal now
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# io_nub_nmrqn = platform.request("nmrq_3v3_n"),
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# io_nub_spn = self.nubus_sp_n,
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# io_nub_spvn = self.nubus_spv_n,
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@ -98,11 +120,48 @@ class NuBus(Module):
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o_mem_super = self.mem_super,
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o_mem_local = self.mem_local,
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o_fpga_to_cpld_signal = platform.request("fpga_to_cpld_signal"),
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o_fpga_to_cpld_signal = rqst_oe_n, # internal now
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i_nub_clk2xn = ClockSignal(cd_nubus90),
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io_nub_tm2n = platform.request("tm2_3v3_n"),
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i_nub_tm2n = platform.request("tm2_3v3_n"),
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o_nub_tm2n = internal_tm2_3v3_n,
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)
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self.specials += Instance("nubus_cpldinfpga",
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i_nubus_oe = nubus_oe, # FIXME: handled in soc
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i_tmoen = tmoen,
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i_nubus_master_dir = nubus_master_dir,
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i_rqst_oe_n = rqst_oe_n,
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i_id_n_3v3 = broadcast_id_3v3_n, # input only
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i_arbcy_n = arbcy_n,
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i_arb_n_3v3 = platform.request("arb_3v3_n"), # arb only seen by cpld
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o_arb_o_n = platform.request("arb_o_n"),
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o_grant = grant,
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i_tm0_n_3v3 = internal_tm0_3v3_n, # tm0 driving controlled by tmoen
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o_tm0_o_n = platform.request("tm_o_n"),
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i_tm1_n_3v3 = internal_tm1_3v3_n, # tm1 driving controlled by tmoen
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o_tm1_o_n = platform_request("tm1_o_n"),
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o_tmx_oe_n = platform_request("tmx_oe_n"),
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i_tm2_n_3v3 = internal_tm2_3v3_n, # tm2 currently never driven
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o_tm2_o_n = platform_request("tm2_o_n"),
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o_tm2_oe_n = platform_request("tm2_oe_n"),
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i_start_n_3v3 = internal_start_3v3_n, # start driving enabled by nubus_master_dir
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o_start_o_n = platform_request("start_o_n"),
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o_start_oe_n = platform_request("start_oe_n"),
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i_ack_n_3v3 = internal_ack_3v3_n, # ack driving controlled by tmoen
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o_ack_o_n = platform_request("ack_o_n"),
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o_ack_oe_n = platform_request("ack_oe_n"),
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i_rqst_n_3v3 = internal_rqst_3v3_n, # rqst driving ocntroller by rqst_oe_n
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o_rqst_o_n = platform_request("rqst_o_n")
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)
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def get_netlist_name(self):
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return "nubus"
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@ -111,10 +170,11 @@ class NuBus(Module):
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platform.add_source("nubus.v", "verilog")
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# XiBus is from my github, branch 'more_fixes'
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platform.add_source("XiBus/nubus.svh", "verilog")
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#platform.add_source("XiBus/nubus_arbiter.v", "verilog") # in the CPLD
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#platform.add_source("XiBus/nubus_arbiter.v", "verilog") # in the CPLDinfpga
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platform.add_source("XiBus/nubus_cpubus.v", "verilog")
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platform.add_source("XiBus/nubus_driver.v", "verilog")
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#platform.add_source("XiBus/nubus_errors.v", "verilog") # unused
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platform.add_source("XiBus/nubus_membus.v", "verilog")
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platform.add_source("XiBus/nubus_master.v", "verilog")
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platform.add_source("XiBus/nubus_slave.v", "verilog")
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platform.add_source("nubus_cpldinfpga.v", "verilog") # internal now
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@ -28,19 +28,26 @@ module nubus
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(
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/* *** NuBus signals *** */
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/* those are connected to the FPGA */
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/* connected via the CPLD */
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input nub_clkn, // Clock (rising is driving edge, faling is sampling)
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input nub_resetn, // Reset
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input [ 3:0] nub_idn, // Slot Identification
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inout nub_tm0n, // Transfer Mode
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inout nub_tm1n, // Transfer Mode
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inout nub_startn, // Start
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inout nub_rqstn, // Request
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inout nub_ackn, // Acknowledge
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// raw input
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input nub_tm0n, // Transfer Mode
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input nub_tm1n, // Transfer Mode
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input nub_startn, // Start
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input nub_rqstn, // Request
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input nub_ackn, // Acknowledge
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// output to other part of the FPGA
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output nub_tm0n_o, // Transfer Mode
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output nub_tm1n_o, // Transfer Mode
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output nub_startn_o, // Start
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output nub_rqstn_o, // Request
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output nub_ackn_o, // Acknowledge
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// connected via the CPLD but NuBus90 (unimplemented)
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// NuBus90 (unimplemented)
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input nub_clk2xn,
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inout nub_tm2n,
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input nub_tm2n,
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output nub_tm2n_o,
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/* connected via the 74LVT245 */
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inout [31:0] nub_adn, // Address/Data
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@ -260,11 +267,11 @@ module nubus
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.mst_tm0n(cpu_tm0n), // Address lines
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.mst_timeout(mst_timeout),
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.mis_errorn(TMN_COMPLETE),
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.nub_tm0n_o(nub_tm0n), // Transfer mode
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.nub_tm1n_o(nub_tm1n), // Transfer mode
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.nub_ackn_o(nub_ackn), // Achnowlege
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.nub_startn_o(nub_startn), // Transfer start
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.nub_rqstn_o(nub_rqstn), // Bus request
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.nub_tm0n_o(nub_tm0n_o), // Transfer mode
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.nub_tm1n_o(nub_tm1n_o), // Transfer mode
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.nub_ackn_o(nub_ackn_o), // Achnowlege
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.nub_startn_o(nub_startn_o), // Transfer start
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.nub_rqstn_o(nub_rqstn_o), // Bus request
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.nub_rqstoen_o(fpga_to_cpld_signal), // Bus request enable
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.drv_tmoen_o(drv_tmoen), // Transfer mode enable
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.drv_mstdn_o(drv_mstdn) // Guess: Slave sends /ACK. Master responds with /MSTDN, which allows slave to clear /ACK and listen for next transaction.
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@ -0,0 +1,73 @@
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module nubus_cpldinfpga
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(
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// Control
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input nubus_oe, // disable all 5v drivers
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input tmoen, // tm output enable
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input nubus_master_dir, // direction of signals, i.e. are we in master mode
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// Spares
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input rqst_oe_n, // rqstoen (extra line from FPGA to CPLD)
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// NuBus
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input [3:0] id_n_3v3, // nubus ID of this card to FPGA
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// NuBus Arbiter
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input arbcy_n, // enable arbitter
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input [3:0] arb_n_3v3, // NuBus arbiter's lines
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output [3:0] arb_o_n, // NuBus arbiter's control lines
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output grant, // Grant access
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// Cycle Control (NuBus two-way)
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input tm0_n_3v3, // nubus tm0 to/from FPGA
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output tm0_o_n, // start from NuBus
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input tm1_n_3v3, // nubus tm1 to/from FPGA
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output tm1_o_n, // start from NuBus
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output tmx_oe_n, // start from NuBus
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input tm2_n_3v3, // nubus tm2 to/from FPGA
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output tm2_o_n, // start from NuBus
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output tm2_oe_n, // start from NuBus
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input start_n_3v3, // start to/from FPGA
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output start_o_n, // start from NuBus
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output start_oe_n, // start from NuBus
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input ack_n_3v3, // ack from/to FPGA
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output ack_o_n, // ack to NuBus
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output ack_oe_n, // ack OE NuBus
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// Master Request (OC)
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input rqst_n_3v3, // rqst from/to FPGA
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output rqst_o_n // rqst to NuBus
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);
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// placeholders
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assign tm2_n_3v3 = tm2_n_5v;
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assign tm2_o_n = 0;
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assign tm2_oe_n = 1;
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// ~nubus_master_dir-controlled signals
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assign start_o_n = nubus_oe ? 1 : ( nubus_master_dir ? start_n_3v3 : 1); // master out
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assign start_oe_n = nubus_oe ? 1 : ( nubus_master_dir ? 0 : 1); // master out
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// rqst_o_n is always driven (the 74lvt125 wired as open collector will convert 1 to Z) and is active low
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assign rqst_o_n = nubus_oe ? 1 : (~rqst_oe_n ? rqst_n_3v3 : 1); // master out
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assign ack_o_n = nubus_oe ? 1 : (( ~tmoen) ? ack_n_3v3 : 1); // slave out/in
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assign ack_oe_n = nubus_oe ? 1 : (( ~tmoen) ? 0 : 1); // slave out/in
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assign tm0_o_n = nubus_oe ? 1 : (( ~tmoen) ? tm0_n_3v3 : 1); // slave out/in
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assign tm1_o_n = nubus_oe ? 1 : (( ~tmoen) ? tm1_n_3v3 : 1); // slave out/in
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assign tmx_oe_n = nubus_oe ? 1 : (( ~tmoen) ? 0 : 1); // slave out/in
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nubus_arbiter UArbiter
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(
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.idn(id_n_3v3),
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.arbn(arb_n_3v3),
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.arbon(arb_o_n),
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.arbcyn(arbcy_n),
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.grant(grant)
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);
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endmodule // nubus_cpld
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