mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-12-22 10:29:53 +00:00
typos
This commit is contained in:
Romain Dolbeau
parent
b621ee2eb5
commit
93e7cd20c1
@ -57,8 +57,10 @@ class NuBus(Module):
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grant = Signal()
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tmoen = Signal()
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self.nubus_oe = nubus_oe = Signal() # improveme
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# those are needed in both Nubus and cpld integrated part now
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broadcast_id_3v3_n = plaform.request("id_3v3_n")
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broadcast_id_3v3_n = platform.request("id_3v3_n")
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# those are 'return' signals (O part of IO separated in I and O)
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# the 3v3 signals 'see' the 5V signals from the external drivers
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internal_start_3v3_n = Signal()
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@ -85,11 +87,11 @@ class NuBus(Module):
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i_nub_startn = platform.request("start_3v3_n"),
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i_nub_rqstn = platform.request("rqst_3v3_n"),
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i_nub_ackn = platform.request("ack_3v3_n"),
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o_nub_tm0n = internal_tm0_3v3_n,
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o_nub_tm1n = internal_tm1_3v3_n,
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o_nub_startn = internal_start_3v3_n,
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o_nub_rqstn = internal_rqst_3v3_n,
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o_nub_ackn = internal_ack_3v3_n,
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o_nub_tm0n_o = internal_tm0_3v3_n,
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o_nub_tm1n_o = internal_tm1_3v3_n,
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o_nub_startn_o = internal_start_3v3_n,
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o_nub_rqstn_o = internal_rqst_3v3_n,
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o_nub_ackn_o = internal_ack_3v3_n,
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# io_nub_arbn = platform.request("nubus_arb_n"),
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o_arbcy_n = arbcy_n, # internal now
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i_grant = grant, # internal now
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@ -124,10 +126,10 @@ class NuBus(Module):
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i_nub_clk2xn = ClockSignal(cd_nubus90),
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i_nub_tm2n = platform.request("tm2_3v3_n"),
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o_nub_tm2n = internal_tm2_3v3_n,
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o_nub_tm2n_o = internal_tm2_3v3_n,
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)
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self.specials += Instance("nubus_cpldinfpga",
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i_nubus_oe = nubus_oe, # FIXME: handled in soc
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i_nubus_oe = nubus_oe, # improveme: handled in soc
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i_tmoen = tmoen,
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i_nubus_master_dir = nubus_master_dir,
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i_rqst_oe_n = rqst_oe_n,
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@ -140,26 +142,26 @@ class NuBus(Module):
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o_grant = grant,
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i_tm0_n_3v3 = internal_tm0_3v3_n, # tm0 driving controlled by tmoen
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o_tm0_o_n = platform.request("tm_o_n"),
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o_tm0_o_n = platform.request("tm0_o_n"),
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i_tm1_n_3v3 = internal_tm1_3v3_n, # tm1 driving controlled by tmoen
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o_tm1_o_n = platform_request("tm1_o_n"),
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o_tmx_oe_n = platform_request("tmx_oe_n"),
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o_tm1_o_n = platform.request("tm1_o_n"),
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o_tmx_oe_n = platform.request("tmx_oe_n"),
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i_tm2_n_3v3 = internal_tm2_3v3_n, # tm2 currently never driven
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o_tm2_o_n = platform_request("tm2_o_n"),
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o_tm2_oe_n = platform_request("tm2_oe_n"),
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o_tm2_o_n = platform.request("tm2_o_n"),
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o_tm2_oe_n = platform.request("tm2_oe_n"),
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i_start_n_3v3 = internal_start_3v3_n, # start driving enabled by nubus_master_dir
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o_start_o_n = platform_request("start_o_n"),
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o_start_oe_n = platform_request("start_oe_n"),
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o_start_o_n = platform.request("start_o_n"),
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o_start_oe_n = platform.request("start_oe_n"),
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i_ack_n_3v3 = internal_ack_3v3_n, # ack driving controlled by tmoen
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o_ack_o_n = platform_request("ack_o_n"),
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o_ack_oe_n = platform_request("ack_oe_n"),
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o_ack_o_n = platform.request("ack_o_n"),
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o_ack_oe_n = platform.request("ack_oe_n"),
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i_rqst_n_3v3 = internal_rqst_3v3_n, # rqst driving ocntroller by rqst_oe_n
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o_rqst_o_n = platform_request("rqst_o_n")
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o_rqst_o_n = platform.request("rqst_o_n")
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)
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@ -43,7 +43,6 @@ module nubus_cpldinfpga
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);
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// placeholders
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assign tm2_n_3v3 = tm2_n_5v;
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assign tm2_o_n = 0;
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assign tm2_oe_n = 1;
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@ -247,7 +247,7 @@ class NuBusFPGA(SoCCore):
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#self.submodules.wa2d = WA2D(self.platform)
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#self.bus.add_slave("WA2D", self.wa2d.bus, SoCRegion(origin=0x00C00000, size=0x00400000, cached=False))
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notsimul = 1
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notsimul = 0
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if (notsimul):
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avail_sdram = 0
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self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
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@ -303,13 +303,14 @@ class NuBusFPGA(SoCCore):
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# Interface NuBus to wishbone
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# we need to cross clock domains
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xibus=0
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xibus=1
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if (xibus):
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wishbone_master_sys = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.wishbone_master_nubus = WishboneDomainCrossingMaster(platform=self.platform, slave=wishbone_master_sys, cd_master="nubus", cd_slave="sys")
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self.bus.add_master(name="NuBusBridgeToWishbone", master=wishbone_master_sys)
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self.submodules.nubus = nubus.NuBus(platform=platform, cd_nubus="nubus")
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#self.submodules.nubus2wishbone = ClockDomainsRenamer("nubus")(NuBus2Wishbone(nubus=self.nubus,wb=self.wishbone_master_nubus))
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self.comb += self.nubus.nubus_oe.eq(hold_reset) # improveme
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nubus_writemaster_sys = wishbone.Interface(data_width=self.bus.data_width)
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self.submodules.nubus2wishbone = NuBus2WishboneFIFO(platform=self.platform,nubus=self.nubus,wb_read=self.wishbone_master_nubus,wb_write=nubus_writemaster_sys)
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self.bus.add_master(name="NuBusBridgeToWishboneWrite", master=nubus_writemaster_sys)
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@ -321,10 +322,10 @@ class NuBusFPGA(SoCCore):
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irq_line = self.platform.request("nmrq_3v3_n") # active low
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fb_irq = Signal() # active low
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led0 = platform.request("user_led", 0)
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self.comb += [
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led0.eq(~fb_irq),
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]
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#led0 = platform.request("user_led", 0)
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#self.comb += [
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# led0.eq(~fb_irq),
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#]
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self.comb += irq_line.eq(fb_irq) # active low, enable if one is low
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else:
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sampling = 1
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@ -134,19 +134,15 @@ module nubus_slave_tb ();
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.A({reset_n_3v3, tm2_n_3v3, tm0_n_3v3, tm1_n_3v3}),
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.B({nub_resetn, nub_tm2n, nub_tm0n, nub_tm1n }));
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assign clk2x_n_3v3 = nub_clk2n;
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assign clk2x_n_3v3 = nub_clk2xn;
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ztex213_nubus_V1_2 UNuBus (
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// NuBus lines only
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.clk48(bd_clk48),
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.clk_3v3_n(clk_n_3v3),
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.reset_3v3_n(reset_n_3v3),
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.nubus_clk2x_n(clk2x_n_3v3),
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.user_led0(leds[0]),
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.user_led1(leds[1]),
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.user_led2(leds[2]),
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.user_led3(leds[3]),
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.nubus_tm2_n(tm2_n_3v3),
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.id_3v3_n(id_n_3v3),
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.ad_3v3_n(ad_n_3v3),
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.tm0_3v3_n(tm0_n_3v3),
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@ -160,10 +156,10 @@ module nubus_slave_tb ();
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.rqst_3v3_n(rqst_n_3v3),
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.rqst_o_n(rqst_o_n),
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.nmrq_3v3_n(nmrq_n_3v3), // output only, direct to driver
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.ack_3v3_n(ack_n_3v3),
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.ack_3v3_n(ack_3v3_n),
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.ack_o_n(ack_o_n),
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.ack_oe_n(ack_oe_n),
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.arb_n_3v3(arb_n_3v3),
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.arb_3v3_n(arb_3v3_n),
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.arb_o_n(arb_o_n),
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.nubus_ad_dir(nubus_ad_dir),
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.nubus_oe(nubus_oe),
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@ -202,7 +202,7 @@ _nubus_nubus_v1_2 = [
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("tm2_oe_n", 0, Pins("R6"), IOStandard("lvttl")),
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("nubus_oe", 0, Pins("G13"), IOStandard("lvttl")),
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("nubus_ad_dir", 0, Pins("G17"), IOStandard("lvttl"))),
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("nubus_ad_dir", 0, Pins("G17"), IOStandard("lvttl")),
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]
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# Connectors ---------------------------------------------------------------------------------------
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@ -214,10 +214,10 @@ connectors_v1_2 = [
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# Ethernet ----------------------------------------------------------------------------------------------
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# custom not-quite-pmod
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def rmii_eth_pmod_io(extpmod):
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def rmii_eth_extpmod_io(extpmod):
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return [
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("eth_clocks", 0,
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Subsignal("ref_clk", Pins(f"{extpmod}:10"))),
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Subsignal("ref_clk", Pins(f"{extpmod}:10")),
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IOStandard("LVCMOS33"),
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),
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("eth", 0,
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@ -225,12 +225,12 @@ def rmii_eth_pmod_io(extpmod):
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Subsignal("rx_data", Pins(f"{extpmod}:8 {extpmod}:11")),
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Subsignal("crs_dv", Pins(f"{extpmod}:6")),
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Subsignal("tx_en", Pins(f"{extpmod}:2")),
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Subsignal("tx_data", Pins(f"{extpmod}:0 {extpmod}:1"))),
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Subsignal("tx_data", Pins(f"{extpmod}:0 {extpmod}:1")),
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Subsignal("mdc", Pins(f"{extpmod}:4")),
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Subsignal("mdio", Pins(f"{extpmod}:7")),
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Subsignal("rx_er", Pins(f"{extpmod}:9"))),
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Subsignal("int_n", Pins(f"{extpmod}:5"))),
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IOStandard("LVCMOS33")
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Subsignal("rx_er", Pins(f"{extpmod}:9")),
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Subsignal("int_n", Pins(f"{extpmod}:5")),
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IOStandard("LVCMOS33"),
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),
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]
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_rmii_eth_extpmod_io_v1_2 = rmii_eth_extpmod_io("P1")
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@ -257,6 +257,10 @@ class Platform(XilinxPlatform):
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"V1.0" : _nubus_nubus_v1_0,
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"V1.2" : _nubus_nubus_v1_2,
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}[version]
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connectors = {
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"V1.0" : connectors_v1_0,
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"V1.2" : connectors_v1_2,
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}[version]
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self.speedgrade = -1
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if (device[-1] == '2'):
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self.speedgrade = -2
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