commit patch for newer Litex

nubus-to-ztex-gateware/DepVideoEqu.a

@@ -1 +0,0 @@
-NuBusFPGAID EQU $BEEF

defMinorBase EQU 0 ; beginning
defMinorLength EQU $C0000 ; 768 KiB

Pages8s EQU 1 ; no idea

defmBounds_Ts EQU 0
defmBounds_Ls EQU 0
defmBounds_Bs EQU 480
defmBounds_Rs EQU 640

DrHwNuBusFPGA EQU $BEEF ; placeholder

defmBaseOffset EQU 0 ; beginning, placeholder

devVersion EQU 0 ; placeholder

defmHRes EQU $480000 ;Horizontal Pixels/inch
defmVRes EQU $480000 ;Vertical pixels/inch

defmDevType EQU 0 ;0 = CLUTType

defmPlaneBytes	EQU 0 ;Offset from one plane to the next.

SGammaResID EQU 0

RB8s EQU 640


ChunkyIndexed EQU 0

defVersion		EQU		0			;Version = 0

ROMSize			EQU		$1000					;4K byte ROM

nubus-to-ztex-gateware/NuBusFPGAPrimaryInit.a

@@ -1 +0,0 @@
-             DC.B sExec2         ; code revision
             DC.B sCPU68020      ; CPU type is 68020
             DC.W 0               ; reserved
             DC.L Begin1stInit-*  ; offset to code

             WITH seBlock,spBlock

Begin1stInit
	MOVE.W	     #1,seStatus(A0) ; assume a good return

	MOVE.L       #$F0000000,D1 ; Dl <- F0000000
	MOVE.B       seSlot(A0),D0 ; get slot number
	BFINS        D0,D1{4:4}    ; Dl <- Fs000000
	MOVE.L       D1,A1         ; copy to address reg

;;; INITIALIZE SOME STUFF HERE

	SUBA          #spBlockSize,SP   ; make an spB10ck
	MOVE.L        SP,A0             ; get pointer to parms
	MOVE.B        D0,spSlot(A0)     ; identify the slot
	CLR.B         SpExtDev(A0)      ; external device = 0


RTS

ENDWITH

nubus-to-ztex-gateware/VintageBusFPGA_Common

@@ -1 +1 @@
-Subproject commit c7d117677ecd10b4990ccf42187265c53a46c1e2
+Subproject commit 342358535e10c4efc1660a442aba68c79ae7d166

nubus-to-ztex-gateware/nubus_to_fpga_export.py

@@ -88,8 +88,10 @@ def get_csr_header_split(regions, constants, csr_base=None, with_access_function
         if not isinstance(region.obj, Memory):
             for csr in region.obj:
                 nr = (csr.size + region.busword - 1)//region.busword
-                r += _get_rw_functions_c(csr.name, origin, nr, region.busword, alignment,
-                    getattr(csr, "read_only", False), with_access_functions)
+                r += _get_rw_functions_c(reg_name=csr.name, reg_base=origin, nwords=nr, busword=region.busword, alignment=alignment,
+                                         read_only=getattr(csr, "read_only", False),
+                                         csr_base=0, with_csr_base_define=False,
+                                         with_access_functions=with_access_functions)
                 origin += alignment//8*nr
                 if hasattr(csr, "fields"):
                     for field in csr.fields.fields:

nubus-to-ztex-gateware/nubus_to_fpga_soc.py

@@ -181,6 +181,7 @@ class NuBusFPGA(SoCCore):
                          sys_clk_freq=sys_clk_freq,
                          clk_freq=sys_clk_freq,
                          csr_paging=0x800, #  default is 0x800
+                         bus_interconnect = "crossbar",
                          **kwargs)
 
         # Quoting the doc:

nubus-to-ztex-gateware/sdram_init.py

@@ -28,7 +28,7 @@ sdram_dfii_pi0_baddress =      sdram_dfii_base + 0x010
 # /!\ keep up to date with csr /!\
 ddrphy_base = 0xf0a00000
 ddrphy_rst                 = ddrphy_base + 0x000
-ddrphy_dly_sel             = ddrphy_base + 0x010
+ddrphy_dly_sel             = ddrphy_base + 0x004
 ddrphy_rdly_dq_rst         = ddrphy_base + 0x014
 ddrphy_rdly_dq_inc         = ddrphy_base + 0x018
 ddrphy_rdly_dq_bitslip_rst = ddrphy_base + 0x01c