better qemu support, exp. add of Eth
This commit is contained in:
Romain Dolbeau
parent
cb5d09df4d
commit
c6e33c5caf
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@ -10,7 +10,7 @@ This project was 'spun off' the [SBusFPGA](https://github.com/rdolbeau/SBusFPGA)
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## Current status
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First prototype is working in a Quadra 650, running MacOS 8.1. It implements a single-screen-resolution, windowboxed multi-resolution, depth-switchable (1/2/4/8/16/32 bits) framebuffer over DVI-in-HDMI-connector (will work with any HDMI-compliant monitor). The framebuffer can be used as secondary/primary/only framebuffer in the machine running OS8.1. Qemu tests indicate this should work with 7.1 & 7.5/7.6 as well. An alternate HDMI PHY also supports audio, enabled as a 8/16 bits, mono/stereo, 44.1 Hz output compoenent in MacOS.
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First prototype is working in a Quadra 650, running MacOS 8.1. It implements a single-screen-resolution, windowboxed multi-resolution, depth-switchable (1/2/4/8/16/32 bits) framebuffer over DVI-in-HDMI-connector (will work with any HDMI-compliant monitor). The framebuffer can be used as secondary/primary/only framebuffer in the machine running OS8.1. Qemu tests indicate this should work with 7.1 & 7.5/7.6 as well. An alternate HDMI PHY also supports audio, enabled as a 8/16 bits, mono/stereo, 44.1 kHz output component in MacOS.
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Some basic acceleration now exists for 8/16/32 bits, doing rectangle screen-to-screen blits and pattern rectangle fills. 1/2/4 bits also has some acceleration, but only for byte-aligned cases.
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@ -17,6 +17,10 @@ APPLEINCS=${NS816DECLROMDIR}/atrap.inc ${NS816DECLROMDIR}/declrom.inc ${NS816DEC
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HRES=1920
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VRES=1080
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QEMU=no
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ifeq ($(QEMU),yes)
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CFLAGS+=-DQEMU
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endif
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CSRC_VIDEO=NuBusFPGADrvr_OpenClose.c NuBusFPGADrvr_Ctrl.c NuBusFPGADrvr_Status.c NuBusFPGAPrimaryInit_Primary.c NuBusFPGAPrimaryInit_RamInit.c NuBusFPGASecondaryInit_Secondary.c
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CSRC_RAMDSK=NuBusFPGARAMDskDrvr_OpenClose.c NuBusFPGARAMDskDrvr_Ctrl.c NuBusFPGARAMDskDrvr_Prime.c NuBusFPGARAMDskDrvr_Status.c myrle.c
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@ -34,8 +34,10 @@ UInt32 Primary(SEBlock* seblock) {
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vres = __builtin_bswap32((UInt32)PRIM_READREG(GOBOFB_VRES)); // fixme: endianness
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/* initialize DRAM controller */
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#ifndef QEMU
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sdram_init(a32);
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#endif
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/* grey the screen */
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/* should switch to HW ? */
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a32_l0 = a32;
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@ -1 +1 @@
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Subproject commit f93c95ba1eda007ffce0cf5f9c5a3421afbcfdc6
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Subproject commit 9e350c5962f1dc8f43091a3f44a7c1f8071d2bff
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@ -2,7 +2,7 @@
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source /opt/Xilinx/Vivado/2020.1/settings64.sh
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export LD_LIBRARY_PATH=/opt/Xilinx/Vivado/2020.1/lib/lnx64.o/SuSE
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi
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python3 nubus_to_fpga_soc.py --build --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6 --goblin --goblin-res 1920x1080@60Hz --hdmi --ethernet
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#python3 nubus_to_fpga_soc.py --csr-csv csr.csv --csr-json csr.json --variant=ztex2.13a --version=V1.2 --sys-clk-freq 100e6
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@ -24,6 +24,8 @@ from litedram.phy import s7ddrphy
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from litedram.frontend.dma import *
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from liteeth.phy.rmii import LiteEthPHYRMII
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from migen.genlib.cdc import BusSynchronizer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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@ -45,7 +47,8 @@ class _CRG(Module):
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def __init__(self, platform, version, sys_clk_freq,
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goblin=False,
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hdmi=False,
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pix_clk=0):
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pix_clk=0,
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ethernet=False):
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self.clock_domains.cd_sys = ClockDomain() # 100 MHz PLL, reset'ed by NuBus (via pll), SoC/Wishbone main clock
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
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@ -59,7 +62,9 @@ class _CRG(Module):
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else:
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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if (ethernet):
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self.clock_domains.cd_eth = ClockDomain()
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# # #
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clk48 = platform.request("clk48")
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@ -118,6 +123,11 @@ class _CRG(Module):
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pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
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platform.add_platform_command("create_generated_clock -name sys4x90clk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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if (ethernet):
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pll.create_clkout(self.cd_eth, 50e6, phase=90) # fixme: what if sys_clk_feq != 100e6?
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platform.add_platform_command("create_generated_clock -name ethclk [get_pins {{{{MMCME2_ADV/CLKOUT{}}}}}]".format(num_clk))
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num_clk = num_clk + 1
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self.comb += pll.reset.eq(~rst_nubus_n) # | ~por_done
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platform.add_false_path_constraints(clk48, self.cd_nubus.clk) # FIXME?
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platform.add_false_path_constraints(self.cd_nubus.clk, clk48) # FIXME?
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@ -171,7 +181,7 @@ class _CRG(Module):
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class NuBusFPGA(SoCCore):
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def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, **kwargs):
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def __init__(self, variant, version, sys_clk_freq, goblin, hdmi, goblin_res, ethernet, **kwargs):
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print(f"Building NuBusFPGA for board version {version}")
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kwargs["cpu_type"] = "None"
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@ -183,6 +193,9 @@ class NuBusFPGA(SoCCore):
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self.platform = platform = ztex213_nubus.Platform(variant = variant, version = version)
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if (ethernet and (version == "V1.2")):
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platform.add_extension(ztex213_nubus._rmii_eth_extpmod_io_v1_2)
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use_goblin_alt = True
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if ((not use_goblin_alt) or (not hdmi)):
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from VintageBusFPGA_Common.goblin_fb import goblin_rounded_size, Goblin
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@ -238,11 +251,12 @@ class NuBusFPGA(SoCCore):
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"goblin_audio_ram" : 0xF0920000, # audio for goblin (RAM buffers)
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"csr" : 0xF0A00000, # CSR
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"pingmaster": 0xF0B00000,
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"ethmac": 0xF0C00000,
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"rom": 0xF0FF8000, # ROM at the end (32 KiB of it ATM)
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#"END OF SLOT SPACE": 0xF0FFFFFF,
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}
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self.mem_map.update(wb_mem_map)
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self.submodules.crg = _CRG(platform=platform, version=version, sys_clk_freq=sys_clk_freq, goblin=goblin, hdmi=hdmi, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"])
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self.submodules.crg = _CRG(platform=platform, version=version, sys_clk_freq=sys_clk_freq, goblin=goblin, hdmi=hdmi, pix_clk=litex.soc.cores.video.video_timings[goblin_res]["pix_clk"], ethernet=ethernet)
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## add our custom timings after the clocks have been defined
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xdc_timings_filename = None;
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@ -476,25 +490,42 @@ class NuBusFPGA(SoCCore):
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self.add_ram("goblin_accel_rom", origin=self.mem_map["goblin_accel_rom"], size=rounded_goblin_rom_len, contents=goblin_rom_data, mode="r")
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self.add_ram("goblin_accel_ram", origin=self.mem_map["goblin_accel_ram"], size=2**12, mode="rw")
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if (ethernet):
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# we need the CRG to provide the cd_eth clock: "use refclk_cd as RMII reference clock (provided by user design) (no external clock).
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self.ethphy = LiteEthPHYRMII(
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clock_pads = self.platform.request("eth_clocks"),
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pads = self.platform.request("eth"))
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self.add_ethernet(phy=self.ethphy, data_width = 32)
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print(f"%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% {self.ethmac.interface.sram.ev.irq}") # FIXME HANDLEME
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# for testing
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if (True):
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if (False):
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from nubus_master_tst import PingMaster
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self.submodules.pingmaster = PingMaster(nubus=self.nubus, platform=self.platform)
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self.bus.add_slave("pingmaster_slv", self.pingmaster.bus_slv, SoCRegion(origin=self.mem_map.get("pingmaster", None), size=0x010, cached=False))
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self.bus.add_master(name="pingmaster_mst", master=self.pingmaster.bus_mst)
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def main():
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parser = argparse.ArgumentParser(description="SbusFPGA")
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parser = argparse.ArgumentParser(description="NuBusFPGA")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--variant", default="ztex2.13a", help="ZTex board variant (default ztex2.13a)")
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parser.add_argument("--version", default="V1.0", help="NuBusFPGA board version (default V1.0)")
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parser.add_argument("--sys-clk-freq", default=100e6, help="NuBusFPGA system clock (default 100e6 = 100 MHz)")
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parser.add_argument("--goblin", action="store_true", help="add a goblin framebuffer")
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parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA)")
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parser.add_argument("--hdmi", action="store_true", help="The framebuffer uses HDMI (default to VGA, required for V1.2)")
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parser.add_argument("--goblin-res", default="640x480@60Hz", help="Specify the goblin resolution")
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parser.add_argument("--ethernet", action="store_true", help="Add Ethernet (V1.2 w/ custom PMod only)")
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builder_args(parser)
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vivado_build_args(parser)
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args = parser.parse_args()
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if (args.ethernet and (args.version == "V1.0")):
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print(" ***** ERROR ***** : Ethernet not supported on V1.0\n");
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assert(False)
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if ((not args.hdmi) and (args.version == "V1.2")):
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print(" ***** ERROR ***** : VGA not supported on V1.2\n");
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assert(False)
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soc = NuBusFPGA(**soc_core_argdict(args),
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variant=args.variant,
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@ -502,7 +533,8 @@ def main():
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sys_clk_freq=int(float(args.sys_clk_freq)),
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goblin=args.goblin,
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hdmi=args.hdmi,
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goblin_res=args.goblin_res)
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goblin_res=args.goblin_res,
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ethernet=args.ethernet)
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version_for_filename = args.version.replace(".", "_")
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