mirror of
https://github.com/rdolbeau/NuBusFPGA.git
synced 2024-06-16 22:29:27 +00:00
update everything
This commit is contained in:
parent
3c222a74e9
commit
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|||
EESchema Schematic File Version 4
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||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
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||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
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||||
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@ -332,8 +331,6 @@ Wire Wire Line
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|||
10200 1050 10200 1350
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||||
Wire Wire Line
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||||
10200 1350 9900 1350
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||||
Wire Wire Line
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||||
9450 1050 10200 1050
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||||
Text GLabel 4100 2050 2 50 Input Italic 0
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||||
~CLK_3V3
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||||
Text GLabel 4100 1350 2 50 Input ~ 0
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||||
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@ -551,9 +548,9 @@ F 3 "" H 700 6600 50 0001 C CNN
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|||
$EndComp
|
||||
Text GLabel 1850 6400 2 60 Input ~ 12
|
||||
LED1
|
||||
Text GLabel 9450 1050 2 60 Input ~ 12
|
||||
Text GLabel 9650 1050 2 60 Input ~ 12
|
||||
LED0
|
||||
Text GLabel 9450 950 2 60 Input ~ 12
|
||||
Text GLabel 9650 950 2 60 Input ~ 12
|
||||
LED1
|
||||
Text GLabel 1600 4050 0 50 Input ~ 0
|
||||
USBH0_D+
|
||||
|
@ -862,4 +859,9 @@ F 3 "" H 3400 5900 50 0001 C CNN
|
|||
1 3400 5900
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||||
1 0 0 -1
|
||||
$EndComp
|
||||
Wire Wire Line
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||||
9450 950 9650 950
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||||
Connection ~ 9450 950
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Wire Wire Line
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||||
9450 1050 10200 1050
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||||
$EndSCHEMATC
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||||
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@ -1,6 +1,5 @@
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|||
EESchema Schematic File Version 4
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||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
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@ -1,6 +1,5 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
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@ -1,6 +1,6 @@
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|||
%!PS-Adobe-3.0
|
||||
%%Creator: PCBNEW
|
||||
%%CreationDate: Sat Oct 1 08:36:44 2022
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||||
%%CreationDate: Tue Nov 1 08:32:03 2022
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||||
%%Title: /home/dolbeau/MAC/NuBusFPGA.V1_2/nubus-to-ztex/nubus-to-ztex-NPTH-drl_map.ps
|
||||
%%Pages: 1
|
||||
%%PageOrder: Ascend
|
||||
|
|
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@ -1,8 +1,11 @@
|
|||
M48
|
||||
;DRILL file {KiCad 5.0.2+dfsg1-1~bpo9+1} date Sat Oct 1 08:36:43 2022
|
||||
; DRILL file {KiCad 5.1.9+dfsg1-1~bpo10+1} date Tue Nov 1 08:32:02 2022
|
||||
; FORMAT={-:-/ absolute / inch / decimal}
|
||||
; #@! TF.CreationDate,2022-11-01T08:32:02+01:00
|
||||
; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.9+dfsg1-1~bpo10+1
|
||||
; #@! TF.FileFunction,NonPlated,1,4,NPTH
|
||||
FMAT,2
|
||||
INCH,TZ
|
||||
INCH
|
||||
T1C0.1122
|
||||
%
|
||||
G90
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,8 +1,11 @@
|
|||
M48
|
||||
;DRILL file {KiCad 5.0.2+dfsg1-1~bpo9+1} date Sat Oct 1 08:36:43 2022
|
||||
; DRILL file {KiCad 5.1.9+dfsg1-1~bpo10+1} date Tue Nov 1 08:32:02 2022
|
||||
; FORMAT={-:-/ absolute / inch / decimal}
|
||||
; #@! TF.CreationDate,2022-11-01T08:32:02+01:00
|
||||
; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.9+dfsg1-1~bpo10+1
|
||||
; #@! TF.FileFunction,Plated,1,4,PTH
|
||||
FMAT,2
|
||||
INCH,TZ
|
||||
INCH
|
||||
T1C0.0157
|
||||
T2C0.0236
|
||||
T3C0.0315
|
||||
|
@ -284,130 +287,130 @@ X4.7992Y-1.3189
|
|||
T8
|
||||
X5.1181Y-1.0811
|
||||
X5.1181Y-1.1811
|
||||
X5.2181Y-1.0811
|
||||
X5.2181Y-1.1811
|
||||
X5.3181Y-1.0811
|
||||
X5.3181Y-1.1811
|
||||
X5.4181Y-1.0811
|
||||
X5.4181Y-1.1811
|
||||
X5.5181Y-1.0811
|
||||
X5.5181Y-1.1811
|
||||
X5.6181Y-1.0811
|
||||
X5.6181Y-1.1811
|
||||
X5.7181Y-1.0811
|
||||
X5.7181Y-1.1811
|
||||
X5.8181Y-1.0811
|
||||
X5.8181Y-1.1811
|
||||
X5.9181Y-1.0811
|
||||
X5.9181Y-1.1811
|
||||
X6.0181Y-1.0811
|
||||
X6.0181Y-1.1811
|
||||
X6.1181Y-1.0811
|
||||
X6.1181Y-1.1811
|
||||
X6.2181Y-1.0811
|
||||
X6.2181Y-1.1811
|
||||
X6.3181Y-1.0811
|
||||
X6.3181Y-1.1811
|
||||
X6.4181Y-1.0811
|
||||
X6.4181Y-1.1811
|
||||
X6.5181Y-1.0811
|
||||
X6.5181Y-1.1811
|
||||
X6.6181Y-1.0811
|
||||
X6.6181Y-1.1811
|
||||
X6.7181Y-1.0811
|
||||
X6.7181Y-1.1811
|
||||
X6.8181Y-1.0811
|
||||
X6.8181Y-1.1811
|
||||
X6.9181Y-1.0811
|
||||
X6.9181Y-1.1811
|
||||
X7.0181Y-1.0811
|
||||
X7.0181Y-1.1811
|
||||
X7.1181Y-1.0811
|
||||
X7.1181Y-1.1811
|
||||
X7.2181Y-1.0811
|
||||
X7.2181Y-1.1811
|
||||
X7.3181Y-1.0811
|
||||
X7.3181Y-1.1811
|
||||
X7.4181Y-1.0811
|
||||
X7.4181Y-1.1811
|
||||
X7.5181Y-1.0811
|
||||
X7.5181Y-1.1811
|
||||
X7.6181Y-1.0811
|
||||
X7.6181Y-1.1811
|
||||
X7.7181Y-1.0811
|
||||
X7.7181Y-1.1811
|
||||
X7.8181Y-1.0811
|
||||
X7.8181Y-1.1811
|
||||
X7.9181Y-1.0811
|
||||
X7.9181Y-1.1811
|
||||
X8.0181Y-1.0811
|
||||
X8.0181Y-1.1811
|
||||
X8.1181Y-1.0811
|
||||
X8.1181Y-1.1811
|
||||
X8.2181Y-1.0811
|
||||
X8.2181Y-1.1811
|
||||
X5.1181Y-2.3311
|
||||
X5.1181Y-2.4311
|
||||
X5.2181Y-1.0811
|
||||
X5.2181Y-1.1811
|
||||
X5.2181Y-2.3311
|
||||
X5.2181Y-2.4311
|
||||
X5.3181Y-1.0811
|
||||
X5.3181Y-1.1811
|
||||
X5.3181Y-2.3311
|
||||
X5.3181Y-2.4311
|
||||
X5.4181Y-1.0811
|
||||
X5.4181Y-1.1811
|
||||
X5.4181Y-2.3311
|
||||
X5.4181Y-2.4311
|
||||
X5.5181Y-1.0811
|
||||
X5.5181Y-1.1811
|
||||
X5.5181Y-2.3311
|
||||
X5.5181Y-2.4311
|
||||
X5.6181Y-1.0811
|
||||
X5.6181Y-1.1811
|
||||
X5.6181Y-2.3311
|
||||
X5.6181Y-2.4311
|
||||
X5.7181Y-1.0811
|
||||
X5.7181Y-1.1811
|
||||
X5.7181Y-2.3311
|
||||
X5.7181Y-2.4311
|
||||
X5.8181Y-1.0811
|
||||
X5.8181Y-1.1811
|
||||
X5.8181Y-2.3311
|
||||
X5.8181Y-2.4311
|
||||
X5.9181Y-1.0811
|
||||
X5.9181Y-1.1811
|
||||
X5.9181Y-2.3311
|
||||
X5.9181Y-2.4311
|
||||
X6.0181Y-1.0811
|
||||
X6.0181Y-1.1811
|
||||
X6.0181Y-2.3311
|
||||
X6.0181Y-2.4311
|
||||
X6.1181Y-1.0811
|
||||
X6.1181Y-1.1811
|
||||
X6.1181Y-2.3311
|
||||
X6.1181Y-2.4311
|
||||
X6.2181Y-1.0811
|
||||
X6.2181Y-1.1811
|
||||
X6.2181Y-2.3311
|
||||
X6.2181Y-2.4311
|
||||
X6.3181Y-1.0811
|
||||
X6.3181Y-1.1811
|
||||
X6.3181Y-2.3311
|
||||
X6.3181Y-2.4311
|
||||
X6.4181Y-1.0811
|
||||
X6.4181Y-1.1811
|
||||
X6.4181Y-2.3311
|
||||
X6.4181Y-2.4311
|
||||
X6.5181Y-1.0811
|
||||
X6.5181Y-1.1811
|
||||
X6.5181Y-2.3311
|
||||
X6.5181Y-2.4311
|
||||
X6.6181Y-1.0811
|
||||
X6.6181Y-1.1811
|
||||
X6.6181Y-2.3311
|
||||
X6.6181Y-2.4311
|
||||
X6.7181Y-1.0811
|
||||
X6.7181Y-1.1811
|
||||
X6.7181Y-2.3311
|
||||
X6.7181Y-2.4311
|
||||
X6.8181Y-1.0811
|
||||
X6.8181Y-1.1811
|
||||
X6.8181Y-2.3311
|
||||
X6.8181Y-2.4311
|
||||
X6.9181Y-1.0811
|
||||
X6.9181Y-1.1811
|
||||
X6.9181Y-2.3311
|
||||
X6.9181Y-2.4311
|
||||
X7.0181Y-1.0811
|
||||
X7.0181Y-1.1811
|
||||
X7.0181Y-2.3311
|
||||
X7.0181Y-2.4311
|
||||
X7.1181Y-1.0811
|
||||
X7.1181Y-1.1811
|
||||
X7.1181Y-2.3311
|
||||
X7.1181Y-2.4311
|
||||
X7.2181Y-1.0811
|
||||
X7.2181Y-1.1811
|
||||
X7.2181Y-2.3311
|
||||
X7.2181Y-2.4311
|
||||
X7.3181Y-1.0811
|
||||
X7.3181Y-1.1811
|
||||
X7.3181Y-2.3311
|
||||
X7.3181Y-2.4311
|
||||
X7.4181Y-1.0811
|
||||
X7.4181Y-1.1811
|
||||
X7.4181Y-2.3311
|
||||
X7.4181Y-2.4311
|
||||
X7.5181Y-1.0811
|
||||
X7.5181Y-1.1811
|
||||
X7.5181Y-2.3311
|
||||
X7.5181Y-2.4311
|
||||
X7.6181Y-1.0811
|
||||
X7.6181Y-1.1811
|
||||
X7.6181Y-2.3311
|
||||
X7.6181Y-2.4311
|
||||
X7.7181Y-1.0811
|
||||
X7.7181Y-1.1811
|
||||
X7.7181Y-2.3311
|
||||
X7.7181Y-2.4311
|
||||
X7.8181Y-1.0811
|
||||
X7.8181Y-1.1811
|
||||
X7.8181Y-2.3311
|
||||
X7.8181Y-2.4311
|
||||
X7.9181Y-1.0811
|
||||
X7.9181Y-1.1811
|
||||
X7.9181Y-2.3311
|
||||
X7.9181Y-2.4311
|
||||
X8.0181Y-1.0811
|
||||
X8.0181Y-1.1811
|
||||
X8.0181Y-2.3311
|
||||
X8.0181Y-2.4311
|
||||
X8.1181Y-1.0811
|
||||
X8.1181Y-1.1811
|
||||
X8.1181Y-2.3311
|
||||
X8.1181Y-2.4311
|
||||
X8.2181Y-1.0811
|
||||
X8.2181Y-1.1811
|
||||
X8.2181Y-2.3311
|
||||
X8.2181Y-2.4311
|
||||
T9
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||||
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@ -439,9 +442,15 @@ X10.7008Y-2.7618
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|||
T12
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||||
X10.1319Y-1.8539
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T2
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X10.6908Y-2.9752G85X10.7184Y-2.9752
|
||||
G00X10.6908Y-2.9752
|
||||
M15
|
||||
G01X10.7184Y-2.9752
|
||||
M16
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||||
G05
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X10.7184Y-3.2508G85X10.6908Y-3.2508
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||||
G00X10.7184Y-3.2508
|
||||
M15
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||||
G01X10.6908Y-3.2508
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||||
M16
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||||
G05
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T0
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M30
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### Module positions - created on Sat Oct 1 08:36:39 2022 ###
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### Printed by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
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### Module positions - created on Tue Nov 1 08:32:29 2022 ###
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### Printed by Pcbnew version kicad 5.1.9+dfsg1-1~bpo10+1
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## Unit = mm, Angle = deg.
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## Side : bottom
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# Ref Val Package PosX PosY Rot Side
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F3 "" 0 0 50 H I C CNN
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ALIAS 74LVC125
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$FPLIST
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DIP?14*
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DIP*W7.62mm*
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$ENDFPLIST
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DRAW
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S -200 300 200 -300 5 1 10 f
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P 5 0 1 0 -170 220 -70 220 -80 190 -160 190 -170 220 F
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||||
P 9 0 1 0 -185 230 -185 220 -175 190 -175 180 -65 180 -65 190 -55 220 -55 230 -185 230 N
|
||||
X VBUS 1 300 200 100 L 50 50 1 1 w
|
||||
X D- 2 300 -100 100 L 50 50 1 1 P
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||||
X D+ 3 300 0 100 L 50 50 1 1 P
|
||||
X D- 2 300 -100 100 L 50 50 1 1 B
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||||
X D+ 3 300 0 100 L 50 50 1 1 B
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||||
X ID 4 300 -200 100 L 50 50 1 1 P
|
||||
X GND 5 0 -400 100 U 50 50 1 1 w
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||||
X Shield 6 -100 -400 100 U 50 50 1 1 P
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||||
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|||
CP_*
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||||
$ENDFPLIST
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||||
DRAW
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||||
S -90 20 -90 40 0 1 0 N
|
||||
S -90 20 90 20 0 1 0 N
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||||
S -90 20 90 40 0 1 0 N
|
||||
S 90 -20 -90 -40 0 1 0 F
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||||
S 90 40 -90 40 0 1 0 N
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||||
S 90 40 90 20 0 1 0 N
|
||||
P 2 0 1 0 -70 90 -30 90 N
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||||
P 2 0 1 0 -50 110 -50 70 N
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||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
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|||
LED_THT:*
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||||
$ENDFPLIST
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||||
DRAW
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||||
P 2 0 1 8 -50 -50 -50 50 N
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P 2 0 1 10 -50 -50 -50 50 N
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P 2 0 1 0 -50 0 50 0 N
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P 4 0 1 8 50 -50 50 50 -50 0 50 -50 F
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P 4 0 1 10 50 -50 50 50 -50 0 50 -50 F
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||||
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
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||||
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
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||||
X K 1 -150 0 100 R 50 50 1 1 P
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Drill report for /home/dolbeau/MAC/NuBusFPGA.V1_2/nubus-to-ztex/nubus-to-ztex.kicad_pcb
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Created on Sat Oct 1 08:36:45 2022
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Created on Tue Nov 1 08:32:06 2022
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Copper Layer Stackup:
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=============================================================
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@ -1,5 +1,5 @@
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### Module positions - created on Sat Oct 1 08:36:39 2022 ###
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### Printed by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
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### Module positions - created on Tue Nov 1 08:32:29 2022 ###
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### Printed by Pcbnew version kicad 5.1.9+dfsg1-1~bpo10+1
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## Unit = mm, Angle = deg.
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## Side : top
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# Ref Val Package PosX PosY Rot Side
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P CODE 00
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P UNITS CUST 0
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P DIM N
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P arrayDim N
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317GND VIA MD0157PA00X+089094Y-012559X0315Y0000R000S3
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317GND VIA MD0157PA00X+054134Y-035162X0315Y0000R000S3
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||||
317GND VIA MD0157PA00X+100874Y-024360X0315Y0000R000S3
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|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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Load Diff
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update=22/05/2015 07:44:53
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update=Fri Oct 28 08:20:13 2022
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version=1
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last_client=kicad
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[general]
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version=1
|
||||
RootSch=
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BoardNm=
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||||
[pcbnew]
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version=1
|
||||
LastNetListRead=
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||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
|
||||
BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
|
@ -31,3 +12,248 @@ NetIExt=net
|
|||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[schematic_editor]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
PlotDirectoryName=
|
||||
SubpartIdSeparator=0
|
||||
SubpartFirstId=65
|
||||
NetFmtName=Pcbnew
|
||||
SpiceAjustPassiveValues=0
|
||||
LabSize=50
|
||||
ERC_TestSimilarLabels=1
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=nubus-to-ztex.net
|
||||
CopperLayerCount=4
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.1524
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.1524
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
dPairWidth1=0.1524
|
||||
dPairGap1=0.1524
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.15
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.15
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.15
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0.051
|
||||
SolderMaskMinWidth=0.25
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.1524
|
||||
TrackWidth=0.1524
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.1524
|
||||
dPairGap=0.1524
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=Shielding
|
||||
Clearance=0.2
|
||||
TrackWidth=0.1524
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.1524
|
||||
dPairGap=0.1524
|
||||
dPairViaGap=0.25
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
## Footprint report - date Sat Oct 1 08:36:50 2022
|
||||
## Created by Pcbnew version kicad 5.0.2+dfsg1-1~bpo9+1
|
||||
## Footprint report - date Tue Nov 1 08:32:34 2022
|
||||
## Created by Pcbnew version kicad 5.1.9+dfsg1-1~bpo10+1
|
||||
## Unit = mm, Angle = deg.
|
||||
|
||||
$BeginDESCRIPTION
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -1,6 +1,5 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A2 23386 16535
|
||||
encoding utf-8
|
||||
|
@ -2614,7 +2613,7 @@ How should unused input be connected ?
|
|||
Text Notes 15800 14800 1 50 ~ 0
|
||||
How should unused input be connected ?
|
||||
Text Notes 11800 12700 0 50 ~ 0
|
||||
SN74CB3T3245PW are cheaper and more available than the SN74CB3T3125PW ...
|
||||
SN74CB3T3245PW are cheaper and more available than the (smaller) SN74CB3T3125PW ...
|
||||
Connection ~ 12250 13800
|
||||
Connection ~ 12250 13900
|
||||
Wire Wire Line
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
|
@ -1,6 +1,5 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
Binary file not shown.
|
@ -1,6 +1,5 @@
|
|||
EESchema Schematic File Version 4
|
||||
LIBS:nubus-to-ztex-cache
|
||||
EELAYER 26 0
|
||||
EELAYER 30 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
encoding utf-8
|
||||
|
|
Loading…
Reference in New Issue
Block a user