13 Commits

Author	SHA1	Message	Date
Romain Dolbeau	b2ef57a8dc	move SDRAM init from HW to SW	2023-01-27 22:25:12 +01:00
Romain Dolbeau	13d0e6519c	get ns816-declrom as a submodule, add auto-buidling of nubus_checksum	2022-12-11 17:00:58 +01:00
Romain Dolbeau	fa39c042d1	cleanup	2022-10-06 23:54:24 +02:00
Romain Dolbeau	4468ffd68c	rework build system	2022-10-06 23:28:07 +02:00
Romain Dolbeau	17a9aebd78	pc-relative code from the compiler	2022-10-06 22:08:48 +02:00
Romain Dolbeau	7084f6e113	automate DeclRom more	2022-09-17 17:06:15 +02:00
Romain Dolbeau	173c87ea02	LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650	2022-06-24 23:37:18 +02:00
Romain Dolbeau	972f628e80	use some custom RLE to initiliaze the RAM disk with a valid HFS FS. Still doesn't mount at boot though.	2022-06-12 13:45:41 +02:00
Romain Dolbeau	2000161727	in _sampling, map whole SDRAm in superslot and use the first 248 Mib as a RAM disk with driver in the DeclRom	2022-06-07 23:05:08 +02:00
Romain Dolbeau	44fa491540	C secondary, add rsrc directory w/o assembly	2022-04-19 23:31:31 +02:00
Romain Dolbeau	62b2c48b32	update to first tested version	2022-04-17 11:25:48 +02:00
Romain Dolbeau	de1aaf8161	some missing stuff, minor HW update, SW	2022-02-05 15:32:44 +01:00
Romain Dolbeau	5f0bc43139	push to github	2021-12-21 08:26:30 +01:00