4 Commits

Author	SHA1	Message	Date
Romain Dolbeau	173c87ea02	LD/LDU/SD (64-bits, dual regs) support in Vex + accel ; ramdisk tested in Q650	2022-06-24 23:37:18 +02:00
Romain Dolbeau	85c62fb331	new interface	2022-06-04 17:25:58 +02:00
Romain Dolbeau	76c29d5b69	accel in 16/32 ; includes adding MUL to Vex & fixing a FIFO overrun in NuBus in 32 bits mode	2022-06-04 14:55:40 +02:00
Romain Dolbeau	d53a70ba9e	Update memory map ; preliminary accel stuff to test (CW project missing, code resource INIT id 0 with the sysheap flag)	2022-05-15 14:43:15 +02:00